blob: edb5894ba5b34723aef68e9676c2c17f5e043322 [file] [log] [blame]
Andrey Petrov59e08342017-06-05 18:08:56 -07001/*
2 * This file is part of the coreboot project.
3 *
Rizwan Qureshi2488bea2018-09-18 22:53:44 +05304 * Copyright (C) 2018 Intel Corporation.
Andrey Petrov59e08342017-06-05 18:08:56 -07005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
Lijian Zhaoc319bab2017-07-08 18:16:13 -070016#include <cbfs.h>
17#include <console/console.h>
18#include <fsp/api.h>
19#include <soc/romstage.h>
20#include "spd/spd.h"
Lijian Zhaoc319bab2017-07-08 18:16:13 -070021#include <spd_bin.h>
22
23void mainboard_memory_init_params(FSPM_UPD *mupd)
24{
25 FSP_M_CONFIG *mem_cfg;
26 mem_cfg = &mupd->FspmConfig;
27 u8 spd_index;
28
29 mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0);
30 mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1);
31 mainboard_fill_dqs_map_ch0(&mem_cfg->DqsMapCpu2DramCh0);
32 mainboard_fill_dqs_map_ch1(&mem_cfg->DqsMapCpu2DramCh1);
33 mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
34 mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
35
Lijian Zhao14cb8282017-10-12 16:55:54 -070036 mem_cfg->DqPinsInterleaved = 0;
37 mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */
38 mem_cfg->ECT = 1; /* Early Command Training Enabled */
39 spd_index = 2;
Lijian Zhaoc319bab2017-07-08 18:16:13 -070040
41 struct region_device spd_rdev;
42
43 if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)
44 die("spd.bin not found\n");
45
46 mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev);
47 /* Memory leak is ok since we have memory mapped boot media */
48 mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);
49 mem_cfg->RefClk = 0; /* Auto Select CLK freq */
50 mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
51}