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Corey Osgoodc0eb5e02007-06-14 12:02:38 +00001/*
Stefan Reinauer7e61e452008-01-18 10:35:56 +00002 * This file is part of the coreboot project.
Corey Osgoodc0eb5e02007-06-14 12:02:38 +00003 *
Elia Yehuda76a88d02009-07-05 15:50:30 +00004 * Copyright (C) 2007-2009 Uwe Hermann <uwe@hermann-uwe.de>
Corey Osgoodc0eb5e02007-06-14 12:02:38 +00005 * Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
Elia Yehuda76a88d02009-07-05 15:50:30 +00006 * Copyright (C) 2008-2009 Elia Yehuda <z4ziggy@gmail.com>
Corey Osgoodc0eb5e02007-06-14 12:02:38 +00007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 */
22
23#include <spd.h>
Corey Osgoodc0eb5e02007-06-14 12:02:38 +000024#include <delay.h>
25#include "i82810.h"
26
27/*-----------------------------------------------------------------------------
28Macros and definitions.
29-----------------------------------------------------------------------------*/
30
Corey Osgoodc0eb5e02007-06-14 12:02:38 +000031/* Debugging macros. */
Stefan Reinauer3ac400e2010-03-30 22:12:59 +000032#define HAVE_ENOUGH_REGISTERS 0 /* Don't have enough registers to compile all
33 * debugging code with ROMCC
34 */
Uwe Hermann01ce6012010-03-05 10:03:50 +000035#if CONFIG_DEBUG_RAM_SETUP
Corey Osgoodc0eb5e02007-06-14 12:02:38 +000036#define PRINT_DEBUG(x) print_debug(x)
37#define PRINT_DEBUG_HEX8(x) print_debug_hex8(x)
38#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
39#define PRINT_DEBUG_HEX32(x) print_debug_hex32(x)
Stefan Reinauer3ac400e2010-03-30 22:12:59 +000040// no dump_pci_device in src/northbridge/intel/i82810/
41// #define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
42#define DUMPNORTH()
Corey Osgoodc0eb5e02007-06-14 12:02:38 +000043#else
44#define PRINT_DEBUG(x)
45#define PRINT_DEBUG_HEX8(x)
46#define PRINT_DEBUG_HEX16(x)
47#define PRINT_DEBUG_HEX32(x)
48#define DUMPNORTH()
49#endif
50
51/* DRAMT[7:5] - SDRAM Mode Select (SMS). */
Uwe Hermann8ab91d82008-11-18 12:02:03 +000052#define RAM_COMMAND_SELF_REFRESH 0x0 /* Disable refresh */
53#define RAM_COMMAND_NORMAL 0x1 /* Refresh: 15.6/11.7us for 100/133MHz */
54#define RAM_COMMAND_NORMAL_FR 0x2 /* Refresh: 7.8/5.85us for 100/133MHz */
55#define RAM_COMMAND_NOP 0x4 /* NOP command */
56#define RAM_COMMAND_PRECHARGE 0x5 /* All bank precharge */
57#define RAM_COMMAND_MRS 0x6 /* Mode register set */
58#define RAM_COMMAND_CBR 0x7 /* CBR */
Corey Osgoodc0eb5e02007-06-14 12:02:38 +000059
Elia Yehudad24fe7e2008-11-21 17:14:40 +000060/*
61 * Table which returns the RAM size in MB when fed the DRP[7:4] or [3:0] value.
62 * Note that 2 is a value which the DRP should never be programmed to.
63 * Some size values appear twice, due to single-sided vs dual-sided banks.
64 */
65static const u16 translate_i82810_to_mb[] = {
66/* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */
67/* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256,
68};
69
70/* Size of bank#0 for dual-sided DIMMs */
71static const u8 translate_i82810_to_bank[] = {
72/* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */
73/* MB */0, 0, 0, 8, 0, 16, 16, 0, 32, 32, 0, 64, 64, 0, 128, 128,
74};
75
Elia Yehudaa24e1dd2009-06-05 00:22:25 +000076struct dimm_info {
77 u8 ds; /* dual-sided */
78 u8 ss; /* single-sided */
79 u8 size;
80};
81
Corey Osgoodc0eb5e02007-06-14 12:02:38 +000082/*-----------------------------------------------------------------------------
83SDRAM configuration functions.
84-----------------------------------------------------------------------------*/
85
86/**
87 * Send the specified RAM command to all DIMMs.
88 *
Elia Yehudad24fe7e2008-11-21 17:14:40 +000089 * @param The RAM command to send to the DIMM(s).
Corey Osgoodc0eb5e02007-06-14 12:02:38 +000090 */
Elia Yehudad24fe7e2008-11-21 17:14:40 +000091static void do_ram_command(u8 command)
Corey Osgoodc0eb5e02007-06-14 12:02:38 +000092{
Elia Yehudad24fe7e2008-11-21 17:14:40 +000093 u32 addr, addr_offset;
94 u16 dimm_size, dimm_start, dimm_bank;
95 u8 reg8, drp;
96 int i, caslatency;
Corey Osgoodc0eb5e02007-06-14 12:02:38 +000097
98 /* Configure the RAM command. */
Elia Yehudad24fe7e2008-11-21 17:14:40 +000099 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), DRAMT);
100 reg8 &= 0x1f; /* Clear bits 7-5. */
101 reg8 |= command << 5;
102 pci_write_config8(PCI_DEV(0, 0, 0), DRAMT, reg8);
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000103
Elia Yehudad24fe7e2008-11-21 17:14:40 +0000104 /*
105 * RAM_COMMAND_NORMAL affects only the memory controller and
106 * doesn't need to be "sent" to the DIMMs.
107 */
108 if (command == RAM_COMMAND_NORMAL)
109 return;
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000110
Elia Yehudad24fe7e2008-11-21 17:14:40 +0000111 dimm_start = 0;
112 for (i = 0; i < DIMM_SOCKETS; i++) {
113 /*
114 * Calculate the address offset where we need to "send" the
115 * DIMM command to. For most commands the offset is 0, only
116 * RAM_COMMAND_MRS needs special values, see below.
117 * The final address offset bits depend on three things:
118 *
119 * (1) Some hardcoded values specified in the datasheet.
120 * (2) Which CAS latency we will use/set. This is the SMAA[4]
121 * bit, which is 1 for CL3, and 0 for CL2. The bitstring
122 * so far has the form '00000001X1010', X being SMAA[4].
123 * (3) The DIMM to which we want to send the command. For
124 * DIMM0 no special handling is needed, but for DIMM1 we
125 * must invert the four bits SMAA[7:4] (see datasheet).
126 *
127 * Finally, the bitstring has to be shifted 3 bits to the left.
128 * See i810 datasheet pages 43, 85, and 86 for details.
129 */
130 addr_offset = 0;
131 caslatency = 3; /* TODO: Dynamically get CAS latency later. */
132 if (i == 0 && command == RAM_COMMAND_MRS && caslatency == 3)
133 addr_offset = 0x1d0; /* DIMM0, CL3, 0000111010000 */
134 if (i == 1 && command == RAM_COMMAND_MRS && caslatency == 3)
135 addr_offset = 0x650; /* DIMM1, CL3, 0011001010000 */
136 if (i == 0 && command == RAM_COMMAND_MRS && caslatency == 2)
137 addr_offset = 0x150; /* DIMM0, CL2, 0000101010000 */
138 if (i == 1 && command == RAM_COMMAND_MRS && caslatency == 2)
139 addr_offset = 0x1a0; /* DIMM1, CL2, 0000110100000 */
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000140
Elia Yehudad24fe7e2008-11-21 17:14:40 +0000141 drp = pci_read_config8(PCI_DEV(0, 0, 0), DRP);
142 drp = (drp >> (i * 4)) & 0x0f;
143
144 dimm_size = translate_i82810_to_mb[drp];
Elia Yehudad24fe7e2008-11-21 17:14:40 +0000145 if (dimm_size) {
Stefan Reinauer3ac400e2010-03-30 22:12:59 +0000146 addr = (dimm_start * 1024 * 1024) + addr_offset;
147#if HAVE_ENOUGH_REGISTERS
Elia Yehudad24fe7e2008-11-21 17:14:40 +0000148 PRINT_DEBUG(" Sending RAM command 0x");
149 PRINT_DEBUG_HEX8(reg8);
150 PRINT_DEBUG(" to 0x");
151 PRINT_DEBUG_HEX32(addr);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000152 PRINT_DEBUG("\n");
Stefan Reinauer3ac400e2010-03-30 22:12:59 +0000153#endif
Elia Yehudad24fe7e2008-11-21 17:14:40 +0000154
155 read32(addr);
156 }
157
158 dimm_bank = translate_i82810_to_bank[drp];
Elia Yehudad24fe7e2008-11-21 17:14:40 +0000159 if (dimm_bank) {
Stefan Reinauer3ac400e2010-03-30 22:12:59 +0000160 addr = ((dimm_start + dimm_bank) * 1024 * 1024) + addr_offset;
161#if HAVE_ENOUGH_REGISTERS
Elia Yehudad24fe7e2008-11-21 17:14:40 +0000162 PRINT_DEBUG(" Sending RAM command 0x");
163 PRINT_DEBUG_HEX8(reg8);
164 PRINT_DEBUG(" to 0x");
165 PRINT_DEBUG_HEX32(addr);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000166 PRINT_DEBUG("\n");
Stefan Reinauer3ac400e2010-03-30 22:12:59 +0000167#endif
Elia Yehudad24fe7e2008-11-21 17:14:40 +0000168 read32(addr);
169 }
170
171 dimm_start += dimm_size;
172 }
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000173}
174
175/*-----------------------------------------------------------------------------
176DIMM-independant configuration functions.
177-----------------------------------------------------------------------------*/
178
Uwe Hermann8ab91d82008-11-18 12:02:03 +0000179/*
180 * Set DRP - DRAM Row Population Register (Device 0).
181 */
Elia Yehudad24fe7e2008-11-21 17:14:40 +0000182static void spd_set_dram_size(void)
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000183{
184 /* The variables drp and dimm_size have to be ints since all the
185 * SMBus-related functions return ints, and its just easier this way.
186 */
187 int i, drp, dimm_size;
188
189 drp = 0x00;
Uwe Hermanndfb3c132007-06-19 22:47:11 +0000190
191 for (i = 0; i < DIMM_SOCKETS; i++) {
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000192 /* First check if a DIMM is actually present. */
Uwe Hermann4cf5ecf2008-11-20 23:18:10 +0000193 if (smbus_read_byte(DIMM_SPD_BASE + i, 2) == 4) {
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000194 print_debug("Found DIMM in slot ");
195 print_debug_hex8(i);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000196 print_debug("\n");
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000197
Uwe Hermann4cf5ecf2008-11-20 23:18:10 +0000198 dimm_size = smbus_read_byte(DIMM_SPD_BASE + i, 31);
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000199
200 /* WISHLIST: would be nice to display it as decimal? */
201 print_debug("DIMM is 0x");
202 print_debug_hex8(dimm_size * 4);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000203 print_debug("MB\n");
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000204
205 /* The i810 can't handle DIMMs larger than 128MB per
206 * side. This will fail if the DIMM uses a
207 * non-supported DRAM tech, and can't be used until
208 * buffers are done dynamically.
Uwe Hermanndfb3c132007-06-19 22:47:11 +0000209 * Note: the factory BIOS just dies if it spots this :D
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000210 */
Uwe Hermanndfb3c132007-06-19 22:47:11 +0000211 if (dimm_size > 32) {
212 print_err("DIMM row sizes larger than 128MB not"
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000213 "supported on i810\n");
Uwe Hermanndfb3c132007-06-19 22:47:11 +0000214 print_err
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000215 ("Attempting to treat as 128MB DIMM\n");
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000216 dimm_size = 32;
217 }
218
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000219 /* This array is provided in raminit.h, because it got
220 * extremely messy. The above way is cleaner, but
221 * doesn't support any asymetrical/odd configurations.
222 */
223 dimm_size = translate_spd_to_i82810[dimm_size];
224
225 print_debug("After translation, dimm_size is 0x");
226 print_debug_hex8(dimm_size);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000227 print_debug("\n");
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000228
229 /* If the DIMM is dual-sided, the DRP value is +2 */
Uwe Hermanndfb3c132007-06-19 22:47:11 +0000230 /* TODO: Figure out asymetrical configurations. */
Uwe Hermann4cf5ecf2008-11-20 23:18:10 +0000231 if ((smbus_read_byte(DIMM_SPD_BASE + i, 127) | 0xf) ==
Uwe Hermanndfb3c132007-06-19 22:47:11 +0000232 0xff) {
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000233 print_debug("DIMM is dual-sided\n");
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000234 dimm_size += 2;
235 }
236 } else {
237 print_debug("No DIMM found in slot ");
238 print_debug_hex8(i);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000239 print_debug("\n");
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000240
Uwe Hermanndfb3c132007-06-19 22:47:11 +0000241 /* If there's no DIMM in the slot, set value to 0. */
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000242 dimm_size = 0x00;
243 }
244
245 /* Put in dimm_size to reflect the current DIMM. */
246 drp |= dimm_size << (i * 4);
247 }
248
249 print_debug("DRP calculated to 0x");
250 print_debug_hex8(drp);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000251 print_debug("\n");
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000252
Uwe Hermann4cf5ecf2008-11-20 23:18:10 +0000253 pci_write_config8(PCI_DEV(0, 0, 0), DRP, drp);
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000254}
255
Uwe Hermann4cf5ecf2008-11-20 23:18:10 +0000256static void set_dram_timing(void)
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000257{
258 /* TODO, for now using default, hopefully safe values. */
Uwe Hermann4cf5ecf2008-11-20 23:18:10 +0000259 // pci_write_config8(PCI_DEV(0, 0, 0), DRAMT, 0x00);
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000260}
261
Uwe Hermann8ab91d82008-11-18 12:02:03 +0000262/*
263 * TODO: BUFF_SC needs to be set according to the DRAM tech (x8, x16,
Elia Yehudad24fe7e2008-11-21 17:14:40 +0000264 * or x32), but the datasheet doesn't list all the details. Currently, it
Uwe Hermann8ab91d82008-11-18 12:02:03 +0000265 * needs to be pulled from the output of 'lspci -xxx Rx92'.
266 *
267 * Common results (tested on actual hardware) are:
268 *
269 * (DRP: c = 128MB dual sided, d = 128MB single sided, f = 256MB dual sided)
270 *
271 * BUFF_SC TOM DRP DIMM0 DIMM1
272 * ----------------------------------------------------------------------------
273 * 0x3356 128MB 0x0c 128MB dual-sided -
274 * 0xcc56 128MB 0xc0 - 128MB dual-sided
275 * 0x77da 128MB 0x0d 128MB single-sided -
276 * 0xddda 128MB 0xd0 - 128MB single-sided
277 * 0x0001 256MB 0xcc 128MB dual-sided 128MB dual-sided
278 * 0x55c6 256MB 0xdd 128MB single-sided 128MB single-sided
279 * 0x4445 256MB 0xcd 128MB single-sided 128MB dual-sided
280 * 0x1145 256MB 0xdc 128MB dual-sided 128MB single-sided
281 * 0x3356 256MB 0x0f 256MB dual-sided -
282 * 0xcc56 256MB 0xf0 - 256MB dual-sided
283 * 0x0001 384MB 0xcf 256MB dual-sided 128MB dual-sided
284 * 0x0001 384MB 0xfc 128MB dual-sided 256MB dual-sided
285 * 0x1145 384MB 0xdf 256MB dual-sided 128MB single-sided
286 * 0x4445 384MB 0xfd 128MB single-sided 256MB dual-sided
287 * 0x0001 512MB 0xff 256MB dual-sided 256MB dual-sided
Elia Yehudaa24e1dd2009-06-05 00:22:25 +0000288 *
289 * See also:
290 * http://www.coreboot.org/pipermail/coreboot/2009-May/047966.html
Uwe Hermann8ab91d82008-11-18 12:02:03 +0000291 */
Uwe Hermann4cf5ecf2008-11-20 23:18:10 +0000292static void set_dram_buffer_strength(void)
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000293{
Elia Yehudaa24e1dd2009-06-05 00:22:25 +0000294 struct dimm_info d0, d1;
295 u16 buff_sc;
296
297 /* Check first slot. */
298 d0.size = d0.ds = d0.ss = 0;
299 if (smbus_read_byte(DIMM_SPD_BASE, SPD_MEMORY_TYPE)
300 == SPD_MEMORY_TYPE_SDRAM) {
301 d0.size = smbus_read_byte(DIMM_SPD_BASE, SPD_BANK_DENSITY);
302 d0.ds = smbus_read_byte(DIMM_SPD_BASE, SPD_NUM_DIMM_BANKS) > 1;
303 d0.ss = !d0.ds;
304 }
305
306 /* Check second slot. */
307 d1.size = d1.ds = d1.ss = 0;
308 if (smbus_read_byte(DIMM_SPD_BASE + 1, SPD_MEMORY_TYPE)
309 == SPD_MEMORY_TYPE_SDRAM) {
310 d1.size = smbus_read_byte(DIMM_SPD_BASE + 1, SPD_BANK_DENSITY);
311 d1.ds = smbus_read_byte(DIMM_SPD_BASE + 1,
312 SPD_NUM_DIMM_BANKS) > 1;
313 d1.ss = !d1.ds;
314 }
315
316 buff_sc = 0;
317
318 /* Tame the beast... */
319 if ((d0.ds && d1.ds) || (d0.ds && d1.ss) || (d0.ss && d1.ds))
320 buff_sc |= 1;
321 if ((d0.size && !d1.size) || (!d0.size && d1.size) || (d0.ss && d1.ss))
322 buff_sc |= 1 << 1;
323 if ((d0.ds && !d1.size) || (!d0.size && d1.ds) || (d0.ss && d1.ss)
324 || (d0.ds && d1.ss) || (d0.ss && d1.ds))
325 buff_sc |= 1 << 2;
326 if ((d0.ss && !d1.size) || (!d0.size && d1.ss))
327 buff_sc |= 1 << 3;
328 if ((d0.size && !d1.size) || (!d0.size && d1.size))
329 buff_sc |= 1 << 4;
330 if ((d0.ds && !d1.size) || (!d0.size && d1.ds) || (d0.ds && d1.ss)
331 || (d0.ss && d1.ds))
332 buff_sc |= 1 << 6;
333 if ((d0.ss && !d1.size) || (!d0.size && d1.ss) || (d0.ss && d1.ss))
334 buff_sc |= 3 << 6;
335 if ((!d0.size && d1.ss) || (d0.ds && d1.ss) || (d0.ss && d1.ss))
336 buff_sc |= 1 << 8;
337 if (d0.size && !d1.size)
338 buff_sc |= 3 << 8;
339 if ((d0.ss && !d1.size) || (d0.ss && d1.ss) || (d0.ss && d1.ds))
340 buff_sc |= 1 << 10;
341 if (!d0.size && d1.size)
342 buff_sc |= 3 << 10;
343 if ((d0.size && !d1.size) || (d0.ss && !d1.size) || (!d0.size && d1.ss)
344 || (d0.ss && d1.ss) || (d0.ds && d1.ss))
345 buff_sc |= 1 << 12;
346 if (d0.size && !d1.size)
347 buff_sc |= 1 << 13;
348 if ((!d0.size && d1.size) || (d0.ss && !d1.size) || (d0.ss && d1.ss)
349 || (d0.ss && d1.ds))
350 buff_sc |= 1 << 14;
351 if (!d0.size && d1.size)
352 buff_sc |= 1 << 15;
353
354 print_debug("BUFF_SC calculated to 0x");
355 print_debug_hex16(buff_sc);
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000356 print_debug("\n");
Elia Yehudaa24e1dd2009-06-05 00:22:25 +0000357
358 pci_write_config16(PCI_DEV(0, 0, 0), BUFF_SC, buff_sc);
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000359}
360
361/*-----------------------------------------------------------------------------
362Public interface.
363-----------------------------------------------------------------------------*/
364
Uwe Hermann4cf5ecf2008-11-20 23:18:10 +0000365static void sdram_set_registers(void)
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000366{
Elia Yehuda76a88d02009-07-05 15:50:30 +0000367 u8 reg8;
368 u16 reg16, did;
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000369
Elia Yehuda76a88d02009-07-05 15:50:30 +0000370 did = pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000371
372 /* Ideally, this should be R/W for as many ranges as possible. */
Elia Yehuda76a88d02009-07-05 15:50:30 +0000373 pci_write_config8(PCI_DEV(0, 0, 0), PAMR, 0xff);
Corey Osgoodcbb8d8a2007-06-19 07:33:39 +0000374
Elia Yehuda76a88d02009-07-05 15:50:30 +0000375 /* Set size for onboard-VGA framebuffer. */
376 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), SMRAM);
377 reg8 &= 0x3f; /* Disable graphics (for now). */
Myles Watsonec0ee642009-10-19 16:21:30 +0000378#if CONFIG_VIDEO_MB
Elia Yehuda76a88d02009-07-05 15:50:30 +0000379 if (CONFIG_VIDEO_MB == 512)
380 reg8 |= (1 << 7); /* Enable graphics (512KB RAM). */
381 else if (CONFIG_VIDEO_MB == 1)
382 reg8 |= (1 << 7) | (1 << 6); /* Enable graphics (1MB RAM). */
Uwe Hermann3f1458d2009-07-05 16:23:43 +0000383#endif
Elia Yehuda76a88d02009-07-05 15:50:30 +0000384 pci_write_config8(PCI_DEV(0, 0, 0), SMRAM, reg8);
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000385
Elia Yehuda76a88d02009-07-05 15:50:30 +0000386 /* MISSC2: Bits 1, 2, 6, 7 must be set for VGA (see datasheet). */
387 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), MISSC2);
388 reg8 |= (1 << 1); /* Instruction Parser Unit-Level Clock Gating */
389 reg8 |= (1 << 2); /* Palette Load Select */
390 if (did == 0x7124) {
391 /* Bits 6 and 7 are only available on 82810E (not 82810). */
392 reg8 |= (1 << 6); /* Text Immediate Blit */
393 reg8 |= (1 << 7); /* Must be 1 as per datasheet. */
394 }
395 pci_write_config8(PCI_DEV(0, 0, 0), MISSC2, reg8);
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000396}
397
Uwe Hermann4cf5ecf2008-11-20 23:18:10 +0000398static void sdram_set_spd_registers(void)
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000399{
Elia Yehudad24fe7e2008-11-21 17:14:40 +0000400 spd_set_dram_size();
Uwe Hermann4cf5ecf2008-11-20 23:18:10 +0000401 set_dram_buffer_strength();
Uwe Hermann4cf5ecf2008-11-20 23:18:10 +0000402 set_dram_timing();
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000403}
404
405/**
406 * Enable SDRAM.
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000407 */
Uwe Hermann4cf5ecf2008-11-20 23:18:10 +0000408static void sdram_enable(void)
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000409{
410 int i;
411
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000412 /* 1. Apply NOP. */
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000413 PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
Elia Yehudad24fe7e2008-11-21 17:14:40 +0000414 do_ram_command(RAM_COMMAND_NOP);
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000415 udelay(200);
416
417 /* 2. Precharge all. Wait tRP. */
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000418 PRINT_DEBUG("RAM Enable 2: Precharge all\n");
Elia Yehudad24fe7e2008-11-21 17:14:40 +0000419 do_ram_command(RAM_COMMAND_PRECHARGE);
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000420 udelay(1);
421
422 /* 3. Perform 8 refresh cycles. Wait tRC each time. */
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000423 PRINT_DEBUG("RAM Enable 3: CBR\n");
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000424 for (i = 0; i < 8; i++) {
Elia Yehudad24fe7e2008-11-21 17:14:40 +0000425 do_ram_command(RAM_COMMAND_CBR);
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000426 udelay(1);
427 }
428
429 /* 4. Mode register set. Wait two memory cycles. */
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000430 PRINT_DEBUG("RAM Enable 4: Mode register set\n");
Elia Yehudad24fe7e2008-11-21 17:14:40 +0000431 do_ram_command(RAM_COMMAND_MRS);
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000432 udelay(2);
433
Elia Yehuda76a88d02009-07-05 15:50:30 +0000434 /* 5. Normal operation (enables refresh at 15.6usec). */
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000435 PRINT_DEBUG("RAM Enable 5: Normal operation\n");
Elia Yehudad24fe7e2008-11-21 17:14:40 +0000436 do_ram_command(RAM_COMMAND_NORMAL);
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000437 udelay(1);
438
Stefan Reinauer64ed2b72010-03-31 14:47:43 +0000439 PRINT_DEBUG("Northbridge following SDRAM init:\n");
Corey Osgoodc0eb5e02007-06-14 12:02:38 +0000440 DUMPNORTH();
441}