Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * 2012 secunet Security Networks AG |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pciexp.h> |
| 22 | #include <device/pci_ids.h> |
| 23 | #include <southbridge/intel/common/pciehp.h> |
| 24 | #include "chip.h" |
| 25 | |
| 26 | static void pci_init(struct device *dev) |
| 27 | { |
| 28 | u16 reg16; |
| 29 | u32 reg32; |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 30 | struct southbridge_intel_i82801jx_config *config = dev->chip_info; |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 31 | |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 32 | printk(BIOS_DEBUG, "Initializing ICH10 PCIe root port.\n"); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 33 | |
| 34 | /* Enable Bus Master */ |
| 35 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 36 | reg32 |= PCI_COMMAND_MASTER; |
| 37 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 38 | |
| 39 | /* Set Cache Line Size to 0x10 */ |
| 40 | // This has no effect but the OS might expect it |
| 41 | pci_write_config8(dev, 0x0c, 0x10); |
| 42 | |
| 43 | reg16 = pci_read_config16(dev, 0x3e); |
| 44 | reg16 &= ~(1 << 0); /* disable parity error response */ |
| 45 | reg16 |= (1 << 2); /* ISA enable */ |
| 46 | pci_write_config16(dev, 0x3e, reg16); |
| 47 | |
| 48 | /* Enable IO xAPIC on this PCIe port */ |
| 49 | reg32 = pci_read_config32(dev, 0xd8); |
| 50 | reg32 |= (1 << 7); |
| 51 | pci_write_config32(dev, 0xd8, reg32); |
| 52 | |
| 53 | /* Enable Backbone Clock Gating */ |
| 54 | reg32 = pci_read_config32(dev, 0xe1); |
| 55 | reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0); |
| 56 | pci_write_config32(dev, 0xe1, reg32); |
| 57 | |
| 58 | /* Set VC0 transaction class */ |
| 59 | reg32 = pci_read_config32(dev, 0x114); |
| 60 | reg32 &= 0xffffff00; |
| 61 | reg32 |= 1; |
| 62 | pci_write_config32(dev, 0x114, reg32); |
| 63 | |
| 64 | /* Mask completion timeouts */ |
| 65 | reg32 = pci_read_config32(dev, 0x148); |
| 66 | reg32 |= (1 << 14); |
| 67 | pci_write_config32(dev, 0x148, reg32); |
| 68 | |
| 69 | /* Lock R/WO Correctable Error Mask. */ |
| 70 | pci_write_config32(dev, 0x154, pci_read_config32(dev, 0x154)); |
| 71 | |
| 72 | /* Clear errors in status registers */ |
| 73 | reg16 = pci_read_config16(dev, 0x06); |
| 74 | pci_write_config16(dev, 0x06, reg16); |
| 75 | reg16 = pci_read_config16(dev, 0x1e); |
| 76 | pci_write_config16(dev, 0x1e, reg16); |
| 77 | |
| 78 | /* Get configured ASPM state */ |
| 79 | const enum aspm_type apmc = pci_read_config32(dev, 0x50) & 3; |
| 80 | |
| 81 | /* If both L0s and L1 enabled then set root port 0xE8[1]=1 */ |
| 82 | if (apmc == PCIE_ASPM_BOTH) { |
| 83 | reg32 = pci_read_config32(dev, 0xe8); |
| 84 | reg32 |= (1 << 1); |
| 85 | pci_write_config32(dev, 0xe8, reg32); |
| 86 | } |
| 87 | |
| 88 | /* Enable expresscard hotplug events. */ |
| 89 | if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { |
| 90 | pci_write_config32(dev, 0xd8, |
| 91 | pci_read_config32(dev, 0xd8) |
| 92 | | (1 << 30)); |
| 93 | pci_write_config16(dev, 0x42, 0x142); |
| 94 | } |
| 95 | } |
| 96 | |
Elyes HAOUAS | 1a8c1df | 2018-05-13 13:36:44 +0200 | [diff] [blame] | 97 | static void pcie_set_subsystem(struct device *dev, unsigned vendor, |
| 98 | unsigned device) |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 99 | { |
| 100 | /* NOTE: 0x94 is not the default position! */ |
| 101 | if (!vendor || !device) { |
| 102 | pci_write_config32(dev, 0x94, |
| 103 | pci_read_config32(dev, 0)); |
| 104 | } else { |
| 105 | pci_write_config32(dev, 0x94, |
| 106 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 107 | } |
| 108 | } |
| 109 | |
Elyes HAOUAS | 1a8c1df | 2018-05-13 13:36:44 +0200 | [diff] [blame] | 110 | static void pch_pciexp_scan_bridge(struct device *dev) |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 111 | { |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 112 | struct southbridge_intel_i82801jx_config *config = dev->chip_info; |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 113 | |
| 114 | /* Normal PCIe Scan */ |
| 115 | pciexp_scan_bridge(dev); |
| 116 | |
| 117 | if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { |
| 118 | intel_acpi_pcie_hotplug_scan_slot(dev->link_list); |
| 119 | } |
| 120 | } |
| 121 | |
| 122 | static struct pci_operations pci_ops = { |
| 123 | .set_subsystem = pcie_set_subsystem, |
| 124 | }; |
| 125 | |
| 126 | static struct device_operations device_ops = { |
| 127 | .read_resources = pci_bus_read_resources, |
| 128 | .set_resources = pci_dev_set_resources, |
| 129 | .enable_resources = pci_bus_enable_resources, |
| 130 | .init = pci_init, |
| 131 | .scan_bus = pch_pciexp_scan_bridge, |
| 132 | .ops_pci = &pci_ops, |
| 133 | }; |
| 134 | |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 135 | /* 82801lJx, ICH10 */ |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 136 | static const unsigned short pci_device_ids[] = { |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 137 | 0x3a40, /* Port 1 */ |
| 138 | 0x3a42, /* Port 2 */ |
| 139 | 0x3a44, /* Port 3 */ |
| 140 | 0x3a46, /* Port 4 */ |
| 141 | 0x3a48, /* Port 5 */ |
| 142 | 0x3a4a, /* Port 6 */ |
| 143 | |
| 144 | 0x3a70, /* Port 1 */ |
| 145 | 0x3a72, /* Port 2 */ |
| 146 | 0x3a74, /* Port 3 */ |
| 147 | 0x3a76, /* Port 4 */ |
| 148 | 0x3a78, /* Port 5 */ |
| 149 | 0x3a7a, /* Port 6 */ |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 150 | 0 |
| 151 | }; |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 152 | |
| 153 | static const struct pci_driver ich10_pcie __pci_driver = { |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 154 | .ops = &device_ops, |
| 155 | .vendor = PCI_VENDOR_ID_INTEL, |
| 156 | .devices = pci_device_ids, |
| 157 | }; |