Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <arch/io.h> |
| 17 | #include <cbmem.h> |
| 18 | #include <console/console.h> |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pciexp.h> |
| 22 | #include <device/pci_ids.h> |
| 23 | #include <stdlib.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 24 | #include <soc/iobp.h> |
| 25 | #include <soc/nvs.h> |
| 26 | #include <soc/pci_devs.h> |
| 27 | #include <soc/pch.h> |
| 28 | #include <soc/ramstage.h> |
| 29 | #include <soc/rcba.h> |
| 30 | #include <soc/serialio.h> |
| 31 | #include <soc/intel/broadwell/chip.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 32 | |
| 33 | /* Set D3Hot Power State in ACPI mode */ |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 34 | static void serialio_enable_d3hot(struct resource *res) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 35 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 36 | u32 reg32 = read32(res2mmio(res, PCH_PCS, 0)); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 37 | reg32 |= PCH_PCS_PS_D3HOT; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 38 | write32(res2mmio(res, PCH_PCS, 0), reg32); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 39 | } |
| 40 | |
| 41 | static int serialio_uart_is_debug(struct device *dev) |
| 42 | { |
Martin Roth | e6ff159 | 2017-06-24 21:34:29 -0600 | [diff] [blame] | 43 | #if IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE) |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 44 | switch (dev->path.pci.devfn) { |
| 45 | case PCH_DEVFN_UART0: /* UART0 */ |
| 46 | return !!(CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 0); |
| 47 | case PCH_DEVFN_UART1: /* UART1 */ |
| 48 | return !!(CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 1); |
| 49 | } |
| 50 | #endif |
| 51 | return 0; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 52 | } |
| 53 | |
| 54 | /* Enable clock in PCI mode */ |
| 55 | static void serialio_enable_clock(struct resource *bar0) |
| 56 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 57 | u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0)); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 58 | reg32 |= SIO_REG_PPR_CLOCK_EN; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 59 | write32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0), reg32); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 60 | } |
| 61 | |
| 62 | /* Put Serial IO D21:F0-F6 device into desired mode. */ |
| 63 | static void serialio_d21_mode(int sio_index, int int_pin, int acpi_mode) |
| 64 | { |
| 65 | u32 portctrl = SIO_IOBP_PORTCTRL_PM_CAP_PRSNT; |
| 66 | |
| 67 | /* Snoop select 1. */ |
| 68 | portctrl |= SIO_IOBP_PORTCTRL_SNOOP_SELECT(1); |
| 69 | |
| 70 | /* Set interrupt pin. */ |
| 71 | portctrl |= SIO_IOBP_PORTCTRL_INT_PIN(int_pin); |
| 72 | |
| 73 | if (acpi_mode) { |
| 74 | /* Enable ACPI interrupt mode. */ |
| 75 | portctrl |= SIO_IOBP_PORTCTRL_ACPI_IRQ_EN; |
| 76 | |
| 77 | /* Disable PCI config space. */ |
| 78 | portctrl |= SIO_IOBP_PORTCTRL_PCI_CONF_DIS; |
| 79 | } |
| 80 | |
| 81 | pch_iobp_update(SIO_IOBP_PORTCTRLX(sio_index), 0, portctrl); |
| 82 | } |
| 83 | |
| 84 | /* Put Serial IO D23:F0 device into desired mode. */ |
| 85 | static void serialio_d23_mode(int acpi_mode) |
| 86 | { |
| 87 | u32 portctrl = 0; |
| 88 | |
| 89 | /* Snoop select 1. */ |
| 90 | pch_iobp_update(SIO_IOBP_PORTCTRL1, 0, |
| 91 | SIO_IOBP_PORTCTRL1_SNOOP_SELECT(1)); |
| 92 | |
| 93 | if (acpi_mode) { |
| 94 | /* Enable ACPI interrupt mode. */ |
| 95 | portctrl |= SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN; |
| 96 | |
| 97 | /* Disable PCI config space. */ |
| 98 | portctrl |= SIO_IOBP_PORTCTRL0_PCI_CONF_DIS; |
| 99 | } |
| 100 | |
| 101 | pch_iobp_update(SIO_IOBP_PORTCTRL0, 0, portctrl); |
| 102 | } |
| 103 | |
| 104 | /* Enable LTR Auto Mode for D21:F1-F6. */ |
| 105 | static void serialio_d21_ltr(struct resource *bar0) |
| 106 | { |
| 107 | u32 reg; |
| 108 | |
| 109 | /* 1. Program BAR0 + 808h[2] = 0b */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 110 | reg = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0)); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 111 | reg &= ~SIO_REG_PPR_GEN_LTR_MODE_MASK; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 112 | write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 113 | |
| 114 | /* 2. Program BAR0 + 804h[1:0] = 00b */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 115 | reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0)); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 116 | reg &= ~SIO_REG_PPR_RST_ASSERT; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 117 | write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 118 | |
| 119 | /* 3. Program BAR0 + 804h[1:0] = 11b */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 120 | reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0)); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 121 | reg |= SIO_REG_PPR_RST_ASSERT; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 122 | write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 123 | |
| 124 | /* 4. Program BAR0 + 814h[31:0] = 00000000h */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 125 | write32(res2mmio(bar0, SIO_REG_AUTO_LTR, 0), 0); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 126 | } |
| 127 | |
| 128 | /* Enable LTR Auto Mode for D23:F0. */ |
| 129 | static void serialio_d23_ltr(struct resource *bar0) |
| 130 | { |
| 131 | u32 reg; |
| 132 | |
| 133 | /* Program BAR0 + 1008h[2] = 1b */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 134 | reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0)); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 135 | reg |= SIO_REG_PPR_GEN_LTR_MODE_MASK; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 136 | write32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0), reg); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 137 | |
| 138 | /* Program BAR0 + 1010h = 0x00000000 */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 139 | write32(res2mmio(bar0, SIO_REG_SDIO_PPR_SW_LTR, 0), 0); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 140 | |
| 141 | /* Program BAR0 + 3Ch[30] = 1b */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 142 | reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0)); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 143 | reg |= SIO_REG_SDIO_PPR_CMD12_B30; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 144 | write32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0), reg); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 145 | } |
| 146 | |
| 147 | /* Select I2C voltage of 1.8V or 3.3V. */ |
| 148 | static void serialio_i2c_voltage_sel(struct resource *bar0, u8 voltage) |
| 149 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 150 | u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0)); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 151 | reg32 &= ~SIO_REG_PPR_GEN_VOLTAGE_MASK; |
| 152 | reg32 |= SIO_REG_PPR_GEN_VOLTAGE(voltage); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 153 | write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg32); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 154 | } |
| 155 | |
| 156 | /* Init sequence to be run once, done as part of D21:F0 (SDMA) init. */ |
| 157 | static void serialio_init_once(int acpi_mode) |
| 158 | { |
| 159 | if (acpi_mode) { |
| 160 | /* Enable ACPI IRQ for IRQ13, IRQ7, IRQ6, IRQ5 in RCBA. */ |
| 161 | RCBA32_OR(ACPIIRQEN, (1 << 13)|(1 << 7)|(1 << 6)|(1 << 5)); |
| 162 | } |
| 163 | |
| 164 | /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b. */ |
| 165 | pch_iobp_update(SIO_IOBP_GPIODF, ~0x0000131f, 0x0000131f); |
| 166 | |
| 167 | /* Program IOBP CB000180h[5:0] = 111111b (undefined register) */ |
| 168 | pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f); |
| 169 | } |
| 170 | |
| 171 | static void serialio_init(struct device *dev) |
| 172 | { |
| 173 | config_t *config = dev->chip_info; |
| 174 | struct resource *bar0, *bar1; |
| 175 | int sio_index = -1; |
| 176 | u32 reg32; |
| 177 | |
| 178 | printk(BIOS_DEBUG, "Initializing Serial IO device\n"); |
| 179 | |
| 180 | /* Ensure memory and bus master are enabled */ |
| 181 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 182 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
| 183 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 184 | |
| 185 | /* Find BAR0 and BAR1 */ |
| 186 | bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 187 | if (!bar0) |
| 188 | return; |
| 189 | bar1 = find_resource(dev, PCI_BASE_ADDRESS_1); |
| 190 | if (!bar1) |
| 191 | return; |
| 192 | |
| 193 | if (!config->sio_acpi_mode) |
| 194 | serialio_enable_clock(bar0); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 195 | |
| 196 | switch (dev->path.pci.devfn) { |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 197 | case PCH_DEVFN_SDMA: /* SDMA */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 198 | sio_index = SIO_ID_SDMA; |
| 199 | serialio_init_once(config->sio_acpi_mode); |
| 200 | serialio_d21_mode(sio_index, SIO_PIN_INTB, |
| 201 | config->sio_acpi_mode); |
| 202 | break; |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 203 | case PCH_DEVFN_I2C0: /* I2C0 */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 204 | sio_index = SIO_ID_I2C0; |
| 205 | serialio_d21_ltr(bar0); |
| 206 | serialio_i2c_voltage_sel(bar0, config->sio_i2c0_voltage); |
| 207 | serialio_d21_mode(sio_index, SIO_PIN_INTC, |
| 208 | config->sio_acpi_mode); |
| 209 | break; |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 210 | case PCH_DEVFN_I2C1: /* I2C1 */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 211 | sio_index = SIO_ID_I2C1; |
| 212 | serialio_d21_ltr(bar0); |
| 213 | serialio_i2c_voltage_sel(bar0, config->sio_i2c1_voltage); |
| 214 | serialio_d21_mode(sio_index, SIO_PIN_INTC, |
| 215 | config->sio_acpi_mode); |
| 216 | break; |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 217 | case PCH_DEVFN_SPI0: /* SPI0 */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 218 | sio_index = SIO_ID_SPI0; |
| 219 | serialio_d21_ltr(bar0); |
| 220 | serialio_d21_mode(sio_index, SIO_PIN_INTC, |
| 221 | config->sio_acpi_mode); |
| 222 | break; |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 223 | case PCH_DEVFN_SPI1: /* SPI1 */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 224 | sio_index = SIO_ID_SPI1; |
| 225 | serialio_d21_ltr(bar0); |
| 226 | serialio_d21_mode(sio_index, SIO_PIN_INTC, |
| 227 | config->sio_acpi_mode); |
| 228 | break; |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 229 | case PCH_DEVFN_UART0: /* UART0 */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 230 | sio_index = SIO_ID_UART0; |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 231 | if (!serialio_uart_is_debug(dev)) |
| 232 | serialio_d21_ltr(bar0); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 233 | serialio_d21_mode(sio_index, SIO_PIN_INTD, |
| 234 | config->sio_acpi_mode); |
| 235 | break; |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 236 | case PCH_DEVFN_UART1: /* UART1 */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 237 | sio_index = SIO_ID_UART1; |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 238 | if (!serialio_uart_is_debug(dev)) |
| 239 | serialio_d21_ltr(bar0); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 240 | serialio_d21_mode(sio_index, SIO_PIN_INTD, |
| 241 | config->sio_acpi_mode); |
| 242 | break; |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 243 | case PCH_DEVFN_SDIO: /* SDIO */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 244 | sio_index = SIO_ID_SDIO; |
| 245 | serialio_d23_ltr(bar0); |
| 246 | serialio_d23_mode(config->sio_acpi_mode); |
| 247 | break; |
| 248 | default: |
| 249 | return; |
| 250 | } |
| 251 | |
| 252 | if (config->sio_acpi_mode) { |
| 253 | global_nvs_t *gnvs; |
| 254 | |
| 255 | /* Find ACPI NVS to update BARs */ |
| 256 | gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 257 | if (!gnvs) { |
| 258 | printk(BIOS_ERR, "Unable to locate Global NVS\n"); |
| 259 | return; |
| 260 | } |
| 261 | |
| 262 | /* Save BAR0 and BAR1 to ACPI NVS */ |
| 263 | gnvs->dev.bar0[sio_index] = (u32)bar0->base; |
| 264 | gnvs->dev.bar1[sio_index] = (u32)bar1->base; |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 265 | |
| 266 | /* Do not enable UART if it is used as debug port */ |
| 267 | if (!serialio_uart_is_debug(dev)) |
| 268 | gnvs->dev.enable[sio_index] = 1; |
| 269 | |
| 270 | /* Put device in D3hot state via BAR1 */ |
| 271 | if (dev->path.pci.devfn != PCH_DEVFN_SDMA) |
| 272 | serialio_enable_d3hot(bar1); /* all but SDMA */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 273 | } |
| 274 | } |
| 275 | |
| 276 | static void serialio_set_resources(struct device *dev) |
| 277 | { |
| 278 | pci_dev_set_resources(dev); |
| 279 | |
Martin Roth | e6ff159 | 2017-06-24 21:34:29 -0600 | [diff] [blame] | 280 | #if IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 281 | /* Update UART base address if used for debug */ |
| 282 | if (serialio_uart_is_debug(dev)) { |
| 283 | struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 284 | if (res) |
| 285 | uartmem_setbaseaddr(res->base); |
| 286 | } |
| 287 | #endif |
| 288 | } |
| 289 | |
| 290 | static struct device_operations device_ops = { |
| 291 | .read_resources = &pci_dev_read_resources, |
| 292 | .set_resources = &serialio_set_resources, |
| 293 | .enable_resources = &pci_dev_enable_resources, |
| 294 | .init = &serialio_init, |
| 295 | .ops_pci = &broadwell_pci_ops, |
| 296 | }; |
| 297 | |
| 298 | static const unsigned short pci_device_ids[] = { |
| 299 | 0x9c60, 0x9ce0, /* 0:15.0 - SDMA */ |
| 300 | 0x9c61, 0x9ce1, /* 0:15.1 - I2C0 */ |
| 301 | 0x9c62, 0x9ce2, /* 0:15.2 - I2C1 */ |
| 302 | 0x9c65, 0x9ce5, /* 0:15.3 - SPI0 */ |
| 303 | 0x9c66, 0x9ce6, /* 0:15.4 - SPI1 */ |
| 304 | 0x9c63, 0x9ce3, /* 0:15.5 - UART0 */ |
| 305 | 0x9c64, 0x9ce4, /* 0:15.6 - UART1 */ |
| 306 | 0x9c35, 0x9cb5, /* 0:17.0 - SDIO */ |
| 307 | 0 |
| 308 | }; |
| 309 | |
| 310 | static const struct pci_driver pch_pcie __pci_driver = { |
| 311 | .ops = &device_ops, |
| 312 | .vendor = PCI_VENDOR_ID_INTEL, |
| 313 | .devices = pci_device_ids, |
| 314 | }; |