Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2003 Linux Networx |
| 5 | * Copyright (C) 2004 SuSE Linux AG |
| 6 | * Copyright (C) 2004 Tyan Computer |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 7 | * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org> |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; version 2 of |
| 12 | * the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 22 | */ |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 23 | |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 24 | #include <console/console.h> |
| 25 | #include <device/device.h> |
| 26 | #include <device/pci.h> |
| 27 | #include <device/pci_ids.h> |
| 28 | #include <device/pci_ops.h> |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 29 | #include <pc80/mc146818rtc.h> |
Steven J. Magnani | ef79223 | 2005-09-21 13:53:44 +0000 | [diff] [blame] | 30 | #include <pc80/isa-dma.h> |
| 31 | #include <arch/io.h> |
Stefan Reinauer | 138be83 | 2010-02-27 01:50:21 +0000 | [diff] [blame] | 32 | #include "i82801dx.h" |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 33 | |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 34 | #define NMI_OFF 0 |
| 35 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 36 | typedef struct southbridge_intel_i82801dx_config config_t; |
| 37 | |
| 38 | static void i82801dx_enable_ioapic(struct device *dev) |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 39 | { |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 40 | u32 reg32; |
Stefan Reinauer | 5c32d24 | 2010-03-17 03:40:23 +0000 | [diff] [blame] | 41 | volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); |
| 42 | volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 43 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 44 | /* Set ACPI base address (I/O space). */ |
| 45 | pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 46 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 47 | /* Enable ACPI I/O and power management. */ |
| 48 | pci_write_config8(dev, ACPI_CNTL, 0x10); |
| 49 | |
| 50 | reg32 = pci_read_config32(dev, GEN_CNTL); |
| 51 | reg32 |= (3 << 7); /* Enable IOAPIC */ |
| 52 | reg32 |= (1 << 13); /* Coprocessor error enable */ |
| 53 | reg32 |= (1 << 1); /* Delayed transaction enable */ |
| 54 | reg32 |= (1 << 2); /* DMA collection buffer enable */ |
| 55 | pci_write_config32(dev, GEN_CNTL, reg32); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 56 | printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 57 | |
| 58 | *ioapic_index = 0; |
| 59 | *ioapic_data = (1 << 25); |
| 60 | |
| 61 | *ioapic_index = 0; |
| 62 | reg32 = *ioapic_data; |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 63 | printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32); |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 64 | if (reg32 != (1 << 25)) |
| 65 | die("APIC Error\n"); |
| 66 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 67 | *ioapic_index = 3; /* Select Boot Configuration register. */ |
| 68 | *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 69 | } |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 70 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 71 | static void i82801dx_enable_serial_irqs(struct device *dev) |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 72 | { |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 73 | /* Set packet length and toggle silent mode bit. */ |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 74 | pci_write_config8(dev, SERIRQ_CNTL, |
| 75 | (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 76 | pci_write_config8(dev, SERIRQ_CNTL, |
| 77 | (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 78 | } |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 79 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 80 | static void i82801dx_pirq_init(device_t dev) |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 81 | { |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 82 | /* Get the chip configuration */ |
| 83 | config_t *config = dev->chip_info; |
| 84 | |
| 85 | pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); |
| 86 | pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); |
| 87 | pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); |
| 88 | pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); |
| 89 | pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); |
| 90 | pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); |
| 91 | pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); |
| 92 | pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 93 | } |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 94 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 95 | static void i82801dx_power_options(device_t dev) |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 96 | { |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 97 | u8 reg8; |
| 98 | u16 reg16, pmbase; |
| 99 | u32 reg32; |
| 100 | const char *state; |
| 101 | |
| 102 | int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; |
Luc Verhaegen | a9c5ea0 | 2009-06-03 14:19:33 +0000 | [diff] [blame] | 103 | int nmi_option; |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 104 | |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 105 | /* Which state do we want to goto after g3 (power restored)? |
| 106 | * 0 == S0 Full On |
| 107 | * 1 == S5 Soft Off |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 108 | * |
| 109 | * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 110 | */ |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 111 | if (get_option(&pwr_on, "power_on_after_fail") < 0) |
| 112 | pwr_on = MAINBOARD_POWER_ON; |
| 113 | |
| 114 | reg8 = pci_read_config8(dev, GEN_PMCON_3); |
| 115 | reg8 &= 0xfe; |
| 116 | switch (pwr_on) { |
| 117 | case MAINBOARD_POWER_OFF: |
| 118 | reg8 |= 1; |
| 119 | state = "off"; |
| 120 | break; |
| 121 | case MAINBOARD_POWER_ON: |
| 122 | reg8 &= ~1; |
| 123 | state = "on"; |
| 124 | break; |
| 125 | case MAINBOARD_POWER_KEEP: |
| 126 | reg8 &= ~1; |
| 127 | state = "state keep"; |
| 128 | break; |
| 129 | default: |
| 130 | state = "undefined"; |
| 131 | } |
| 132 | |
| 133 | reg8 &= ~(1 << 3); /* minimum asssertion is 1 to 2 RTCCLK */ |
| 134 | |
| 135 | pci_write_config8(dev, GEN_PMCON_3, reg8); |
| 136 | printk_info("Set power %s after power failure.\n", state); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 137 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 138 | /* Set up NMI on errors. */ |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 139 | reg8 = inb(0x61); |
| 140 | reg8 &= 0x0f; /* Higher Nibble must be 0 */ |
| 141 | reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ |
| 142 | // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ |
| 143 | reg8 |= (1 << 2); /* PCI SERR# Disable for now */ |
| 144 | outb(reg8, 0x61); |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 145 | |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 146 | reg8 = inb(0x70); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 147 | nmi_option = NMI_OFF; |
Luc Verhaegen | a9c5ea0 | 2009-06-03 14:19:33 +0000 | [diff] [blame] | 148 | get_option(&nmi_option, "nmi"); |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 149 | if (nmi_option) { |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 150 | printk_info ("NMI sources enabled.\n"); |
| 151 | reg8 &= ~(1 << 7); /* Set NMI. */ |
| 152 | } else { |
| 153 | printk_info ("NMI sources disabled.\n"); |
| 154 | reg8 |= ( 1 << 7); /* Disable NMI. */ |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 155 | } |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 156 | outb(reg8, 0x70); |
| 157 | |
| 158 | /* Set SMI# rate down and enable CPU_SLP# */ |
| 159 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 160 | reg16 &= ~(3 << 0); // SMI# rate 1 minute |
| 161 | reg16 |= (1 << 5); // CPUSLP_EN Desktop only |
| 162 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 163 | |
| 164 | pmbase = pci_read_config16(dev, 0x40) & 0xfffe; |
| 165 | |
| 166 | /* Set up power management block and determine sleep mode */ |
| 167 | reg32 = inl(pmbase + 0x04); // PM1_CNT |
| 168 | |
| 169 | reg32 &= ~(7 << 10); // SLP_TYP |
| 170 | reg32 |= (1 << 0); // SCI_EN |
| 171 | outl(reg32, pmbase + 0x04); |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 172 | } |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 173 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 174 | static void gpio_init(device_t dev) |
| 175 | { |
| 176 | /* This should be done in romstage.c already */ |
| 177 | pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1)); |
| 178 | pci_write_config8(dev, GPIO_CNTL, 0x10); |
| 179 | } |
| 180 | |
| 181 | static void i82801dx_rtc_init(struct device *dev) |
| 182 | { |
| 183 | u8 reg8; |
| 184 | u32 reg32; |
| 185 | int rtc_failed; |
| 186 | |
| 187 | reg8 = pci_read_config8(dev, GEN_PMCON_3); |
| 188 | rtc_failed = reg8 & RTC_BATTERY_DEAD; |
| 189 | if (rtc_failed) { |
| 190 | reg8 &= ~(1 << 1); /* Preserve the power fail state. */ |
| 191 | pci_write_config8(dev, GEN_PMCON_3, reg8); |
| 192 | } |
| 193 | reg32 = pci_read_config32(dev, GEN_STS); |
| 194 | rtc_failed |= reg32 & (1 << 2); |
| 195 | rtc_init(rtc_failed); |
| 196 | |
| 197 | /* Enable access to the upper 128 byte bank of CMOS RAM. */ |
| 198 | pci_write_config8(dev, RTC_CONF, 0x04); |
| 199 | } |
| 200 | |
| 201 | static void i82801dx_lpc_route_dma(struct device *dev, u8 mask) |
| 202 | { |
| 203 | u16 reg16; |
| 204 | int i; |
| 205 | |
| 206 | reg16 = pci_read_config16(dev, PCI_DMA_CFG); |
| 207 | reg16 &= 0x300; |
| 208 | for (i = 0; i < 8; i++) { |
| 209 | if (i == 4) |
| 210 | continue; |
| 211 | reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2); |
| 212 | } |
| 213 | pci_write_config16(dev, PCI_DMA_CFG, reg16); |
| 214 | } |
| 215 | |
| 216 | static void i82801dx_lpc_decode_en(device_t dev) |
| 217 | { |
| 218 | /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. |
| 219 | * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. |
| 220 | * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7. |
| 221 | * We also need to set the value for LPC I/F Enables Register. |
| 222 | */ |
| 223 | pci_write_config8(dev, COM_DEC, 0x10); |
| 224 | pci_write_config16(dev, LPC_EN, 0x300F); |
| 225 | } |
| 226 | |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 227 | /* ICH4 does not mention HPET in the docs, but |
| 228 | * all ICH3 and ICH4 do have HPETs built in. |
| 229 | */ |
| 230 | static void enable_hpet(struct device *dev) |
| 231 | { |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 232 | u32 reg32, hpet, val; |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 233 | |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 234 | /* Set HPET base address and enable it */ |
| 235 | printk_debug("Enabling HPET at 0x%x\n", HPET_ADDR); |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 236 | reg32 = pci_read_config32(dev, GEN_CNTL); |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 237 | /* |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 238 | * Bit 17 is HPET enable bit. |
| 239 | * Bit 16:15 control the HPET base address. |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 240 | */ |
| 241 | reg32 &= ~(3 << 15); /* Clear it */ |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 242 | |
| 243 | hpet = HPET_ADDR >> 12; |
| 244 | hpet &= 0x3; |
| 245 | |
| 246 | reg32 |= (hpet << 15); |
| 247 | reg32 |= (1 << 17); /* Enable HPET. */ |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 248 | pci_write_config32(dev, GEN_CNTL, reg32); |
| 249 | |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 250 | /* Check to see whether it took */ |
| 251 | reg32 = pci_read_config32(dev, GEN_CNTL); |
| 252 | val = reg32 >> 15; |
| 253 | val &= 0x7; |
| 254 | |
| 255 | if ((val & 0x4) && (hpet == (val & 0x3))) { |
| 256 | printk_debug("HPET enabled at 0x%x\n", HPET_ADDR); |
| 257 | } else { |
| 258 | printk_err("HPET was not enabled correctly\n"); |
| 259 | reg32 &= ~(1 << 17); /* Clear Enable */ |
| 260 | pci_write_config32(dev, GEN_CNTL, reg32); |
| 261 | } |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 262 | } |
| 263 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 264 | static void lpc_init(struct device *dev) |
| 265 | { |
| 266 | /* Set the value for PCI command register. */ |
| 267 | pci_write_config16(dev, PCI_COMMAND, 0x000f); |
| 268 | |
| 269 | /* IO APIC initialization. */ |
| 270 | i82801dx_enable_ioapic(dev); |
| 271 | |
| 272 | i82801dx_enable_serial_irqs(dev); |
| 273 | |
| 274 | /* Setup the PIRQ. */ |
| 275 | i82801dx_pirq_init(dev); |
| 276 | |
| 277 | /* Setup power options. */ |
| 278 | i82801dx_power_options(dev); |
| 279 | |
| 280 | /* Set the state of the GPIO lines. */ |
| 281 | gpio_init(dev); |
| 282 | |
| 283 | /* Initialize the real time clock. */ |
Stefan Reinauer | 138be83 | 2010-02-27 01:50:21 +0000 | [diff] [blame] | 284 | i82801dx_rtc_init(dev); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 285 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 286 | /* Route DMA. */ |
Stefan Reinauer | 138be83 | 2010-02-27 01:50:21 +0000 | [diff] [blame] | 287 | i82801dx_lpc_route_dma(dev, 0xff); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 288 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 289 | /* Initialize ISA DMA. */ |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 290 | isa_dma_init(); |
| 291 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 292 | /* Setup decode ports and LPC I/F enables. */ |
| 293 | i82801dx_lpc_decode_en(dev); |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 294 | |
| 295 | /* Initialize the High Precision Event Timers */ |
| 296 | enable_hpet(dev); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 297 | } |
| 298 | |
Stefan Reinauer | 138be83 | 2010-02-27 01:50:21 +0000 | [diff] [blame] | 299 | static void i82801dx_lpc_read_resources(device_t dev) |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 300 | { |
Eric Biederman | 4f9265f | 2004-10-22 02:33:51 +0000 | [diff] [blame] | 301 | struct resource *res; |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 302 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 303 | /* Get the normal PCI resources of this device. */ |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 304 | pci_dev_read_resources(dev); |
| 305 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 306 | /* Add an extra subtractive resource for both memory and I/O. */ |
Eric Biederman | 4f9265f | 2004-10-22 02:33:51 +0000 | [diff] [blame] | 307 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 308 | res->base = 0; |
| 309 | res->size = 0x1000; |
| 310 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 311 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
Eric Biederman | 4f9265f | 2004-10-22 02:33:51 +0000 | [diff] [blame] | 312 | |
| 313 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 314 | res->base = 0xff800000; |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 315 | res->size = 0x00800000; /* 8 MB for flash */ |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 316 | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 317 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 318 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 319 | res = new_resource(dev, 3); /* IOAPIC */ |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 320 | res->base = 0xfec00000; |
| 321 | res->size = 0x00001000; |
| 322 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
Eric Biederman | 4f9265f | 2004-10-22 02:33:51 +0000 | [diff] [blame] | 323 | } |
| 324 | |
Stefan Reinauer | 138be83 | 2010-02-27 01:50:21 +0000 | [diff] [blame] | 325 | static void i82801dx_lpc_enable_resources(device_t dev) |
Eric Biederman | 4f9265f | 2004-10-22 02:33:51 +0000 | [diff] [blame] | 326 | { |
| 327 | pci_dev_enable_resources(dev); |
| 328 | enable_childrens_resources(dev); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 329 | } |
| 330 | |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 331 | static struct device_operations lpc_ops = { |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 332 | .read_resources = i82801dx_lpc_read_resources, |
| 333 | .set_resources = pci_dev_set_resources, |
| 334 | .enable_resources = i82801dx_lpc_enable_resources, |
| 335 | .init = lpc_init, |
| 336 | .scan_bus = scan_static_bus, |
| 337 | .enable = i82801dx_enable, |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 338 | }; |
| 339 | |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 340 | /* 82801DB/DBL */ |
| 341 | static const struct pci_driver lpc_driver_db __pci_driver = { |
| 342 | .ops = &lpc_ops, |
| 343 | .vendor = PCI_VENDOR_ID_INTEL, |
| 344 | .device = PCI_DEVICE_ID_INTEL_82801DB_LPC, |
| 345 | }; |
| 346 | |
| 347 | /* 82801DBM */ |
| 348 | static const struct pci_driver lpc_driver_dbm __pci_driver = { |
| 349 | .ops = &lpc_ops, |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 350 | .vendor = PCI_VENDOR_ID_INTEL, |
Uwe Hermann | a29ec06 | 2007-11-04 03:21:37 +0000 | [diff] [blame] | 351 | .device = PCI_DEVICE_ID_INTEL_82801DBM_LPC, |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 352 | }; |