Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Patrick Georgi | 5b2a2d0 | 2018-09-26 20:46:04 +0200 | [diff] [blame] | 4 | * Copyright (C) 2012 Google LLC |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 5 | * Copyright (C) 2013 Vladimir Serbinenko. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #define __SIMPLE_DEVICE__ |
| 18 | |
Kyösti Mälkki | 2c3fd49 | 2016-07-22 22:52:14 +0300 | [diff] [blame] | 19 | #include <arch/cpu.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 20 | #include <device/pci_ops.h> |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 21 | #include <cbmem.h> |
Kyösti Mälkki | 2c3fd49 | 2016-07-22 22:52:14 +0300 | [diff] [blame] | 22 | #include <console/console.h> |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 23 | #include <cpu/intel/romstage.h> |
Kyösti Mälkki | 2c3fd49 | 2016-07-22 22:52:14 +0300 | [diff] [blame] | 24 | #include <cpu/x86/mtrr.h> |
| 25 | #include <program_loading.h> |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 26 | #include <stage_cache.h> |
Arthur Heymans | 97c7c6b | 2018-05-15 16:45:21 +0200 | [diff] [blame] | 27 | #include <cpu/intel/smm/gen1/smi.h> |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 28 | #include "nehalem.h" |
| 29 | |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 30 | static uintptr_t smm_region_start(void) |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 31 | { |
| 32 | /* Base of TSEG is top of usable DRAM */ |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 33 | uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); |
| 34 | return tom; |
| 35 | } |
| 36 | |
Arthur Heymans | 97c7c6b | 2018-05-15 16:45:21 +0200 | [diff] [blame] | 37 | u32 northbridge_get_tseg_base(void) |
| 38 | { |
Arthur Heymans | 23fbd05 | 2019-05-28 17:38:17 +0200 | [diff] [blame] | 39 | return (u32)smm_region_start(); |
Arthur Heymans | 97c7c6b | 2018-05-15 16:45:21 +0200 | [diff] [blame] | 40 | } |
| 41 | |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 42 | u32 northbridge_get_tseg_size(void) |
| 43 | { |
| 44 | return CONFIG_SMM_TSEG_SIZE; |
| 45 | } |
| 46 | |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 47 | void *cbmem_top(void) |
| 48 | { |
| 49 | return (void *) smm_region_start(); |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 50 | } |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 51 | |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 52 | void stage_cache_external_region(void **base, size_t *size) |
| 53 | { |
| 54 | /* The stage cache lives at the end of TSEG region. |
| 55 | * The top of RAM is defined to be the TSEG base address. */ |
| 56 | *size = CONFIG_SMM_RESERVED_SIZE; |
| 57 | *base = (void *)((uintptr_t)northbridge_get_tseg_base() + |
| 58 | northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); |
| 59 | } |
| 60 | |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 61 | void fill_postcar_frame(struct postcar_frame *pcf) |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 62 | { |
Kyösti Mälkki | 2c3fd49 | 2016-07-22 22:52:14 +0300 | [diff] [blame] | 63 | uintptr_t top_of_ram; |
| 64 | |
Kyösti Mälkki | 2c3fd49 | 2016-07-22 22:52:14 +0300 | [diff] [blame] | 65 | /* Cache at least 8 MiB below the top of ram, and at most 8 MiB |
| 66 | * above top of the ram. This satisfies MTRR alignment requirement |
| 67 | * with different TSEG size configurations. |
| 68 | */ |
| 69 | top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 70 | postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); |
| 71 | postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 72 | } |