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Patrick Georgi0588d192009-08-12 15:00:51 +00001##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00002## This file is part of the coreboot project.
Patrick Georgi0588d192009-08-12 15:00:51 +00003##
Alexandru Gagniuc70c660f2012-08-23 02:32:58 -05004## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
Stefan Reinauer16f515a2010-01-20 18:44:30 +00005## Copyright (C) 2009-2010 coresystems GmbH
Patrick Georgi0588d192009-08-12 15:00:51 +00006##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00007## This program is free software; you can redistribute it and/or modify
8## it under the terms of the GNU General Public License as published by
9## the Free Software Foundation; version 2 of the License.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
Patrick Georgi0588d192009-08-12 15:00:51 +000016
Uwe Hermannad8c95f2012-04-12 22:00:03 +020017mainmenu "coreboot configuration"
Patrick Georgi0588d192009-08-12 15:00:51 +000018
Uwe Hermannc04be932009-10-05 13:55:28 +000019menu "General setup"
20
21config LOCALVERSION
Uwe Hermann168b11b2009-10-07 16:15:40 +000022 string "Local version string"
Uwe Hermannc04be932009-10-05 13:55:28 +000023 help
24 Append an extra string to the end of the coreboot version.
25
Uwe Hermann168b11b2009-10-07 16:15:40 +000026 This can be useful if, for instance, you want to append the
27 respective board's hostname or some other identifying string to
28 the coreboot version number, so that you can easily distinguish
29 boot logs of different boards from each other.
30
Patrick Georgi4b8a2412010-02-09 19:35:16 +000031config CBFS_PREFIX
32 string "CBFS prefix to use"
33 default "fallback"
34 help
35 Select the prefix to all files put into the image. It's "fallback"
36 by default, "normal" is a common alternative.
37
Vadim Bendeburyadcb0952014-05-01 12:23:09 -070038config COMMON_CBFS_SPI_WRAPPER
39 bool
40 default n
41 depends on SPI_FLASH
42 depends on !ARCH_X86
43 help
44 Use common wrapper to interface CBFS to SPI bootrom.
45
Vadim Bendebury6bfabce2014-12-25 15:07:22 -080046config MULTIPLE_CBFS_INSTANCES
Martin Roth595e7772015-04-26 18:53:26 -060047 bool "Multiple CBFS instances in the bootrom"
48 default n
Martin Roth595e7772015-04-26 18:53:26 -060049 help
50 Account for the firmware image containing more than one CBFS
51 instance. Locations of instances are known at build time and are
52 communicated between coreboot stages to make sure the next stage is
53 loaded from the appropriate instance.
Vadim Bendebury6bfabce2014-12-25 15:07:22 -080054
Patrick Georgi23d89cc2010-03-16 01:17:19 +000055choice
Uwe Hermannad8c95f2012-04-12 22:00:03 +020056 prompt "Compiler to use"
Patrick Georgi23d89cc2010-03-16 01:17:19 +000057 default COMPILER_GCC
58 help
59 This option allows you to select the compiler used for building
60 coreboot.
Martin Rotha5a628e82016-01-19 12:01:09 -070061 You must build the coreboot crosscompiler for the board that you
62 have selected.
63
64 To build all the GCC crosscompilers (takes a LONG time), run:
65 make crossgcc
66
67 For help on individual architectures, run the command:
68 make help_toolchain
Patrick Georgi23d89cc2010-03-16 01:17:19 +000069
70config COMPILER_GCC
71 bool "GCC"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020072 help
73 Use the GNU Compiler Collection (GCC) to build coreboot.
74
75 For details see http://gcc.gnu.org.
76
Patrick Georgi23d89cc2010-03-16 01:17:19 +000077config COMPILER_LLVM_CLANG
Martin Rotha5a628e82016-01-19 12:01:09 -070078 bool "LLVM/clang (TESTING ONLY - Not currently working)"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020079 help
Martin Rotha5a628e82016-01-19 12:01:09 -070080 Use LLVM/clang to build coreboot. To use this, you must build the
81 coreboot version of the clang compiler. Run the command
82 make clang
83 Note that this option is not currently working correctly and should
84 really only be selected if you're trying to work on getting clang
85 operational.
Uwe Hermannad8c95f2012-04-12 22:00:03 +020086
87 For details see http://clang.llvm.org.
88
Patrick Georgi23d89cc2010-03-16 01:17:19 +000089endchoice
90
Patrick Georgi9b0de712013-12-29 18:45:23 +010091config ANY_TOOLCHAIN
92 bool "Allow building with any toolchain"
93 default n
94 depends on COMPILER_GCC
95 help
96 Many toolchains break when building coreboot since it uses quite
97 unusual linker features. Unless developers explicitely request it,
98 we'll have to assume that they use their distro compiler by mistake.
99 Make sure that using patched compilers is a conscious decision.
100
Patrick Georgi516a2a72010-03-25 21:45:25 +0000101config CCACHE
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200102 bool "Use ccache to speed up (re)compilation"
Patrick Georgi516a2a72010-03-25 21:45:25 +0000103 default n
104 help
105 Enables the use of ccache for faster builds.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200106
107 Requires the ccache utility in your system $PATH.
108
109 For details see https://ccache.samba.org.
Patrick Georgi516a2a72010-03-25 21:45:25 +0000110
Sol Boucher69b88bf2015-02-26 11:47:19 -0800111config FMD_GENPARSER
112 bool "Generate flashmap descriptor parser using flex and bison"
113 default n
Sol Boucher69b88bf2015-02-26 11:47:19 -0800114 help
115 Enable this option if you are working on the flashmap descriptor
116 parser and made changes to fmd_scanner.l or fmd_parser.y.
117
118 Otherwise, say N to use the provided pregenerated scanner/parser.
119
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000120config SCONFIG_GENPARSER
121 bool "Generate SCONFIG parser using flex and bison"
122 default n
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000123 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200124 Enable this option if you are working on the sconfig device tree
Sol Boucher69b88bf2015-02-26 11:47:19 -0800125 parser and made changes to sconfig.l or sconfig.y.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200126
Sol Boucher69b88bf2015-02-26 11:47:19 -0800127 Otherwise, say N to use the provided pregenerated scanner/parser.
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000128
Joe Korty6d772522010-05-19 18:41:15 +0000129config USE_OPTION_TABLE
130 bool "Use CMOS for configuration values"
131 default n
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000132 depends on HAVE_OPTION_TABLE
Joe Korty6d772522010-05-19 18:41:15 +0000133 help
134 Enable this option if coreboot shall read options from the "CMOS"
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200135 NVRAM instead of using hard-coded values.
Joe Korty6d772522010-05-19 18:41:15 +0000136
Timothy Pearsonf20c6e82015-02-14 16:15:31 -0600137config STATIC_OPTION_TABLE
138 bool "Load default configuration values into CMOS on each boot"
139 default n
140 depends on USE_OPTION_TABLE
141 help
142 Enable this option to reset "CMOS" NVRAM values to default on
143 every boot. Use this if you want the NVRAM configuration to
144 never be modified from its default values.
145
Julius Wernercdf92ea2014-12-09 12:18:00 -0800146config UNCOMPRESSED_RAMSTAGE
147 bool
148 default n
149
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000150config COMPRESS_RAMSTAGE
151 bool "Compress ramstage with LZMA"
Julius Wernercdf92ea2014-12-09 12:18:00 -0800152 default y if !UNCOMPRESSED_RAMSTAGE
153 default n
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000154 help
155 Compress ramstage to save memory in the flash image. Note
156 that decompression might slow down booting if the boot flash
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200157 is connected through a slow link (i.e. SPI).
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000158
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200159config INCLUDE_CONFIG_FILE
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200160 bool "Include the coreboot .config file into the ROM image"
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200161 default y
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200162 help
163 Include the .config file that was used to compile coreboot
164 in the (CBFS) ROM image. This is useful if you want to know which
165 options were used to build a specific coreboot.rom image.
166
Daniele Forsi53847a22014-07-22 18:00:56 +0200167 Saying Y here will increase the image size by 2-3KB.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200168
169 You can use the following command to easily list the options:
170
171 grep -a CONFIG_ coreboot.rom
172
173 Alternatively, you can also use cbfstool to print the image
174 contents (including the raw 'config' item we're looking for).
175
176 Example:
177
178 $ cbfstool coreboot.rom print
179 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
180 offset 0x0
181 Alignment: 64 bytes
Steve Goodrichf0269122012-05-18 11:18:47 -0600182
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200183 Name Offset Type Size
184 cmos_layout.bin 0x0 cmos layout 1159
185 fallback/romstage 0x4c0 stage 339756
Daniele Forsi53847a22014-07-22 18:00:56 +0200186 fallback/ramstage 0x53440 stage 186664
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200187 fallback/payload 0x80dc0 payload 51526
188 config 0x8d740 raw 3324
189 (empty) 0x8e480 null 3610440
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200190
Kyösti Mälkkif8bf5a12013-10-11 22:08:02 +0300191config EARLY_CBMEM_INIT
Kyösti Mälkki3bf38542014-12-18 22:22:04 +0200192 def_bool !LATE_CBMEM_INIT
193
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700194config COLLECT_TIMESTAMPS
195 bool "Create a table of timestamps collected during boot"
Kyösti Mälkki26447932013-10-11 21:14:59 +0300196 default n
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700197 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200198 Make coreboot create a table of timer-ID/timer-value pairs to
199 allow measuring time spent at different phases of the boot process.
200
Aaron Durbin1936f6c2015-07-03 17:04:21 -0500201config HAS_PRECBMEM_TIMESTAMP_REGION
202 bool "Timestamp region exists for pre-cbmem timestamps"
203 default y if ARCH_ROMSTAGE_X86_32 && CACHE_AS_RAM
Aaron Durbin1936f6c2015-07-03 17:04:21 -0500204 help
205 A separate region is maintained to allow storing of timestamps before
206 cbmem comes up. This is useful for storing timestamps across different
207 stage boundaries.
208
Patrick Georgi7e9b9d82012-04-30 21:06:10 +0200209config USE_BLOBS
210 bool "Allow use of binary-only repository"
211 default n
212 help
213 This draws in the blobs repository, which contains binary files that
214 might be required for some chipsets or boards.
215 This flag ensures that a "Free" option remains available for users.
216
Stefan Reinauerd37ab452012-12-18 16:23:28 -0800217config COVERAGE
218 bool "Code coverage support"
219 depends on COMPILER_GCC
220 default n
221 help
222 Add code coverage support for coreboot. This will store code
223 coverage information in CBMEM for extraction from user space.
224 If unsure, say N.
225
Stefan Reinauer58470e32014-10-17 13:08:36 +0200226config RELOCATABLE_MODULES
Vladimir Serbinenko633352c2015-05-30 22:21:37 +0200227 bool
Stefan Reinauer58470e32014-10-17 13:08:36 +0200228 default n
229 help
230 If RELOCATABLE_MODULES is selected then support is enabled for
231 building relocatable modules in the RAM stage. Those modules can be
232 loaded anywhere and all the relocations are handled automatically.
233
234config RELOCATABLE_RAMSTAGE
Vladimir Serbinenko633352c2015-05-30 22:21:37 +0200235 depends on EARLY_CBMEM_INIT
Stefan Reinauer58470e32014-10-17 13:08:36 +0200236 bool "Build the ramstage to be relocatable in 32-bit address space."
237 default n
Vladimir Serbinenko633352c2015-05-30 22:21:37 +0200238 select RELOCATABLE_MODULES
Stefan Reinauer58470e32014-10-17 13:08:36 +0200239 help
240 The reloctable ramstage support allows for the ramstage to be built
241 as a relocatable module. The stage loader can identify a place
242 out of the OS way so that copying memory is unnecessary during an S3
243 wake. When selecting this option the romstage is responsible for
244 determing a stack location to use for loading the ramstage.
245
246config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
247 depends on RELOCATABLE_RAMSTAGE
248 bool "Cache the relocated ramstage outside of cbmem."
249 default n
250 help
251 The relocated ramstage is saved in an area specified by the
252 by the board and/or chipset.
253
Aaron Durbin0424c952015-03-28 23:56:22 -0500254config FLASHMAP_OFFSET
255 hex "Flash Map Offset"
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -0700256 default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC
257 default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
Aaron Durbin0424c952015-03-28 23:56:22 -0500258 default CBFS_SIZE if !ARCH_X86
259 default 0
260 help
261 Offset of flash map in firmware image
262
Julius Werner86fc11d2015-10-09 13:37:58 -0700263# TODO: This doesn't belong here, move to src/arch/x86/Kconfig
Stefan Reinauer58470e32014-10-17 13:08:36 +0200264choice
265 prompt "Bootblock behaviour"
266 default BOOTBLOCK_SIMPLE
267
268config BOOTBLOCK_SIMPLE
269 bool "Always load fallback"
270
271config BOOTBLOCK_NORMAL
272 bool "Switch to normal if CMOS says so"
273
274endchoice
275
Julius Werner86fc11d2015-10-09 13:37:58 -0700276# To be selected by arch, SoC or mainboard if it does not want use the normal
277# src/lib/bootblock.c#main() C entry point.
278config BOOTBLOCK_CUSTOM
279 bool
280 default n
281
Stefan Reinauer58470e32014-10-17 13:08:36 +0200282config BOOTBLOCK_SOURCE
283 string
284 default "bootblock_simple.c" if BOOTBLOCK_SIMPLE
285 default "bootblock_normal.c" if BOOTBLOCK_NORMAL
286
Alexandru Gagniucee464b12015-10-02 18:01:18 -0700287# To be selected by arch or platform if a C environment is available during the
288# bootblock. Normally this signifies availability of RW memory (e.g. SRAM).
289config C_ENVIRONMENT_BOOTBLOCK
Martin Roth95f33f4e2016-01-21 12:30:52 -0700290 bool
291 default n
Alexandru Gagniucee464b12015-10-02 18:01:18 -0700292
Timothy Pearson44724082015-03-16 11:47:45 -0500293config SKIP_MAX_REBOOT_CNT_CLEAR
294 bool "Do not clear reboot count after successful boot"
295 default n
Timothy Pearson3bfd7cc2015-11-01 02:13:17 -0600296 depends on BOOTBLOCK_NORMAL
Timothy Pearson44724082015-03-16 11:47:45 -0500297 help
298 Do not clear the reboot count immediately after successful boot.
299 Set to allow the payload to control normal/fallback image recovery.
Timothy Pearson3bfd7cc2015-11-01 02:13:17 -0600300 Note that it is the responsibility of the payload to reset the
301 normal boot bit to 1 after each successsful boot.
Timothy Pearson44724082015-03-16 11:47:45 -0500302
Stefan Reinauer58470e32014-10-17 13:08:36 +0200303config UPDATE_IMAGE
304 bool "Update existing coreboot.rom image"
305 default n
306 help
307 If this option is enabled, no new coreboot.rom file
308 is created. Instead it is expected that there already
309 is a suitable file for further processing.
310 The bootblock will not be modified.
311
Martin Roth5942e062016-01-20 14:59:21 -0700312 If unsure, select 'N'
313
Stefan Reinauerd06258c2015-03-26 16:29:00 -0700314config GENERIC_GPIO_LIB
315 bool
316 default n
317 help
318 If enabled, compile the generic GPIO library. A "generic" GPIO
319 implies configurability usually found on SoCs, particularly the
320 ability to control internal pull resistors.
321
322config BOARD_ID_AUTO
323 bool
324 default n
325 help
326 Mainboards that can read a board ID from the hardware straps
327 (ie. GPIO) select this configuration option.
328
329config BOARD_ID_MANUAL
Vladimir Serbinenko1e161422015-05-30 22:47:22 +0200330 bool
Stefan Reinauerd06258c2015-03-26 16:29:00 -0700331 default n
332 depends on !BOARD_ID_AUTO
333 help
334 If you want to maintain a board ID, but the hardware does not
335 have straps to automatically determine the ID, you can say Y
336 here and add a file named 'board_id' to CBFS. If you don't know
337 what this is about, say N.
338
339config BOARD_ID_STRING
340 string "Board ID"
341 default "(none)"
342 depends on BOARD_ID_MANUAL
343 help
344 This string is placed in the 'board_id' CBFS file for indicating
345 board type.
346
David Hendricks627b3bd2014-11-03 17:42:09 -0800347config RAM_CODE_SUPPORT
Vladimir Serbinenko8ef9c562015-05-30 22:55:44 +0200348 bool
David Hendricks627b3bd2014-11-03 17:42:09 -0800349 default n
350 help
351 If enabled, coreboot discovers RAM configuration (value obtained by
352 reading board straps) and stores it in coreboot table.
353
Konstantin Aladyshev6544cb32015-01-24 18:52:10 +0400354config BOOTSPLASH_IMAGE
355 bool "Add a bootsplash image"
356 help
357 Select this option if you have a bootsplash image that you would
358 like to add to your ROM.
359
360 This will only add the image to the ROM. To actually run it check
361 options under 'Display' section.
362
363config BOOTSPLASH_FILE
364 string "Bootsplash path and filename"
365 depends on BOOTSPLASH_IMAGE
366 default "bootsplash.jpg"
367 help
368 The path and filename of the file to use as graphical bootsplash
369 screen. The file format has to be jpg.
370
Uwe Hermannc04be932009-10-05 13:55:28 +0000371endmenu
372
Alexander Couzens77103792015-04-16 02:03:26 +0200373source "src/acpi/Kconfig"
374
Martin Roth026e4dc2015-06-19 23:17:15 -0600375menu "Mainboard"
376
Stefan Reinauera48ca842015-04-04 01:58:28 +0200377source "src/mainboard/Kconfig"
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000378
Martin Roth59ff3402016-02-09 09:06:46 -0700379# defaults for CBFS_SIZE are set at the end of the file.
Martin Roth026e4dc2015-06-19 23:17:15 -0600380config CBFS_SIZE
381 hex "Size of CBFS filesystem in ROM"
Martin Roth026e4dc2015-06-19 23:17:15 -0600382 help
383 This is the part of the ROM actually managed by CBFS, located at the
384 end of the ROM (passed through cbfstool -o) on x86 and at at the start
385 of the ROM (passed through cbfstool -s) everywhere else. It defaults
386 to span the whole ROM on all but Intel systems that use an Intel Firmware
387 Descriptor. It can be overridden to make coreboot live alongside other
388 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
389 binaries.
390
Patrick Georgi8a3592e2015-09-16 18:10:52 +0200391config FMDFILE
392 string "fmap description file in fmd format"
Patrick Georgi5d7ab392015-12-12 00:23:15 +0100393 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
Patrick Georgi8a3592e2015-09-16 18:10:52 +0200394 default ""
395 help
396 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
397 but in some cases more complex setups are required.
398 When an fmd is specified, it overrides the default format.
399
Martin Rothda1ca202015-12-26 16:51:16 -0700400endmenu
401
Martin Rothb09a5692016-01-24 19:38:33 -0700402# load site-local kconfig to allow user specific defaults and overrides
403source "site-local/Kconfig"
404
Vladimir Serbinenkoa9db82f2014-10-16 13:21:47 +0200405config SYSTEM_TYPE_LAPTOP
Martin Roth595e7772015-04-26 18:53:26 -0600406 default n
407 bool
Vladimir Serbinenkoa9db82f2014-10-16 13:21:47 +0200408
Werner Zehc0fb3612016-01-14 15:08:36 +0100409config CBFS_AUTOGEN_ATTRIBUTES
410 default n
411 bool
412 help
413 If this option is selected, every file in cbfs which has a constraint
414 regarding position or alignment will get an additional file attribute
415 which describes this constraint.
416
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000417menu "Chipset"
418
Duncan Lauried2119762015-06-08 18:11:56 -0700419comment "SoC"
420source "src/soc/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000421comment "CPU"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200422source "src/cpu/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000423comment "Northbridge"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200424source "src/northbridge/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000425comment "Southbridge"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200426source "src/southbridge/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000427comment "Super I/O"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200428source "src/superio/*/Kconfig"
Sven Schnelle7592e8b2011-01-27 11:43:03 +0000429comment "Embedded Controllers"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200430source "src/ec/acpi/Kconfig"
431source "src/ec/*/*/Kconfig"
Marc Jones78687972015-04-22 23:16:31 -0600432source "src/drivers/intel/fsp1_0/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000433
Martin Roth59aa2b12015-06-20 16:17:12 -0600434source "src/southbridge/intel/common/firmware/Kconfig"
Martin Rothe1523ec2015-06-19 22:30:43 -0600435source "src/vendorcode/*/Kconfig"
Martin Roth59aa2b12015-06-20 16:17:12 -0600436
Martin Rothe1523ec2015-06-19 22:30:43 -0600437source "src/arch/*/Kconfig"
438
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000439endmenu
Patrick Georgi0588d192009-08-12 15:00:51 +0000440
Stefan Reinauera48ca842015-04-04 01:58:28 +0200441source "src/device/Kconfig"
Stefan Reinauer95a63962012-11-13 17:00:01 -0800442
Rudolf Marekd9c25492010-05-16 15:31:53 +0000443menu "Generic Drivers"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200444source "src/drivers/*/Kconfig"
Rudolf Marekd9c25492010-05-16 15:31:53 +0000445endmenu
446
Patrick Georgi0770f252015-04-22 13:28:21 +0200447config RTC
448 bool
449 default n
450
Stefan Reinauer7cb01e02013-08-29 16:05:02 -0700451config TPM
452 bool
453 default n
454 select LPC_TPM if ARCH_X86
Gabe Black51edd542013-09-30 23:00:33 -0700455 select I2C_TPM if ARCH_ARM
Furquan Shaikh2af76f42014-04-28 16:39:40 -0700456 select I2C_TPM if ARCH_ARM64
Stefan Reinauer7cb01e02013-08-29 16:05:02 -0700457 help
458 Enable this option to enable TPM support in coreboot.
459
460 If unsure, say N.
461
Kyösti Mälkkieaee6e22014-04-30 01:35:29 +0300462config RAMTOP
463 hex
464 default 0x200000
465 depends on ARCH_X86
466
Patrick Georgi0588d192009-08-12 15:00:51 +0000467config HEAP_SIZE
468 hex
Myles Watson04000f42009-10-16 19:12:49 +0000469 default 0x4000
Patrick Georgi0588d192009-08-12 15:00:51 +0000470
Julius Wernerc3e7c4e2014-09-19 13:18:16 -0700471config STACK_SIZE
472 hex
Julius Werner66a476a2015-10-12 16:45:21 -0700473 default 0x1000 if ARCH_X86
474 default 0x0
Julius Wernerc3e7c4e2014-09-19 13:18:16 -0700475
Patrick Georgi0588d192009-08-12 15:00:51 +0000476config MAX_CPUS
477 int
478 default 1
479
480config MMCONF_SUPPORT_DEFAULT
481 bool
482 default n
483
484config MMCONF_SUPPORT
485 bool
486 default n
487
Kyösti Mälkki5687fc92013-11-28 18:11:49 +0200488config BOOTMODE_STRAPS
489 bool
490 default n
491
Stefan Reinauera48ca842015-04-04 01:58:28 +0200492source "src/console/Kconfig"
Patrick Georgi0588d192009-08-12 15:00:51 +0000493
494config HAVE_ACPI_RESUME
495 bool
496 default n
497
Aaron Durbin87c9fae2016-01-22 15:26:04 -0600498config RESUME_PATH_SAME_AS_BOOT
499 bool
500 default y if ARCH_X86
501 depends on HAVE_ACPI_RESUME
502 help
503 This option indicates that when a system resumes it takes the
504 same path as a regular boot. e.g. an x86 system runs from the
505 reset vector at 0xfffffff0 on both resume and warm/cold boot.
506
Patrick Georgi0588d192009-08-12 15:00:51 +0000507config HAVE_HARD_RESET
508 bool
Uwe Hermann748475b2009-10-09 11:47:21 +0000509 default n
Patrick Georgi37bdb872010-02-27 08:39:04 +0000510 help
511 This variable specifies whether a given board has a hard_reset
512 function, no matter if it's provided by board code or chipset code.
513
Timothy Pearson44d53422015-05-18 16:04:10 -0500514config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
515 bool
516 default n
517
Timothy Pearson7b22d842015-08-28 19:52:05 -0500518config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
519 bool
520 default n
521 help
522 This should be enabled on certain plaforms, such as the AMD
523 SR565x, that cannot handle concurrent CBFS accesses from
524 multiple APs during early startup.
525
Timothy Pearsonc764c742015-08-28 20:48:17 -0500526config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
527 bool
528 default n
529
Aaron Durbina4217912013-04-29 22:31:51 -0500530config HAVE_MONOTONIC_TIMER
531 def_bool n
532 help
533 The board/chipset provides a monotonic timer.
534
Aaron Durbine5e36302014-09-25 10:05:15 -0500535config GENERIC_UDELAY
536 def_bool n
537 depends on HAVE_MONOTONIC_TIMER
538 help
539 The board/chipset uses a generic udelay function utilizing the
540 monotonic timer.
541
Aaron Durbin340ca912013-04-30 09:58:12 -0500542config TIMER_QUEUE
543 def_bool n
544 depends on HAVE_MONOTONIC_TIMER
545 help
Kyösti Mälkkiecd84242013-09-13 07:57:49 +0300546 Provide a timer queue for performing time-based callbacks.
Aaron Durbin340ca912013-04-30 09:58:12 -0500547
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500548config COOP_MULTITASKING
549 def_bool n
Aaron Durbin38c326d2013-05-06 12:22:23 -0500550 depends on TIMER_QUEUE && ARCH_X86
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500551 help
552 Cooperative multitasking allows callbacks to be multiplexed on the
553 main thread of ramstage. With this enabled it allows for multiple
554 execution paths to take place when they have udelay() calls within
555 their code.
556
557config NUM_THREADS
558 int
559 default 4
560 depends on COOP_MULTITASKING
561 help
562 How many execution threads to cooperatively multitask with.
563
Patrick Georgi0588d192009-08-12 15:00:51 +0000564config HAVE_OPTION_TABLE
565 bool
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000566 default n
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000567 help
568 This variable specifies whether a given board has a cmos.layout
569 file containing NVRAM/CMOS bit definitions.
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000570 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
Patrick Georgi0588d192009-08-12 15:00:51 +0000571
Patrick Georgi0588d192009-08-12 15:00:51 +0000572config PIRQ_ROUTE
573 bool
574 default n
575
576config HAVE_SMI_HANDLER
577 bool
578 default n
579
580config PCI_IO_CFG_EXT
581 bool
582 default n
583
584config IOAPIC
585 bool
586 default n
587
Kyösti Mälkki107f72e2014-01-06 11:06:26 +0200588config CACHE_ROM_SIZE_OVERRIDE
Stefan Reinauer5b635792012-08-16 14:05:42 -0700589 hex
Kyösti Mälkki107f72e2014-01-06 11:06:26 +0200590 default 0
Stefan Reinauer5b635792012-08-16 14:05:42 -0700591
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000592# TODO: Can probably be removed once all chipsets have kconfig options for it.
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000593config VIDEO_MB
594 int
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000595 default 0
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000596
Myles Watson45bb25f2009-09-22 18:49:08 +0000597config USE_WATCHDOG_ON_BOOT
598 bool
599 default n
600
601config VGA
602 bool
603 default n
604 help
605 Build board-specific VGA code.
606
607config GFXUMA
608 bool
Myles Watsond73c1b52009-10-26 15:14:07 +0000609 default n
Myles Watson45bb25f2009-09-22 18:49:08 +0000610 help
611 Enable Unified Memory Architecture for graphics.
612
Myles Watsonb8e20272009-10-15 13:35:47 +0000613config HAVE_ACPI_TABLES
614 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000615 help
616 This variable specifies whether a given board has ACPI table support.
617 It is usually set in mainboard/*/Kconfig.
Myles Watsonb8e20272009-10-15 13:35:47 +0000618
619config HAVE_MP_TABLE
620 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000621 help
622 This variable specifies whether a given board has MP table support.
623 It is usually set in mainboard/*/Kconfig.
624 Whether or not the MP table is actually generated by coreboot
625 is configurable by the user via GENERATE_MP_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000626
627config HAVE_PIRQ_TABLE
628 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000629 help
630 This variable specifies whether a given board has PIRQ table support.
631 It is usually set in mainboard/*/Kconfig.
632 Whether or not the PIRQ table is actually generated by coreboot
633 is configurable by the user via GENERATE_PIRQ_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000634
Alexandru Gagniuc70c660f2012-08-23 02:32:58 -0500635config MAX_PIRQ_LINKS
636 int
637 default 4
638 help
639 This variable specifies the number of PIRQ interrupt links which are
640 routable. On most chipsets, this is 4, INTA through INTD. Some
641 chipsets offer more than four links, commonly up to INTH. They may
642 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
643 table specifies links greater than 4, pirq_route_irqs will not
644 function properly, unless this variable is correctly set.
645
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200646config COMMON_FADT
647 bool
648 default n
649
Aaron Durbin9420a522015-11-17 16:31:00 -0600650config ACPI_NHLT
651 bool
652 default n
653 help
654 Build support for NHLT (non HD Audio) ACPI table generation.
655
Myles Watsond73c1b52009-10-26 15:14:07 +0000656#These Options are here to avoid "undefined" warnings.
657#The actual selection and help texts are in the following menu.
658
Uwe Hermann168b11b2009-10-07 16:15:40 +0000659menu "System tables"
Myles Watson45bb25f2009-09-22 18:49:08 +0000660
Myles Watsonb8e20272009-10-15 13:35:47 +0000661config GENERATE_MP_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800662 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
663 bool
664 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000665 help
666 Generate an MP table (conforming to the Intel MultiProcessor
667 specification 1.4) for this board.
668
669 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000670
Myles Watsonb8e20272009-10-15 13:35:47 +0000671config GENERATE_PIRQ_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800672 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
673 bool
674 default HAVE_PIRQ_TABLE
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000675 help
676 Generate a PIRQ table for this board.
677
678 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000679
Sven Schnelle164bcfd2011-08-14 20:56:34 +0200680config GENERATE_SMBIOS_TABLES
681 depends on ARCH_X86
682 bool "Generate SMBIOS tables"
683 default y
684 help
685 Generate SMBIOS tables for this board.
686
687 If unsure, say Y.
688
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200689config SMBIOS_PROVIDED_BY_MOBO
690 bool
691 default n
692
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200693config MAINBOARD_SERIAL_NUMBER
694 string "SMBIOS Serial Number"
695 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200696 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200697 default "123456789"
Martin Roth595e7772015-04-26 18:53:26 -0600698 help
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200699 The Serial Number to store in SMBIOS structures.
700
701config MAINBOARD_VERSION
702 string "SMBIOS Version Number"
703 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200704 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200705 default "1.0"
706 help
707 The Version Number to store in SMBIOS structures.
708
709config MAINBOARD_SMBIOS_MANUFACTURER
710 string "SMBIOS Manufacturer"
711 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200712 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200713 default MAINBOARD_VENDOR
714 help
715 Override the default Manufacturer stored in SMBIOS structures.
716
717config MAINBOARD_SMBIOS_PRODUCT_NAME
718 string "SMBIOS Product name"
719 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200720 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200721 default MAINBOARD_PART_NUMBER
722 help
723 Override the default Product name stored in SMBIOS structures.
724
Myles Watson45bb25f2009-09-22 18:49:08 +0000725endmenu
726
Martin Roth21c06502016-02-04 19:52:27 -0700727source "payloads/Kconfig"
Peter Stugea758ca22009-09-17 16:21:31 +0000728
Uwe Hermann168b11b2009-10-07 16:15:40 +0000729menu "Debugging"
730
731# TODO: Better help text and detailed instructions.
Patrick Georgi0588d192009-08-12 15:00:51 +0000732config GDB_STUB
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000733 bool "GDB debugging support"
Rudolf Marek65888022012-03-25 20:51:16 +0200734 default n
Denis 'GNUtoo' Carikli3747ba12015-12-10 22:04:56 +0100735 depends on CONSOLE_SERIAL
Patrick Georgi0588d192009-08-12 15:00:51 +0000736 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000737 If enabled, you will be able to set breakpoints for gdb debugging.
Stefan Reinauer8677a232010-12-11 20:33:41 +0000738 See src/arch/x86/lib/c_start.S for details.
Patrick Georgi0588d192009-08-12 15:00:51 +0000739
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200740config GDB_WAIT
741 bool "Wait for a GDB connection"
742 default n
743 depends on GDB_STUB
744 help
745 If enabled, coreboot will wait for a GDB connection.
746
Julius Wernerd82e0cf2015-02-17 17:27:23 -0800747config FATAL_ASSERTS
748 bool "Halt when hitting a BUG() or assertion error"
749 default n
750 help
751 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
752
Stefan Reinauerfe422182012-05-02 16:33:18 -0700753config DEBUG_CBFS
754 bool "Output verbose CBFS debug messages"
755 default n
Stefan Reinauerfe422182012-05-02 16:33:18 -0700756 help
757 This option enables additional CBFS related debug messages.
758
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000759config HAVE_DEBUG_RAM_SETUP
760 def_bool n
761
Uwe Hermann01ce6012010-03-05 10:03:50 +0000762config DEBUG_RAM_SETUP
763 bool "Output verbose RAM init debug messages"
764 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000765 depends on HAVE_DEBUG_RAM_SETUP
Uwe Hermann01ce6012010-03-05 10:03:50 +0000766 help
767 This option enables additional RAM init related debug messages.
768 It is recommended to enable this when debugging issues on your
769 board which might be RAM init related.
770
771 Note: This option will increase the size of the coreboot image.
772
773 If unsure, say N.
774
Patrick Georgie82618d2010-10-01 14:50:12 +0000775config HAVE_DEBUG_CAR
776 def_bool n
777
Peter Stuge5015f792010-11-10 02:00:32 +0000778config DEBUG_CAR
779 def_bool n
780 depends on HAVE_DEBUG_CAR
781
782if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
Uwe Hermanna953f372010-11-10 00:14:32 +0000783# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
784# printk(BIOS_DEBUG, ...) calls.
Patrick Georgie82618d2010-10-01 14:50:12 +0000785config DEBUG_CAR
786 bool "Output verbose Cache-as-RAM debug messages"
787 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000788 depends on HAVE_DEBUG_CAR
Patrick Georgie82618d2010-10-01 14:50:12 +0000789 help
790 This option enables additional CAR related debug messages.
Peter Stuge5015f792010-11-10 02:00:32 +0000791endif
Patrick Georgie82618d2010-10-01 14:50:12 +0000792
Myles Watson80e914ff2010-06-01 19:25:31 +0000793config DEBUG_PIRQ
794 bool "Check PIRQ table consistency"
795 default n
796 depends on GENERATE_PIRQ_TABLE
797 help
798 If unsure, say N.
799
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000800config HAVE_DEBUG_SMBUS
801 def_bool n
802
Uwe Hermann01ce6012010-03-05 10:03:50 +0000803config DEBUG_SMBUS
804 bool "Output verbose SMBus debug messages"
805 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000806 depends on HAVE_DEBUG_SMBUS
Uwe Hermann01ce6012010-03-05 10:03:50 +0000807 help
808 This option enables additional SMBus (and SPD) debug messages.
809
810 Note: This option will increase the size of the coreboot image.
811
812 If unsure, say N.
813
814config DEBUG_SMI
815 bool "Output verbose SMI debug messages"
816 default n
817 depends on HAVE_SMI_HANDLER
Martin Roth3a543182015-09-28 15:27:24 -0600818 select SPI_FLASH_SMM if SPI_CONSOLE
Uwe Hermann01ce6012010-03-05 10:03:50 +0000819 help
820 This option enables additional SMI related debug messages.
821
822 Note: This option will increase the size of the coreboot image.
823
824 If unsure, say N.
825
Stefan Reinauerbc0f7a62010-08-01 15:41:14 +0000826config DEBUG_SMM_RELOCATION
827 bool "Debug SMM relocation code"
828 default n
829 depends on HAVE_SMI_HANDLER
830 help
831 This option enables additional SMM handler relocation related
832 debug messages.
833
834 Note: This option will increase the size of the coreboot image.
835
836 If unsure, say N.
837
Uwe Hermanna953f372010-11-10 00:14:32 +0000838# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
839# printk(BIOS_DEBUG, ...) calls.
840config DEBUG_MALLOC
Stefan Reinauer95a63962012-11-13 17:00:01 -0800841 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
842 bool
Uwe Hermanna953f372010-11-10 00:14:32 +0000843 default n
Uwe Hermanna953f372010-11-10 00:14:32 +0000844 help
845 This option enables additional malloc related debug messages.
846
847 Note: This option will increase the size of the coreboot image.
848
849 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300850
851# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
852# printk(BIOS_DEBUG, ...) calls.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300853config DEBUG_ACPI
Stefan Reinauer95a63962012-11-13 17:00:01 -0800854 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
855 bool
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300856 default n
857 help
858 This option enables additional ACPI related debug messages.
859
860 Note: This option will slightly increase the size of the coreboot image.
861
862 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300863
Uwe Hermanna953f372010-11-10 00:14:32 +0000864# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
865# printk(BIOS_DEBUG, ...) calls.
Myles Watson6c9bc012010-09-07 22:30:15 +0000866config REALMODE_DEBUG
Stefan Reinauer95a63962012-11-13 17:00:01 -0800867 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
868 bool
Myles Watson6c9bc012010-09-07 22:30:15 +0000869 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000870 depends on PCI_OPTION_ROM_RUN_REALMODE
Myles Watson6c9bc012010-09-07 22:30:15 +0000871 help
872 This option enables additional x86emu related debug messages.
873
874 Note: This option will increase the time to emulate a ROM.
875
876 If unsure, say N.
877
Uwe Hermann01ce6012010-03-05 10:03:50 +0000878config X86EMU_DEBUG
879 bool "Output verbose x86emu debug messages"
880 default n
881 depends on PCI_OPTION_ROM_RUN_YABEL
882 help
883 This option enables additional x86emu related debug messages.
884
885 Note: This option will increase the size of the coreboot image.
886
887 If unsure, say N.
888
889config X86EMU_DEBUG_JMP
890 bool "Trace JMP/RETF"
891 default n
892 depends on X86EMU_DEBUG
893 help
894 Print information about JMP and RETF opcodes from x86emu.
895
896 Note: This option will increase the size of the coreboot image.
897
898 If unsure, say N.
899
900config X86EMU_DEBUG_TRACE
901 bool "Trace all opcodes"
902 default n
903 depends on X86EMU_DEBUG
904 help
905 Print _all_ opcodes that are executed by x86emu.
Stefan Reinauer14e22772010-04-27 06:56:47 +0000906
Uwe Hermann01ce6012010-03-05 10:03:50 +0000907 WARNING: This will produce a LOT of output and take a long time.
908
909 Note: This option will increase the size of the coreboot image.
910
911 If unsure, say N.
912
913config X86EMU_DEBUG_PNP
914 bool "Log Plug&Play accesses"
915 default n
916 depends on X86EMU_DEBUG
917 help
918 Print Plug And Play accesses made by option ROMs.
919
920 Note: This option will increase the size of the coreboot image.
921
922 If unsure, say N.
923
924config X86EMU_DEBUG_DISK
925 bool "Log Disk I/O"
926 default n
927 depends on X86EMU_DEBUG
928 help
929 Print Disk I/O related messages.
930
931 Note: This option will increase the size of the coreboot image.
932
933 If unsure, say N.
934
935config X86EMU_DEBUG_PMM
936 bool "Log PMM"
937 default n
938 depends on X86EMU_DEBUG
939 help
940 Print messages related to POST Memory Manager (PMM).
941
942 Note: This option will increase the size of the coreboot image.
943
944 If unsure, say N.
945
946
947config X86EMU_DEBUG_VBE
948 bool "Debug VESA BIOS Extensions"
949 default n
950 depends on X86EMU_DEBUG
951 help
952 Print messages related to VESA BIOS Extension (VBE) functions.
953
954 Note: This option will increase the size of the coreboot image.
955
956 If unsure, say N.
957
958config X86EMU_DEBUG_INT10
959 bool "Redirect INT10 output to console"
960 default n
961 depends on X86EMU_DEBUG
962 help
963 Let INT10 (i.e. character output) calls print messages to debug output.
964
965 Note: This option will increase the size of the coreboot image.
966
967 If unsure, say N.
968
969config X86EMU_DEBUG_INTERRUPTS
970 bool "Log intXX calls"
971 default n
972 depends on X86EMU_DEBUG
973 help
974 Print messages related to interrupt handling.
975
976 Note: This option will increase the size of the coreboot image.
977
978 If unsure, say N.
979
980config X86EMU_DEBUG_CHECK_VMEM_ACCESS
981 bool "Log special memory accesses"
982 default n
983 depends on X86EMU_DEBUG
984 help
985 Print messages related to accesses to certain areas of the virtual
986 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
987
988 Note: This option will increase the size of the coreboot image.
989
990 If unsure, say N.
991
992config X86EMU_DEBUG_MEM
993 bool "Log all memory accesses"
994 default n
995 depends on X86EMU_DEBUG
996 help
997 Print memory accesses made by option ROM.
998 Note: This also includes accesses to fetch instructions.
999
1000 Note: This option will increase the size of the coreboot image.
1001
1002 If unsure, say N.
1003
1004config X86EMU_DEBUG_IO
1005 bool "Log IO accesses"
1006 default n
1007 depends on X86EMU_DEBUG
1008 help
1009 Print I/O accesses made by option ROM.
1010
1011 Note: This option will increase the size of the coreboot image.
1012
1013 If unsure, say N.
1014
Denis 'GNUtoo' Carikli4cdc5d62013-05-15 00:19:49 +02001015config X86EMU_DEBUG_TIMINGS
1016 bool "Output timing information"
1017 default n
1018 depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
1019 help
1020 Print timing information needed by i915tool.
1021
1022 If unsure, say N.
1023
Stefan Reinauerdfb098d2011-11-17 12:50:54 -08001024config DEBUG_TPM
1025 bool "Output verbose TPM debug messages"
1026 default n
1027 depends on TPM
1028 help
1029 This option enables additional TPM related debug messages.
1030
Stefan Reinauer1c56d9b2012-05-10 11:27:32 -07001031config DEBUG_SPI_FLASH
1032 bool "Output verbose SPI flash debug messages"
1033 default n
1034 depends on SPI_FLASH
1035 help
1036 This option enables additional SPI flash related debug messages.
1037
Kyösti Mälkki3be80cc2013-06-06 10:46:37 +03001038config DEBUG_USBDEBUG
1039 bool "Output verbose USB 2.0 EHCI debug dongle messages"
1040 default n
1041 depends on USBDEBUG
1042 help
1043 This option enables additional USB 2.0 debug dongle related messages.
1044
1045 Select this to debug the connection of usbdebug dongle. Note that
1046 you need some other working console to receive the messages.
1047
Stefan Reinauer8e073822012-04-04 00:07:22 +02001048if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1049# Only visible with the right southbridge and loglevel.
1050config DEBUG_INTEL_ME
1051 bool "Verbose logging for Intel Management Engine"
1052 default n
1053 help
1054 Enable verbose logging for Intel Management Engine driver that
1055 is present on Intel 6-series chipsets.
1056endif
1057
Rudolf Marek7f0e9302011-09-02 23:23:41 +02001058config TRACE
1059 bool "Trace function calls"
1060 default n
1061 help
1062 If enabled, every function will print information to console once
1063 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1064 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
Ben Gardner8420ad42015-11-18 10:46:53 -06001065 of calling function. Please note some printk related functions
Rudolf Marek7f0e9302011-09-02 23:23:41 +02001066 are omitted from trace to have good looking console dumps.
Stefan Reinauerd37ab452012-12-18 16:23:28 -08001067
1068config DEBUG_COVERAGE
1069 bool "Debug code coverage"
1070 default n
1071 depends on COVERAGE
1072 help
1073 If enabled, the code coverage hooks in coreboot will output some
1074 information about the coverage data that is dumped.
1075
Uwe Hermann168b11b2009-10-07 16:15:40 +00001076endmenu
1077
Myles Watsond73c1b52009-10-26 15:14:07 +00001078# These probably belong somewhere else, but they are needed somewhere.
Myles Watsond73c1b52009-10-26 15:14:07 +00001079config ENABLE_APIC_EXT_ID
1080 bool
1081 default n
Myles Watson2e672732009-11-12 16:38:03 +00001082
1083config WARNINGS_ARE_ERRORS
1084 bool
Edward O'Callaghan63f6dc72014-11-18 03:17:54 +11001085 default y
Patrick Georgi436f99b2009-11-27 16:55:13 +00001086
Martin Roth77c67b32015-06-25 09:36:27 -06001087# TODO: Remove this when all platforms are fixed.
1088config IASL_WARNINGS_ARE_ERRORS
1089 def_bool y
1090 help
1091 Select to Fail the build if a IASL generates a warning.
1092 This will be defaulted to disabled for the platforms that
1093 currently fail. This allows the REST of the platforms to
1094 have this check enabled while we're working to get those
1095 boards fixed.
1096
1097 DO NOT ADD TO ANY ADDITIONAL PLATFORMS INSTEAD OF FIXING
1098 THE ASL.
1099
Peter Stuge51eafde2010-10-13 06:23:02 +00001100# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1101# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1102# mutually exclusive. One of these options must be selected in the
1103# mainboard Kconfig if the chipset supports enabling and disabling of
1104# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1105# in mainboard/Kconfig to know if the button should be enabled or not.
1106
1107config POWER_BUTTON_DEFAULT_ENABLE
1108 def_bool n
1109 help
1110 Select when the board has a power button which can optionally be
1111 disabled by the user.
1112
1113config POWER_BUTTON_DEFAULT_DISABLE
1114 def_bool n
1115 help
1116 Select when the board has a power button which can optionally be
1117 enabled by the user, e.g. when the board ships with a jumper over
1118 the power switch contacts.
1119
1120config POWER_BUTTON_FORCE_ENABLE
1121 def_bool n
1122 help
1123 Select when the board requires that the power button is always
1124 enabled.
1125
1126config POWER_BUTTON_FORCE_DISABLE
1127 def_bool n
1128 help
1129 Select when the board requires that the power button is always
1130 disabled, e.g. when it has been hardwired to ground.
1131
1132config POWER_BUTTON_IS_OPTIONAL
1133 bool
1134 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1135 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1136 help
1137 Internal option that controls ENABLE_POWER_BUTTON visibility.
Duncan Laurie72748002013-10-31 08:26:23 -07001138
1139config REG_SCRIPT
1140 bool
Duncan Laurie72748002013-10-31 08:26:23 -07001141 default n
1142 help
1143 Internal option that controls whether we compile in register scripts.
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07001144
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07001145config MAX_REBOOT_CNT
1146 int
1147 default 3
Timothy Pearson17ada2e2015-03-18 01:31:34 -05001148 help
1149 Internal option that sets the maximum number of bootblock executions allowed
1150 with the normal image enabled before assuming the normal image is defective
Vadim Bendebury9c9c3362014-07-23 09:40:02 -07001151 and switching to the fallback image.
Martin Roth59ff3402016-02-09 09:06:46 -07001152
1153config CBFS_SIZE
1154 hex
1155 default ROM_SIZE
1156 help
1157 This is the part of the ROM actually managed by CBFS. Set it to be
1158 equal to the full rom size if that hasn't been overridden by the
1159 chipset or mainboard.