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review.coreboot.org / coreboot / ec5a947b44f1f2bd2bd90071df2617de608cd1c2 / . / src / vendorcode / amd / pi / 00670F00 / AMD.h
blob: c4d56c92932a0b777904dc5bb38e53c6b99fee38 [file] [log] [blame]
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Agesa structures and definitions
6 *
7 * Contains AMD AGESA core interface
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: Include
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]12 * @e \$Revision$ @e \$Date$
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]13 */
14 /*****************************************************************************
15 *
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]16 * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are met:
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
27 * its contributors may be used to endorse or promote products derived
28 * from this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
32 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
34 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
39 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ***************************************************************************/
42
Martin Rothae016342017-11-16 22:46:56 -0700[diff] [blame]43#include "check_for_wrapper.h"
44
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]45#ifndef _AMD_H_
46#define _AMD_H_
47
Marshall Dawsonf3093882016-10-15 09:45:44 -0600[diff] [blame]48#define Int16FromChar(a,b) (UINT16)((a) << 0 | (b) << 8)
49#define Int32FromChar(a,b,c,d) (UINT32)((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
50#define Int64FromChar(a,b,c,d,e,f,g,h) ((UINT64)(Int32FromChar(a,b,c,d)<<32) | (UINT64)Int32FromChar(e,f,g,h))
51
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]52#define AGESA_REVISION "Arch2008"
Marshall Dawsonf3093882016-10-15 09:45:44 -0600[diff] [blame]53#define AGESA_ID {'A', 'G', 'E', 'S', 'A', 0x00, 0x00, 0x00}
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]54
55//
56//
57// AGESA Types and Definitions
58//
59//
60#define LAST_ENTRY 0xFFFFFFFFul
Marshall Dawsonf3093882016-10-15 09:45:44 -0600[diff] [blame]61#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
62#define MODULE_SIGNATURE Int32FromChar ('$', 'M', 'O', 'D')
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]63#define IOCF8 0xCF8
64#define IOCFC 0xCFC
65
66/// The return status for all AGESA public services.
67///
68/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
69/// will have log entries with more detail.
70///
71typedef enum {
72 AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged.
73 AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested.
74 ///< Not logged.
75 AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided.
76 ///< Example, memory address not installed, heap buffer handle not found.
77 ///< Not Logged.
78 // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
79 AGESA_ALERT, ///< An observed condition, but no loss of function. See Log.
80 AGESA_WARNING, ///< Possible or minor loss of function. See Log.
81 AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log.
82 AGESA_CRITICAL, ///< Continue boot only to notify user. See Log.
83 AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems
84 ///< may not be able to reliably produce log events.
85 AgesaStatusMax ///< Not a status, for limit checking.
86} AGESA_STATUS;
87
88/// For checking whether a status is at or above the mandatory log level.
89#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
90
91/**
92 * Callout method to the host environment.
93 *
94 * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
95 *
96 * @param[in] Function The specific callout function being invoked.
97 * @param[in] FcnData Function specific data item.
98 * @param[in,out] ConfigPtr Reference to Callout params.
99 */
100typedef AGESA_STATUS (*CALLOUT_ENTRY) (
101 IN UINT32 Function,
102 IN UINTN FcnData,
103 IN OUT VOID *ConfigPtr
104 );
105
106typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
107typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
108
109///This allocation type is used by the AmdCreateStruct entry point
110typedef enum {
111 PreMemHeap = 0, ///< Create heap in cache.
112 PostMemDram, ///< Create heap in memory.
113 ByHost ///< Create heap by Host.
114} ALLOCATION_METHOD;
115
116/// These width descriptors are used by the library function, and others, to specify the data size
117typedef enum ACCESS_WIDTH {
118 AccessWidthNone = 0, ///< dummy access width
119 AccessWidth8 = 1, ///< Access width is 8 bits.
120 AccessWidth16, ///< Access width is 16 bits.
121 AccessWidth32, ///< Access width is 32 bits.
122 AccessWidth64, ///< Access width is 64 bits.
123
124 AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
125 AccessS3SaveWidth16, ///< Save 16 bits data.
126 AccessS3SaveWidth32, ///< Save 32 bits data.
127 AccessS3SaveWidth64, ///< Save 64 bits data.
128} ACCESS_WIDTH;
129
130/// AGESA struct name
131typedef enum {
132 // AGESA BASIC FUNCTIONS
Marshall Dawsonf3093882016-10-15 09:45:44 -0600[diff] [blame]133 AMD_INIT_RECOVERY = 0x00021000, ///< AmdInitRecovery entry point handle
134 AMD_CREATE_STRUCT = 0x00022000, ///< AmdCreateStruct handle
135 AMD_INIT_EARLY = 0x00023000, ///< AmdInitEarly entry point handle
136 AMD_INIT_ENV = 0x00024000, ///< AmdInitEnv entry point handle
137 AMD_INIT_LATE = 0x00025000, ///< AmdInitLate entry point handle
138 AMD_INIT_MID = 0x00026000, ///< AmdInitMid entry point handle
139 AMD_INIT_POST = 0x00027000, ///< AmdInitPost entry point handle
140 AMD_INIT_RESET = 0x00028000, ///< AmdInitReset entry point handle
141 AMD_INIT_RESUME = 0x00029000, ///< AmdInitResume entry point handle
142 AMD_RELEASE_STRUCT = 0x0002A000, ///< AmdReleaseStruct handle
143 AMD_S3LATE_RESTORE = 0x0002B000, ///< AmdS3LateRestore entry point handle
144 AMD_GET_APIC_ID = 0x0002C000, ///< AmdGetApicId entry point handle
145 AMD_GET_PCI_ADDRESS = 0x0002D000, ///< AmdGetPciAddress entry point handle
146 AMD_IDENTIFY_CORE = 0x0002E000, ///< AmdIdentifyCore general service handle
147 AMD_READ_EVENT_LOG = 0x0002F000, ///< AmdReadEventLog general service handle
148 AMD_GET_EXECACHE_SIZE = 0x00030000, ///< AmdGetAvailableExeCacheSize general service handle
149 AMD_LATE_RUN_AP_TASK = 0x00031000, ///< AmdLateRunApTask entry point handle
150 AMD_IDENTIFY_DIMMS = 0x00032000, ///< AmdIdentifyDimm general service handle
151 AMD_GET_2D_DATA_EYE = 0x00033000, ///< AmdGet2DDataEye general service handle
152 AMD_S3FINAL_RESTORE = 0x00034000, ///< AmdS3FinalRestore entry point handle
153 AMD_INIT_RTB = 0x00035000, ///< AmdInitRtb entry point handle
154 AMD_HEAP_ALLOCATE_BUFFER = 0x00038000,
155 AMD_HEAP_DEALLOCATE_BUFFER = 0x00039000,
156 FCH_INIT_RESET = 0x00040000,
157 FCH_INIT_ENV = 0x00041000,
158 FCH_INIT_MID = 0x00042000,
159 FCH_INIT_LATE = 0x00043000,
160 FCH_INIT_S3_EARLY_RESTORE = 0x00044000,
161 FCH_INIT_S3_LATE_RESTORE = 0x00045000,
Kyösti Mälkkid2fa3372017-09-24 22:03:55 +0300[diff] [blame]162 AMD_SET_VALUE_invalid = 0x00081000,
163 AMD_GET_VALUE_invalid = 0x00082000
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]164} AGESA_STRUCT_NAME;
165
166 /* ResetType constant values */
167#define WARM_RESET_WHENEVER 1
168#define COLD_RESET_WHENEVER 2
169#define WARM_RESET_IMMEDIATELY 3
170#define COLD_RESET_IMMEDIATELY 4
171
172
173// AGESA Structures
174
175/// The standard header for all AGESA services.
176/// For internal AGESA naming conventions, see @ref amdconfigparamname .
177typedef struct {
Marshall Dawsonf3093882016-10-15 09:45:44 -0600[diff] [blame]178 IN VOID * ImageBasePtr; ///< The AGESA Image base address.
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]179 IN UINT32 Func; ///< The service desired
Marshall Dawsonf3093882016-10-15 09:45:44 -0600[diff] [blame]180 IN VOID * AltImageBasePtr; ///< Alternate Image location
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]181 IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
182 IN UINT8 HeapStatus; ///< For heap status from boot time slide.
183 IN UINT64 HeapBasePtr; ///< Location of the heap
184 IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
185} AMD_CONFIG_PARAMS;
186
187
188/// Create Struct Interface.
189typedef struct {
190 IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
191 IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init
192 IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation
193 IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only.
194 IN OUT VOID *NewStructPtr; ///< The struct for the service.
195 ///< The struct to init for ByHost allocation,
196 ///< the initialized struct on return.
197} AMD_INTERFACE_PARAMS;
198
199#define FUNC_0 0 // bit-placed for PCI address creation
200#define FUNC_1 1
201#define FUNC_2 2
202#define FUNC_3 3
203#define FUNC_4 4
204#define FUNC_5 5
205#define FUNC_6 6
206#define FUNC_7 7
207
208/// AGESA Binary module header structure
209typedef struct {
210 IN UINT32 Signature; ///< Binary Signature
211 IN CHAR8 CreatorID[8]; ///< 8 characters ID
212 IN CHAR8 Version[12]; ///< 12 characters version
213 IN UINT32 ModuleInfoOffset; ///< Offset of module
214 IN UINT32 EntryPointAddress; ///< Entry address
215 IN UINT32 ImageBase; ///< Image base
216 IN UINT32 RelocTableOffset; ///< Relocate Table offset
217 IN UINT32 ImageSize; ///< Size
218 IN UINT16 Checksum; ///< Checksum
219 IN UINT8 ImageType; ///< Type
220 IN UINT8 V_Reserved; ///< Reserved
221} AMD_IMAGE_HEADER;
222/// AGESA Binary module header structure
223typedef struct _AMD_MODULE_HEADER {
224 IN UINT32 ModuleHeaderSignature; ///< Module signature
225 IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
226 IN CHAR8 ModuleVersion[12]; ///< 12 characters version
227 IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher
228 IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link
229} AMD_MODULE_HEADER;
230
231// AMD_CODE_HEADER Signatures.
232#define AGESA_CODE_SIGNATURE {'!', '!', '!', 'A', 'G', 'E', 'S', 'A'}
233#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
234#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
235
236/// AGESA_CODE_SIGNATURE
237typedef struct {
238 IN CHAR8 Signature[8]; ///< code header Signature
239 IN CHAR8 ComponentName[16]; ///< 16 character name of the code module
240 IN CHAR8 Version[12]; ///< 12 character version string
241 IN CHAR8 TerminatorNull; ///< null terminated string
242 IN CHAR8 VerReserved[7]; ///< reserved space
243} AMD_CODE_HEADER;
244
245/// Extended PCI address format
246typedef struct {
247 IN OUT UINT32 Register:12; ///< Register offset
248 IN OUT UINT32 Function:3; ///< Function number
249 IN OUT UINT32 Device:5; ///< Device number
250 IN OUT UINT32 Bus:8; ///< Bus number
251 IN OUT UINT32 Segment:4; ///< Segment
252} EXT_PCI_ADDR;
253
254/// Union type for PCI address
255typedef union _PCI_ADDR {
256 IN UINT32 AddressValue; ///< Formal address
257 IN EXT_PCI_ADDR Address; ///< Extended address
258} PCI_ADDR;
259
260// SBDFO - Segment Bus Device Function Offset
261// 31:28 Segment (4-bits)
262// 27:20 Bus (8-bits)
263// 19:15 Device (5-bits)
264// 14:12 Function(3-bits)
265// 11:00 Offset (12-bits)
266
267#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
268 (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
269#define ILLEGAL_SBDFO 0xFFFFFFFFul
270
271/// CPUID data received registers format
272typedef struct {
273 OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
274 OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
275 OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
276 OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
277} CPUID_DATA;
278
279// Topology Services definitions and macros
280#define TOPOLOGY_LIST_TERMINAL 0xFF ///< End of list.
281
282
283#ifndef BIT0
284 #define BIT0 0x0000000000000001ull
285#endif
286#ifndef BIT1
287 #define BIT1 0x0000000000000002ull
288#endif
289#ifndef BIT2
290 #define BIT2 0x0000000000000004ull
291#endif
292#ifndef BIT3
293 #define BIT3 0x0000000000000008ull
294#endif
295#ifndef BIT4
296 #define BIT4 0x0000000000000010ull
297#endif
298#ifndef BIT5
299 #define BIT5 0x0000000000000020ull
300#endif
301#ifndef BIT6
302 #define BIT6 0x0000000000000040ull
303#endif
304#ifndef BIT7
305 #define BIT7 0x0000000000000080ull
306#endif
307#ifndef BIT8
308 #define BIT8 0x0000000000000100ull
309#endif
310#ifndef BIT9
311 #define BIT9 0x0000000000000200ull
312#endif
313#ifndef BIT10
314 #define BIT10 0x0000000000000400ull
315#endif
316#ifndef BIT11
317 #define BIT11 0x0000000000000800ull
318#endif
319#ifndef BIT12
320 #define BIT12 0x0000000000001000ull
321#endif
322#ifndef BIT13
323 #define BIT13 0x0000000000002000ull
324#endif
325#ifndef BIT14
326 #define BIT14 0x0000000000004000ull
327#endif
328#ifndef BIT15
329 #define BIT15 0x0000000000008000ull
330#endif
331#ifndef BIT16
332 #define BIT16 0x0000000000010000ull
333#endif
334#ifndef BIT17
335 #define BIT17 0x0000000000020000ull
336#endif
337#ifndef BIT18
338 #define BIT18 0x0000000000040000ull
339#endif
340#ifndef BIT19
341 #define BIT19 0x0000000000080000ull
342#endif
343#ifndef BIT20
344 #define BIT20 0x0000000000100000ull
345#endif
346#ifndef BIT21
347 #define BIT21 0x0000000000200000ull
348#endif
349#ifndef BIT22
350 #define BIT22 0x0000000000400000ull
351#endif
352#ifndef BIT23
353 #define BIT23 0x0000000000800000ull
354#endif
355#ifndef BIT24
356 #define BIT24 0x0000000001000000ull
357#endif
358#ifndef BIT25
359 #define BIT25 0x0000000002000000ull
360#endif
361#ifndef BIT26
362 #define BIT26 0x0000000004000000ull
363#endif
364#ifndef BIT27
365 #define BIT27 0x0000000008000000ull
366#endif
367#ifndef BIT28
368 #define BIT28 0x0000000010000000ull
369#endif
370#ifndef BIT29
371 #define BIT29 0x0000000020000000ull
372#endif
373#ifndef BIT30
374 #define BIT30 0x0000000040000000ull
375#endif
376#ifndef BIT31
377 #define BIT31 0x0000000080000000ull
378#endif
379#ifndef BIT32
380 #define BIT32 0x0000000100000000ull
381#endif
382#ifndef BIT33
383 #define BIT33 0x0000000200000000ull
384#endif
385#ifndef BIT34
386 #define BIT34 0x0000000400000000ull
387#endif
388#ifndef BIT35
389 #define BIT35 0x0000000800000000ull
390#endif
391#ifndef BIT36
392 #define BIT36 0x0000001000000000ull
393#endif
394#ifndef BIT37
395 #define BIT37 0x0000002000000000ull
396#endif
397#ifndef BIT38
398 #define BIT38 0x0000004000000000ull
399#endif
400#ifndef BIT39
401 #define BIT39 0x0000008000000000ull
402#endif
403#ifndef BIT40
404 #define BIT40 0x0000010000000000ull
405#endif
406#ifndef BIT41
407 #define BIT41 0x0000020000000000ull
408#endif
409#ifndef BIT42
410 #define BIT42 0x0000040000000000ull
411#endif
412#ifndef BIT43
413 #define BIT43 0x0000080000000000ull
414#endif
415#ifndef BIT44
416 #define BIT44 0x0000100000000000ull
417#endif
418#ifndef BIT45
419 #define BIT45 0x0000200000000000ull
420#endif
421#ifndef BIT46
422 #define BIT46 0x0000400000000000ull
423#endif
424#ifndef BIT47
425 #define BIT47 0x0000800000000000ull
426#endif
427#ifndef BIT48
428 #define BIT48 0x0001000000000000ull
429#endif
430#ifndef BIT49
431 #define BIT49 0x0002000000000000ull
432#endif
433#ifndef BIT50
434 #define BIT50 0x0004000000000000ull
435#endif
436#ifndef BIT51
437 #define BIT51 0x0008000000000000ull
438#endif
439#ifndef BIT52
440 #define BIT52 0x0010000000000000ull
441#endif
442#ifndef BIT53
443 #define BIT53 0x0020000000000000ull
444#endif
445#ifndef BIT54
446 #define BIT54 0x0040000000000000ull
447#endif
448#ifndef BIT55
449 #define BIT55 0x0080000000000000ull
450#endif
451#ifndef BIT56
452 #define BIT56 0x0100000000000000ull
453#endif
454#ifndef BIT57
455 #define BIT57 0x0200000000000000ull
456#endif
457#ifndef BIT58
458 #define BIT58 0x0400000000000000ull
459#endif
460#ifndef BIT59
461 #define BIT59 0x0800000000000000ull
462#endif
463#ifndef BIT60
464 #define BIT60 0x1000000000000000ull
465#endif
466#ifndef BIT61
467 #define BIT61 0x2000000000000000ull
468#endif
469#ifndef BIT62
470 #define BIT62 0x4000000000000000ull
471#endif
472#ifndef BIT63
473 #define BIT63 0x8000000000000000ull
474#endif
475
476#endif // _AMD_H_