Subrata Banik | 30a0114 | 2023-03-22 00:35:42 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <cpu/x86/mtrr.h> |
| 5 | #include <ip_checksum.h> |
| 6 | #include <intelbasecode/ramtop.h> |
| 7 | #include <pc80/mc146818rtc.h> |
| 8 | #include <stdint.h> |
| 9 | |
| 10 | /* We need a region in CMOS to store the RAMTOP address */ |
| 11 | |
| 12 | #define RAMTOP_SIGNATURE 0x52544F50 /* 'RTOP' */ |
| 13 | |
Subrata Banik | 30a0114 | 2023-03-22 00:35:42 +0530 | [diff] [blame] | 14 | /* |
Sean Rhodes | bc602b8 | 2023-04-19 08:41:24 +0100 | [diff] [blame] | 15 | * Address of the ramtop byte in CMOS. Should be reserved |
Subrata Banik | 30a0114 | 2023-03-22 00:35:42 +0530 | [diff] [blame] | 16 | * in mainboards' cmos.layout and not covered by checksum. |
| 17 | */ |
| 18 | |
| 19 | #if CONFIG(USE_OPTION_TABLE) |
| 20 | #include "option_table.h" |
Sean Rhodes | 579e03a | 2023-04-18 21:18:30 +0100 | [diff] [blame] | 21 | |
Sean Rhodes | bfe2cd4 | 2023-05-02 21:02:43 +0100 | [diff] [blame] | 22 | #ifndef CMOS_VSTART_ramtop |
| 23 | #error "The `ramtop` CMOS entry is missing, please add it to your cmos.layout." |
| 24 | #endif |
| 25 | |
Sean Rhodes | 579e03a | 2023-04-18 21:18:30 +0100 | [diff] [blame] | 26 | #if CMOS_VSTART_ramtop % 8 != 0 |
| 27 | #error "The `ramtop` CMOS entry needs to be byte aligned, check your cmos.layout." |
| 28 | #endif // CMOS_VSTART_ramtop % 8 != 0 |
| 29 | |
Sean Rhodes | 4265d52 | 2023-05-02 20:54:40 +0100 | [diff] [blame] | 30 | #if CMOS_VLEN_ramtop != (10 * 8) |
| 31 | #error "The `ramtop` CMOS entry needs to be 10 bytes long, check your cmos.layout." |
| 32 | #endif // CMOS_VLEN_ramtop != (10 * 8) |
Sean Rhodes | 579e03a | 2023-04-18 21:18:30 +0100 | [diff] [blame] | 33 | |
| 34 | #else |
| 35 | #define CMOS_VSTART_ramtop 800 |
| 36 | #endif // CONFIG(USE_OPTION_TABLE) |
Subrata Banik | 30a0114 | 2023-03-22 00:35:42 +0530 | [diff] [blame] | 37 | |
| 38 | struct ramtop_table { |
| 39 | uint32_t signature; |
| 40 | uint32_t addr; |
| 41 | uint16_t checksum; |
| 42 | } __packed; |
| 43 | |
| 44 | /* Read and validate ramtop_table structure from CMOS */ |
| 45 | static int ramtop_cmos_read(struct ramtop_table *ramtop) |
| 46 | { |
| 47 | u8 i, *p; |
| 48 | u16 csum; |
| 49 | |
| 50 | for (p = (u8 *)ramtop, i = 0; i < sizeof(*ramtop); i++, p++) |
Sean Rhodes | 579e03a | 2023-04-18 21:18:30 +0100 | [diff] [blame] | 51 | *p = cmos_read((CMOS_VSTART_ramtop / 8) + i); |
Subrata Banik | 30a0114 | 2023-03-22 00:35:42 +0530 | [diff] [blame] | 52 | |
| 53 | /* Verify signature */ |
| 54 | if (ramtop->signature != RAMTOP_SIGNATURE) { |
| 55 | printk(BIOS_DEBUG, "ramtop_table invalid signature\n"); |
| 56 | return -1; |
| 57 | } |
| 58 | |
| 59 | /* Verify checksum over signature and counter only */ |
| 60 | csum = compute_ip_checksum(ramtop, offsetof(struct ramtop_table, checksum)); |
| 61 | |
| 62 | if (csum != ramtop->checksum) { |
| 63 | printk(BIOS_DEBUG, "ramtop_table checksum mismatch\n"); |
| 64 | return -1; |
| 65 | } |
| 66 | |
| 67 | return 0; |
| 68 | } |
| 69 | |
| 70 | /* Write ramtop_table structure to CMOS */ |
| 71 | static void ramtop_cmos_write(struct ramtop_table *ramtop) |
| 72 | { |
| 73 | u8 i, *p; |
| 74 | |
| 75 | /* Checksum over signature and counter only */ |
| 76 | ramtop->checksum = compute_ip_checksum( |
| 77 | ramtop, offsetof(struct ramtop_table, checksum)); |
| 78 | |
| 79 | for (p = (u8 *)ramtop, i = 0; i < sizeof(*ramtop); i++, p++) |
Sean Rhodes | 579e03a | 2023-04-18 21:18:30 +0100 | [diff] [blame] | 80 | cmos_write(*p, (CMOS_VSTART_ramtop / 8) + i); |
Subrata Banik | 30a0114 | 2023-03-22 00:35:42 +0530 | [diff] [blame] | 81 | } |
| 82 | |
| 83 | /* Update the RAMTOP if required based on the input top_of_ram address */ |
| 84 | void update_ramtop(uint32_t addr) |
| 85 | { |
| 86 | struct ramtop_table ramtop; |
| 87 | |
| 88 | /* Read and update ramtop (if required) */ |
| 89 | if (ramtop_cmos_read(&ramtop) < 0) { |
| 90 | /* Structure invalid, re-initialize */ |
| 91 | ramtop.signature = RAMTOP_SIGNATURE; |
| 92 | ramtop.addr = 0; |
| 93 | } |
| 94 | |
| 95 | /* Update ramtop if required */ |
| 96 | if (ramtop.addr == addr) |
| 97 | return; |
| 98 | |
| 99 | ramtop.addr = addr; |
| 100 | |
| 101 | /* Write the new top_of_ram address to CMOS */ |
| 102 | ramtop_cmos_write(&ramtop); |
| 103 | |
| 104 | printk(BIOS_DEBUG, "Updated the RAMTOP address into CMOS 0x%x\n", ramtop.addr); |
| 105 | } |
| 106 | |
| 107 | static uint32_t get_ramtop_addr(void) |
| 108 | { |
| 109 | struct ramtop_table ramtop; |
| 110 | |
| 111 | if (ramtop_cmos_read(&ramtop) < 0) |
| 112 | return 0; |
| 113 | |
| 114 | return ramtop.addr; |
| 115 | } |
| 116 | |
| 117 | /* Early caching of top_of_ram region */ |
| 118 | void early_ramtop_enable_cache_range(void) |
| 119 | { |
| 120 | uint32_t ramtop = get_ramtop_addr(); |
| 121 | if (!ramtop) |
| 122 | return; |
| 123 | |
| 124 | int mtrr = get_free_var_mtrr(); |
| 125 | if (mtrr == -1) { |
| 126 | printk(BIOS_WARNING, "ramtop_table update failure due to no free MTRR available!\n"); |
| 127 | return; |
| 128 | } |
| 129 | /* |
| 130 | * We need to make sure late romstage (including FSP-M post mem) will be run |
| 131 | * cached. Caching 16MB below ramtop is a safe to cover late romstage. |
| 132 | */ |
| 133 | set_var_mtrr(mtrr, ramtop - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); |
| 134 | } |