Angel Pons | 6ad9176 | 2020-04-03 01:23:24 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 2 | |
| 3 | #include <arch/io.h> |
| 4 | #include <bootstate.h> |
| 5 | #include <cf9_reset.h> |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 6 | #include <device/pci_def.h> |
| 7 | #include <device/pci_ids.h> |
| 8 | #include <device/pci_ops.h> |
| 9 | #include <gpio.h> |
| 10 | #include <hwilib.h> |
| 11 | #include <intelblocks/lpc_lib.h> |
| 12 | #include <intelblocks/pcr.h> |
| 13 | #include <soc/pcr_ids.h> |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 14 | #include <baseboard/variants.h> |
| 15 | #include <types.h> |
| 16 | |
| 17 | #define TX_DWORD3 0xa8c |
| 18 | |
| 19 | void variant_mainboard_final(void) |
| 20 | { |
| 21 | struct device *dev = NULL; |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 22 | |
| 23 | /* PIR6 register mapping for PCIe root ports |
| 24 | * INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC# |
| 25 | */ |
| 26 | pcr_write16(PID_ITSS, 0x314c, 0x2103); |
| 27 | |
| 28 | /* Enable CLKRUN_EN for power gating LPC */ |
| 29 | lpc_enable_pci_clk_cntl(); |
| 30 | |
| 31 | /* |
| 32 | * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2 |
| 33 | * offset 0x341D bit3 and bit0. |
| 34 | * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2 |
| 35 | * offset 0x341C bit [3:0]. |
| 36 | */ |
| 37 | pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN)); |
| 38 | |
Werner Zeh | 1412ffa | 2021-07-20 07:33:20 +0200 | [diff] [blame] | 39 | /* Set Master Enable for on-board PCI device if allowed. */ |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 40 | dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); |
| 41 | if (dev) { |
Werner Zeh | 1412ffa | 2021-07-20 07:33:20 +0200 | [diff] [blame] | 42 | if (CONFIG(PCI_ALLOW_BUS_MASTER)) |
| 43 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 44 | |
Werner Zeh | 4f7fe49 | 2019-11-08 09:50:20 +0100 | [diff] [blame] | 45 | /* Disable clock outputs 0-3 (CLKOUT) for upstream |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 46 | * XIO2001 PCIe to PCI Bridge. |
| 47 | */ |
| 48 | struct device *parent = dev->bus->dev; |
| 49 | if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) |
Werner Zeh | 4f7fe49 | 2019-11-08 09:50:20 +0100 | [diff] [blame] | 50 | pci_write_config8(parent, 0xd8, 0x0F); |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 51 | } |
| 52 | |
| 53 | /* Disable clock outputs 2-5 (CLKOUT) for another XIO2001 PCIe to PCI |
| 54 | * Bridge on this mainboard. |
| 55 | */ |
| 56 | dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0); |
| 57 | if (dev) { |
| 58 | struct device *parent = dev->bus->dev; |
| 59 | if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) |
| 60 | pci_write_config8(parent, 0xd8, 0x3c); |
| 61 | } |
| 62 | |
| 63 | /* Set Full Reset Bit in Reset Control Register (I/O port CF9h). |
| 64 | * When Bit 3 is set to 1 and then the reset button is pressed the PCH |
| 65 | * will drive SLP_S3 active (low). SLP_S3 is then used on the mainboard |
| 66 | * to generate the right reset timing. |
| 67 | */ |
| 68 | outb(FULL_RST, RST_CNT); |
| 69 | } |
| 70 | |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 71 | static void finalize_boot(void *unused) |
| 72 | { |
| 73 | /* Set coreboot ready LED. */ |
| 74 | gpio_output(CNV_RGI_DT, 1); |
| 75 | } |
| 76 | |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 77 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); |