Lee Leahy | 5cb9dda | 2015-05-01 10:34:54 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * Copyright (C) 2015 Intel Corp. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc. |
| 19 | */ |
| 20 | |
| 21 | #include <arch/io.h> |
| 22 | #include <soc/gpio.h> |
| 23 | #include <soc/lpc.h> |
| 24 | #include <soc/pci_devs.h> |
| 25 | #include <soc/romstage.h> |
| 26 | |
| 27 | /* |
| 28 | * return family number and internal pad number in that community |
| 29 | * by pad number and which community it is in. |
| 30 | */ |
| 31 | |
| 32 | |
| 33 | |
| 34 | /* family number in high byte and inner pad number in lowest byte */ |
| 35 | |
Lee Leahy | 3c4053f | 2015-09-17 12:35:10 -0700 | [diff] [blame] | 36 | void mainboard_pre_console_init(void) |
Lee Leahy | 5cb9dda | 2015-05-01 10:34:54 -0700 | [diff] [blame] | 37 | { |
| 38 | uint32_t reg; |
| 39 | uint32_t *pad_config_reg; |
| 40 | |
| 41 | /* Enable the UART hardware for COM1. */ |
| 42 | reg = 1; |
| 43 | pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); |
| 44 | |
| 45 | /* |
| 46 | * Set up the pads to select the UART function |
| 47 | * AD12 SW16(UART1_DATAIN/UART0_DATAIN) - Setting Mode 2 for UART0_RXD |
| 48 | * AD10 SW20(UART1_DATAOUT/UART0_DATAOUT) - Setting Mode 2 for UART0_TXD |
| 49 | */ |
| 50 | pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_RXD_PAD); |
| 51 | write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, |
| 52 | M2)); |
| 53 | |
| 54 | pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_TXD_PAD); |
| 55 | write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, |
| 56 | M2)); |
| 57 | } |