Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 1 | /* |
| 2 | * inteltool - dump all registers on an Intel CPU + chipset based system. |
| 3 | * |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 4 | * Copyright (C) 2008-2010 by coresystems GmbH |
| 5 | * |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 18 | */ |
| 19 | |
| 20 | |
| 21 | #include <stdio.h> |
| 22 | #include <stdlib.h> |
Stefan Reinauer | a7b296d | 2011-11-14 12:40:34 -0800 | [diff] [blame] | 23 | #include <inttypes.h> |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 24 | #include "inteltool.h" |
| 25 | |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 26 | static const io_register_t sandybridge_mch_registers[] = { |
| 27 | /* Channel 0 */ |
| 28 | { 0x4000, 4, "TC_DBP_C0" }, // Timing of DDR Bin Parameters |
| 29 | { 0x4004, 4, "TC_RAP_C0" }, // Timing of DDR Regular Access Parameters |
| 30 | { 0x4028, 4, "SC_IO_LATENCY_C0" }, // IO Latency Configuration |
| 31 | { 0x42A4, 4, "TC_SRFTP_C0" }, // Self-Refresh Timing Parameters |
| 32 | { 0x40B0, 4, "PM_PDWN_config_C0" }, // Power-down Configuration |
| 33 | { 0x4294, 4, "TC_RFP_C0" }, // Refresh Parameters |
| 34 | { 0x4298, 4, "TC_RFTP_C0" }, // Refresh Timing Parameters |
| 35 | /* Channel 1 */ |
| 36 | { 0x4400, 4, "TC_DBP_C1" }, // Timing of DDR Bin Parameters |
| 37 | { 0x4404, 4, "TC_RAP_C1" }, // Timing of DDR Regular Access Parameters |
| 38 | { 0x4428, 4, "SC_IO_LATENCY_C1" }, // IO Latency Configuration |
| 39 | { 0x46A4, 4, "TC_SRFTP_C1" }, // Self-Refresh Timing Parameters |
| 40 | { 0x44B0, 4, "PM_PDWN_config_C1" }, // Power-down Configuration |
| 41 | { 0x4694, 4, "TC_RFP_C1" }, // Refresh Parameters |
| 42 | { 0x4698, 4, "TC_RFTP_C1" }, // Refresh Timing Parameters |
| 43 | /* Integrated Memory Peripheral Hub (IMPH) */ |
| 44 | { 0x740C, 4, "CRDTCTL3" }, // Credit Control 3 |
| 45 | /* Common Registers */ |
| 46 | { 0x5000, 4, "MAD_CHNL" }, // Address decoder Channel Configuration |
| 47 | { 0x5004, 4, "MAD_DIMM_ch0" }, // Address Decode Channel 0 |
| 48 | { 0x5008, 4, "MAD_DIMM_ch1" }, // Address Decode Channel 1 |
| 49 | { 0x5060, 4, "PM_SREF_config" }, // Self Refresh Configuration |
| 50 | /* MMIO Registers Broadcast Group */ |
| 51 | { 0x4CB0, 4, "PM_PDWN_config" }, // Power-down Configuration |
| 52 | { 0x4F84, 4, "PM_CMD_PWR" }, // Power Management Command Power |
| 53 | { 0x4F88, 4, "PM_BW_LIMIT_config" }, // BW Limit Configuration |
| 54 | { 0x4F8C, 4, "RESERVED" }, // Reserved, default value - 0xFF1D1519 |
| 55 | /* PCU MCHBAR Registers */ |
| 56 | { 0x5880, 4, "MEM_TRML_ESTIMATION_CONFIG" }, // Memory Thermal Estimation Configuration |
| 57 | { 0x5884, 4, "RESERVED" }, // Reserved |
| 58 | { 0x5888, 4, "MEM_TRML_THRESHOLDS_CONFIG" }, // Memory Thermal Thresholds Configuration |
| 59 | { 0x58A0, 4, "MEM_TRML_STATUS_REPORT" }, // Memory Thermal Status Report |
| 60 | { 0x58A4, 4, "MEM_TRML_TEMPERATURE_REPORT" }, // Memory Thermal Temperature Report |
| 61 | { 0x58A8, 4, "MEM_TRML_INTERRUPT" }, // Memory Thermal Interrupt |
| 62 | { 0x5948, 4, "GT_PERF_STATUS" }, // GT Performance Status |
| 63 | { 0x5998, 4, "RP_STATE_CAP" }, // RP State Capability |
| 64 | { 0x5D10, 8, "SSKPD" }, // Sticky Scratchpad Data |
| 65 | }; |
| 66 | |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 67 | /* |
| 68 | * (G)MCH MMIO Config Space |
| 69 | */ |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 70 | int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 71 | { |
| 72 | int i, size = (16 * 1024); |
| 73 | volatile uint8_t *mchbar; |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 74 | uint64_t mchbar_phys; |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 75 | const io_register_t *mch_registers = NULL; |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 76 | struct pci_dev *nb_device6; /* "overflow device" on i865 */ |
| 77 | uint16_t pcicmd6; |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 78 | |
| 79 | printf("\n============= MCHBAR ============\n\n"); |
| 80 | |
| 81 | switch (nb->device_id) { |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 82 | case PCI_DEVICE_ID_INTEL_82865: |
| 83 | /* |
| 84 | * On i865, the memory access enable/disable bit (MCHBAREN on |
| 85 | * i945/i965) is not in the MCHBAR (i945/i965) register but in |
| 86 | * the PCICMD6 register. BAR6 and PCICMD6 reside on device 6. |
| 87 | * |
| 88 | * The actual base address is in BAR6 on i865 where on |
| 89 | * i945/i965 the base address is in MCHBAR. |
| 90 | */ |
| 91 | nb_device6 = pci_get_dev(pacc, 0, 0, 0x06, 0); /* Device 6 */ |
| 92 | mchbar_phys = pci_read_long(nb_device6, 0x10); /* BAR6 */ |
| 93 | pcicmd6 = pci_read_long(nb_device6, 0x04); /* PCICMD6 */ |
| 94 | |
| 95 | /* Try to enable Memory Access Enable (MAE). */ |
| 96 | if (!(pcicmd6 & (1 << 1))) { |
| 97 | printf("Access to BAR6 is currently disabled, " |
| 98 | "attempting to enable.\n"); |
| 99 | pci_write_long(nb_device6, 0x04, pcicmd6 | (1 << 1)); |
| 100 | if (pci_read_long(nb_device6, 0x04) & (1 << 1)) |
| 101 | printf("Enabled successfully.\n"); |
| 102 | else |
| 103 | printf("Enable FAILED!\n"); |
| 104 | } |
| 105 | mchbar_phys &= 0xfffff000; /* Bits 31:12 from BAR6 */ |
| 106 | break; |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 107 | case PCI_DEVICE_ID_INTEL_82915: |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 108 | case PCI_DEVICE_ID_INTEL_82945GM: |
Björn Busse | 2d33dc4 | 2010-08-01 15:33:30 +0000 | [diff] [blame] | 109 | case PCI_DEVICE_ID_INTEL_82945GSE: |
Stefan Reinauer | 3d9a12f | 2008-11-02 11:11:40 +0000 | [diff] [blame] | 110 | case PCI_DEVICE_ID_INTEL_82945P: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 111 | case PCI_DEVICE_ID_INTEL_82975X: |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 112 | mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe; |
| 113 | break; |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 114 | case PCI_DEVICE_ID_INTEL_82965PM: |
| 115 | case PCI_DEVICE_ID_INTEL_82Q35: |
| 116 | case PCI_DEVICE_ID_INTEL_82G33: |
| 117 | case PCI_DEVICE_ID_INTEL_82Q33: |
| 118 | mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; |
| 119 | mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; |
| 120 | break; |
Stefan Tauner | 1a00cf0 | 2012-10-13 06:23:52 +0200 | [diff] [blame] | 121 | case PCI_DEVICE_ID_INTEL_82946: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 122 | case PCI_DEVICE_ID_INTEL_82Q965: |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 123 | case PCI_DEVICE_ID_INTEL_ATOM_DXXX: |
| 124 | case PCI_DEVICE_ID_INTEL_ATOM_NXXX: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 125 | mchbar_phys = pci_read_long(nb, 0x48); |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 126 | |
| 127 | /* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads. |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 128 | * If it isn't, try to set it. This may fail, because there is |
| 129 | * some bit that locks that bit, and isn't in the public |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 130 | * datasheets. |
| 131 | */ |
| 132 | |
| 133 | if(!(mchbar_phys & 1)) |
| 134 | { |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 135 | printf("Access to the MCHBAR is currently disabled, " |
| 136 | "attempting to enable.\n"); |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 137 | mchbar_phys |= 0x1; |
| 138 | pci_write_long(nb, 0x48, mchbar_phys); |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 139 | if(pci_read_long(nb, 0x48) & 1) |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 140 | printf("Enabled successfully.\n"); |
| 141 | else |
| 142 | printf("Enable FAILED!\n"); |
| 143 | } |
| 144 | mchbar_phys &= 0xfffffffe; |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 145 | mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; |
| 146 | break; |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 147 | case PCI_DEVICE_ID_INTEL_82443LX: |
| 148 | case PCI_DEVICE_ID_INTEL_82443BX: |
Stefan Reinauer | b2aedb1 | 2009-08-29 15:45:43 +0000 | [diff] [blame] | 149 | case PCI_DEVICE_ID_INTEL_82810: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 150 | case PCI_DEVICE_ID_INTEL_82810E_DC: |
| 151 | case PCI_DEVICE_ID_INTEL_82810_DC: |
Stefan Reinauer | 0484481 | 2010-02-22 11:26:06 +0000 | [diff] [blame] | 152 | case PCI_DEVICE_ID_INTEL_82830M: |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 153 | printf("This northbridge does not have MCHBAR.\n"); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 154 | return 1; |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 155 | case PCI_DEVICE_ID_INTEL_82X4X: |
| 156 | case PCI_DEVICE_ID_INTEL_82X38: |
Ruud Schramp | bb41f50 | 2011-04-04 07:53:19 +0200 | [diff] [blame] | 157 | case PCI_DEVICE_ID_INTEL_32X0: |
Anton Kochkov | da0b456 | 2010-05-30 12:33:12 +0000 | [diff] [blame] | 158 | mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; |
| 159 | mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 160 | break; |
| 161 | case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: |
| 162 | mchbar_phys = pci_read_long(nb, 0x48); |
| 163 | mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; |
| 164 | mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */ |
| 165 | mch_registers = NULL; /* No public documentation */ |
| 166 | break; |
| 167 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN: |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 168 | mch_registers = sandybridge_mch_registers; |
| 169 | size = ARRAY_SIZE(sandybridge_mch_registers); |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 170 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN: /* pretty printing not implemented yet */ |
| 171 | mchbar_phys = pci_read_long(nb, 0x48); |
| 172 | mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; |
| 173 | mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */ |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 174 | break; |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 175 | default: |
| 176 | printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n"); |
| 177 | return 1; |
| 178 | } |
| 179 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 180 | mchbar = map_physical(mchbar_phys, size); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 181 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 182 | if (mchbar == NULL) { |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 183 | if (nb->device_id == PCI_DEVICE_ID_INTEL_82865) |
| 184 | perror("Error mapping BAR6"); |
| 185 | else |
| 186 | perror("Error mapping MCHBAR"); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 187 | exit(1); |
| 188 | } |
| 189 | |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 190 | if (nb->device_id == PCI_DEVICE_ID_INTEL_82865) |
Stefan Reinauer | a7b296d | 2011-11-14 12:40:34 -0800 | [diff] [blame] | 191 | printf("BAR6 = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys); |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 192 | else |
Stefan Reinauer | a7b296d | 2011-11-14 12:40:34 -0800 | [diff] [blame] | 193 | printf("MCHBAR = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 194 | |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 195 | if (mch_registers != NULL) { |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 196 | printf("%d registers:\n", size); |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 197 | for (i = 0; i < size; i++) { |
| 198 | switch (mch_registers[i].size) { |
| 199 | case 8: |
Stefan Tauner | 0dc775e | 2013-04-05 01:15:04 +0200 | [diff] [blame] | 200 | printf("mchbase+0x%04x: 0x%016"PRIx64" (%s)\n", |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 201 | mch_registers[i].addr, |
| 202 | *(uint64_t *)(mchbar+mch_registers[i].addr), |
| 203 | mch_registers[i].name); |
| 204 | break; |
| 205 | case 4: |
Stefan Tauner | 0dc775e | 2013-04-05 01:15:04 +0200 | [diff] [blame] | 206 | printf("mchbase+0x%04x: 0x%08"PRIx32" (%s)\n", |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 207 | mch_registers[i].addr, |
| 208 | *(uint32_t *)(mchbar+mch_registers[i].addr), |
| 209 | mch_registers[i].name); |
| 210 | break; |
| 211 | case 2: |
Stefan Tauner | 0dc775e | 2013-04-05 01:15:04 +0200 | [diff] [blame] | 212 | printf("mchbase+0x%04x: 0x%04"PRIx16" (%s)\n", |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 213 | mch_registers[i].addr, |
| 214 | *(uint16_t *)(mchbar+mch_registers[i].addr), |
| 215 | mch_registers[i].name); |
| 216 | break; |
| 217 | case 1: |
Stefan Tauner | 0dc775e | 2013-04-05 01:15:04 +0200 | [diff] [blame] | 218 | printf("mchbase+0x%04x: 0x%02"PRIx8" (%s)\n", |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 219 | mch_registers[i].addr, |
| 220 | *(uint8_t *)(mchbar+mch_registers[i].addr), |
| 221 | mch_registers[i].name); |
| 222 | break; |
| 223 | } |
| 224 | } |
| 225 | } else { |
| 226 | for (i = 0; i < size; i += 4) { |
| 227 | if (*(uint32_t *)(mchbar + i)) |
Stefan Tauner | 0dc775e | 2013-04-05 01:15:04 +0200 | [diff] [blame] | 228 | printf("0x%04x: 0x%08"PRIx32"\n", i, *(uint32_t *)(mchbar+i)); |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 229 | } |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 230 | } |
| 231 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 232 | unmap_physical((void *)mchbar, size); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 233 | return 0; |
| 234 | } |
| 235 | |
| 236 | |