| QingPei Wang | e169f82 | 2011-09-13 13:35:43 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de> |
| 5 | * Copyright (C) 2011 QingPei Wang <wangqingpei@gmail.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | #include <arch/romcc_io.h> |
| 23 | #include "it8721f.h" |
| 24 | |
| 25 | /* The base address is 0x2e or 0x4e, depending on config bytes. */ |
| 26 | #define SIO_BASE 0x2e |
| 27 | #define SIO_INDEX SIO_BASE |
| 28 | #define SIO_DATA (SIO_BASE + 1) |
| 29 | |
| 30 | /* Global configuration registers. */ |
| 31 | #define IT8721F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ |
| 32 | #define IT8721F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ |
| 33 | #define IT8721F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ |
| 34 | #define IT8721F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ |
| 35 | |
| 36 | static void it8721f_sio_write(u8 ldn, u8 index, u8 value) |
| 37 | { |
| 38 | outb(IT8721F_CONFIG_REG_LDN, SIO_BASE); |
| 39 | outb(ldn, SIO_DATA); |
| 40 | outb(index, SIO_BASE); |
| 41 | outb(value, SIO_DATA); |
| 42 | } |
| 43 | |
| 44 | static void it8721f_enter_conf(void) |
| 45 | { |
| 46 | u16 port = 0x2e; /* TODO: Don't hardcode! */ |
| 47 | |
| 48 | outb(0x87, port); |
| 49 | outb(0x01, port); |
| 50 | outb(0x55, port); |
| 51 | outb((port == 0x4e) ? 0xaa : 0x55, port); |
| 52 | } |
| 53 | |
| 54 | static void it8721f_exit_conf(void) |
| 55 | { |
| 56 | it8721f_sio_write(0x00, IT8721F_CONFIG_REG_CC, 0x02); |
| 57 | } |
| 58 | |
| 59 | /* Select 24MHz CLKIN (48MHz default). */ |
| 60 | void it8721f_24mhz_clkin(void) |
| 61 | { |
| 62 | it8721f_enter_conf(); |
| 63 | it8721f_sio_write(0x00, IT8721F_CONFIG_REG_CLOCKSEL, 0x1); |
| 64 | it8721f_exit_conf(); |
| 65 | } |
| 66 | |
| 67 | |
| 68 | /* Enable the serial port(s). */ |
| 69 | void it8721f_enable_serial(device_t dev, u16 iobase) |
| 70 | { |
| 71 | /* (1) Enter the configuration state (MB PnP mode). */ |
| 72 | it8721f_enter_conf(); |
| 73 | |
| 74 | /* (2) Modify the data of configuration registers. */ |
| 75 | |
| 76 | /* |
| 77 | * Select the chip to configure (if there's more than one). |
| 78 | * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. |
| 79 | * If this register is not written, both chips are configured. |
| 80 | */ |
| 81 | |
| 82 | /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */ |
| 83 | |
| 84 | /* Enable serial port(s). */ |
| 85 | it8721f_sio_write(IT8721F_SP1, 0x30, 0x1); /* Serial port 1 */ |
| 86 | it8721f_sio_write(IT8721F_SP2, 0x30, 0x1); /* Serial port 2 */ |
| 87 | |
| 88 | /* Clear software suspend mode (clear bit 0). TODO: Needed? */ |
| 89 | /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */ |
| 90 | |
| 91 | /* (3) Exit the configuration state (MB PnP mode). */ |
| 92 | it8721f_exit_conf(); |
| 93 | } |