Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007 AMD |
| 5 | * Written by Yinghai Lu <yinghailu@amd.com> for AMD. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 22 | #define FAM10_SCAN_PCI_BUS 0 |
| 23 | #define FAM10_ALLOCATE_IO_RANGE 1 |
| 24 | |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 25 | #include <stdint.h> |
| 26 | #include <string.h> |
| 27 | #include <device/pci_def.h> |
| 28 | #include <device/pci_ids.h> |
| 29 | #include <arch/io.h> |
| 30 | #include <device/pnp_def.h> |
| 31 | #include <arch/romcc_io.h> |
| 32 | #include <cpu/x86/lapic.h> |
Patrick Georgi | 12584e2 | 2010-05-08 09:14:51 +0000 | [diff] [blame] | 33 | #include <console/console.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 34 | #include <lib.h> |
Uwe Hermann | 26535d6 | 2010-11-20 20:36:40 +0000 | [diff] [blame] | 35 | #include <spd.h> |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 36 | #include <cpu/amd/model_10xxx_rev.h> |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 37 | #include "southbridge/nvidia/mcp55/early_smbus.c" |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 38 | #include "northbridge/amd/amdfam10/raminit.h" |
| 39 | #include "northbridge/amd/amdfam10/amdfam10.h" |
Stefan Reinauer | bcb8c97 | 2010-04-25 18:06:32 +0000 | [diff] [blame] | 40 | #include "cpu/amd/model_fxx/apic_timer.c" |
| 41 | #include "lib/delay.c" |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 42 | #include "cpu/x86/lapic/boot_cpu.c" |
| 43 | #include "northbridge/amd/amdfam10/reset_test.c" |
stepan | 8301d83 | 2010-12-08 07:07:33 +0000 | [diff] [blame] | 44 | #include "superio/winbond/w83627ehg/early_serial.c" |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 45 | #include "cpu/x86/bist.h" |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 46 | #include "northbridge/amd/amdfam10/debug.c" |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 47 | #include "cpu/x86/mtrr/earlymtrr.c" |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 48 | #include "northbridge/amd/amdfam10/setup_resource_map.c" |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 49 | #include "southbridge/nvidia/mcp55/early_ctrl.c" |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 50 | |
| 51 | #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 52 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 53 | static void activate_spd_rom(const struct mem_controller *ctrl) { } |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 54 | |
| 55 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 56 | { |
| 57 | return smbus_read_byte(device, address); |
| 58 | } |
| 59 | |
| 60 | #include "northbridge/amd/amdfam10/amdfam10.h" |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 61 | #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" |
stepan | 8301d83 | 2010-12-08 07:07:33 +0000 | [diff] [blame] | 62 | #include "northbridge/amd/amdfam10/pci.c" |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 63 | #include "resourcemap.c" |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 64 | #include "cpu/amd/quadcore/quadcore.c" |
| 65 | |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 66 | #define MCP55_MB_SETUP \ |
| 67 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ |
| 68 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ |
| 69 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \ |
| 70 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \ |
| 71 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ |
| 72 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ |
| 73 | |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 74 | #include "southbridge/nvidia/mcp55/early_setup_ss.h" |
| 75 | #include "southbridge/nvidia/mcp55/early_setup_car.c" |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 76 | #include "cpu/amd/car/post_cache_as_ram.c" |
Myles Watson | 075fbe8 | 2010-04-15 05:19:29 +0000 | [diff] [blame] | 77 | #include "cpu/amd/microcode/microcode.c" |
Xavi Drudis Ferran | 4c28a6f | 2011-02-26 23:29:44 +0000 | [diff] [blame] | 78 | |
| 79 | #if CONFIG_UPDATE_CPU_MICROCODE |
Myles Watson | 075fbe8 | 2010-04-15 05:19:29 +0000 | [diff] [blame] | 80 | #include "cpu/amd/model_10xxx/update_microcode.c" |
Xavi Drudis Ferran | 4c28a6f | 2011-02-26 23:29:44 +0000 | [diff] [blame] | 81 | #endif |
| 82 | |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 83 | #include "cpu/amd/model_10xxx/init_cpus.c" |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 84 | #include "northbridge/amd/amdfam10/early_ht.c" |
| 85 | |
| 86 | static void sio_setup(void) |
| 87 | { |
Stefan Reinauer | 8b547b1 | 2010-03-30 09:56:35 +0000 | [diff] [blame] | 88 | u32 dword; |
| 89 | u8 byte; |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 90 | |
Uwe Hermann | 5fa76e2 | 2010-03-01 20:16:38 +0000 | [diff] [blame] | 91 | byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); |
| 92 | byte |= 0x20; |
| 93 | pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 94 | |
Uwe Hermann | 5fa76e2 | 2010-03-01 20:16:38 +0000 | [diff] [blame] | 95 | dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); |
| 96 | dword |= (1<<0); |
| 97 | pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 98 | } |
| 99 | |
Uwe Hermann | 26535d6 | 2010-11-20 20:36:40 +0000 | [diff] [blame] | 100 | static const u8 spd_addr[] = { |
| 101 | //first node |
| 102 | RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 103 | #if CONFIG_MAX_PHYSICAL_CPUS > 1 |
| 104 | //second node |
| 105 | RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, |
| 106 | #endif |
| 107 | }; |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 108 | |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 109 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 110 | { |
| 111 | struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 112 | u32 bsp_apicid = 0, val, wants_reset; |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 113 | u8 reg; |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 114 | msr_t msr; |
| 115 | |
Patrick Georgi | 2bd9100 | 2010-03-18 16:46:50 +0000 | [diff] [blame] | 116 | if (!cpu_init_detectedx && boot_cpu()) { |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 117 | /* Nothing special needs to be done to find bus 0 */ |
| 118 | /* Allow the HT devices to be found */ |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 119 | set_bsp_node_CHtExtNodeCfgEn(); |
| 120 | enumerate_ht_chain(); |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 121 | sio_setup(); |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 122 | } |
| 123 | |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 124 | post_code(0x30); |
| 125 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 126 | if (bist == 0) |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 127 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 128 | |
| 129 | post_code(0x32); |
| 130 | |
| 131 | pnp_enter_ext_func_mode(SERIAL_DEV); |
| 132 | /* We have 24MHz input. */ |
| 133 | reg = pnp_read_config(SERIAL_DEV, 0x24); |
| 134 | pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf)); |
| 135 | pnp_exit_ext_func_mode(SERIAL_DEV); |
| 136 | |
| 137 | w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 138 | console_init(); |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 139 | |
| 140 | /* Halt if there was a built in self test failure */ |
| 141 | report_bist_failure(bist); |
| 142 | |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 143 | val = cpuid_eax(1); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 144 | printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 145 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 146 | printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 147 | printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 148 | |
| 149 | /* Setup sysinfo defaults */ |
| 150 | set_sysinfo_in_ram(0); |
| 151 | |
Xavi Drudis Ferran | 4c28a6f | 2011-02-26 23:29:44 +0000 | [diff] [blame] | 152 | #if CONFIG_UPDATE_CPU_MICROCODE |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 153 | update_microcode(val); |
Xavi Drudis Ferran | 4c28a6f | 2011-02-26 23:29:44 +0000 | [diff] [blame] | 154 | #endif |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 155 | post_code(0x33); |
| 156 | |
| 157 | cpuSetAMDMSR(); |
| 158 | post_code(0x34); |
| 159 | |
| 160 | amd_ht_init(sysinfo); |
| 161 | post_code(0x35); |
| 162 | |
| 163 | /* Setup nodes PCI space and start core 0 AP init. */ |
| 164 | finalize_node_setup(sysinfo); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 165 | printk(BIOS_DEBUG, "finalize_node_setup done\n"); |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 166 | |
| 167 | /* Setup any mainboard PCI settings etc. */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 168 | printk(BIOS_DEBUG, "setup_mb_resource_map begin\n"); |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 169 | setup_mb_resource_map(); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 170 | printk(BIOS_DEBUG, "setup_mb_resource_map end\n"); |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 171 | post_code(0x36); |
| 172 | |
| 173 | /* wait for all the APs core0 started by finalize_node_setup. */ |
| 174 | /* FIXME: A bunch of cores are going to start output to serial at once. |
| 175 | * It would be nice to fixup prink spinlocks for ROM XIP mode. |
| 176 | * I think it could be done by putting the spinlock flag in the cache |
| 177 | * of the BSP located right after sysinfo. |
| 178 | */ |
| 179 | wait_all_core0_started(); |
| 180 | |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame^] | 181 | #if CONFIG_LOGICAL_CPUS |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 182 | /* Core0 on each node is configured. Now setup any additional cores. */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 183 | printk(BIOS_DEBUG, "start_other_cores()\n"); |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 184 | start_other_cores(); |
| 185 | post_code(0x37); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 186 | printk(BIOS_DEBUG, "wait_all_other_cores_started()\n"); |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 187 | wait_all_other_cores_started(bsp_apicid); |
| 188 | #endif |
| 189 | |
| 190 | post_code(0x38); |
| 191 | |
Patrick Georgi | 76e8152 | 2010-11-16 21:25:29 +0000 | [diff] [blame] | 192 | #if CONFIG_SET_FIDVID |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 193 | msr = rdmsr(0xc0010071); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 194 | printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 195 | |
| 196 | /* FIXME: The sb fid change may survive the warm reset and only |
| 197 | * need to be done once.*/ |
| 198 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 199 | |
| 200 | post_code(0x39); |
| 201 | |
| 202 | if (!warm_reset_detect(0)) { // BSP is node 0 |
| 203 | init_fidvid_bsp(bsp_apicid, sysinfo->nodes); |
| 204 | } else { |
| 205 | init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 |
| 206 | } |
| 207 | |
| 208 | post_code(0x3A); |
| 209 | |
| 210 | /* show final fid and vid */ |
| 211 | msr=rdmsr(0xc0010071); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 212 | printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 213 | #endif |
Stefan Reinauer | bcb8c97 | 2010-04-25 18:06:32 +0000 | [diff] [blame] | 214 | init_timer(); /* Need to use TMICT to synconize FID/VID. */ |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 215 | |
| 216 | wants_reset = mcp55_early_setup_x(); |
| 217 | |
| 218 | /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ |
| 219 | if (!warm_reset_detect(0)) { |
| 220 | print_info("...WARM RESET...\n\n\n"); |
| 221 | soft_reset(); |
| 222 | die("After soft_reset_x - shouldn't see this message!!!\n"); |
| 223 | } |
| 224 | |
| 225 | if (wants_reset) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 226 | printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n"); |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 227 | |
| 228 | post_code(0x3B); |
| 229 | |
| 230 | /* It's the time to set ctrl in sysinfo now; */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 231 | printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 232 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 233 | post_code(0x3D); |
| 234 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 235 | printk(BIOS_DEBUG, "enable_smbus()\n"); |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 236 | enable_smbus(); |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 237 | |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 238 | post_code(0x40); |
| 239 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 240 | printk(BIOS_DEBUG, "raminit_amdmct()\n"); |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 241 | raminit_amdmct(sysinfo); |
| 242 | post_code(0x41); |
| 243 | |
Timothy Pearson | d3b2bbe | 2010-03-01 10:56:51 +0000 | [diff] [blame] | 244 | post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. |
| 245 | post_code(0x43); // Should never see this post code. |
| 246 | } |
Scott Duplichan | 314dd0b | 2011-03-08 23:01:46 +0000 | [diff] [blame] | 247 | |
| 248 | /** |
| 249 | * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) |
| 250 | * Description: |
| 251 | * This routine is called every time a non-coherent chain is processed. |
| 252 | * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a |
| 253 | * swap list. The first part of the list controls the BUID assignment and the |
| 254 | * second part of the list provides the device to device linking. Device orientation |
| 255 | * can be detected automatically, or explicitly. See documentation for more details. |
| 256 | * |
| 257 | * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially |
| 258 | * based on each device's unit count. |
| 259 | * |
| 260 | * Parameters: |
| 261 | * @param[in] u8 node = The node on which this chain is located |
| 262 | * @param[in] u8 link = The link on the host for this chain |
| 263 | * @param[out] u8** list = supply a pointer to a list |
| 264 | * @param[out] BOOL result = true to use a manual list |
| 265 | * false to initialize the link automatically |
| 266 | */ |
| 267 | BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) |
| 268 | { |
| 269 | static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; |
| 270 | /* If the BUID was adjusted in early_ht we need to do the manual override */ |
| 271 | if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { |
| 272 | printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); |
| 273 | if ((node == 0) && (link == 0)) { /* BSP SB link */ |
| 274 | *List = swaplist; |
| 275 | return 1; |
| 276 | } |
| 277 | } |
| 278 | |
| 279 | return 0; |
| 280 | } |