blob: 06a6bca5530f0f272dfd99a19f4f9a43b36a16b4 [file] [log] [blame]
Duncan Laurie26cf00a2018-10-14 02:39:46 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2018 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <stddef.h>
17#include <stdint.h>
18#include <arch/io.h>
19
20#include "mec.h"
21
22enum mec_access_mode {
23 /* 8-bit access */
24 ACCESS_TYPE_BYTE = 0x0,
25 /* 16-bit access */
26 ACCESS_TYPE_WORD = 0x1,
27 /* 32-bit access */
28 ACCESS_TYPE_LONG = 0x2,
29 /*
30 * 32-bit access, read or write of MEC_EMI_EC_DATA_B3 causes the
31 * EC data register to be incremented.
32 */
33 ACCESS_TYPE_LONG_AUTO_INCREMENT = 0x3,
34};
35
36/* EMI registers are relative to base */
37#define MEC_EMI_HOST_TO_EC(base) ((base) + 0)
38#define MEC_EMI_EC_TO_HOST(base) ((base) + 1)
39#define MEC_EMI_EC_ADDRESS_B0(base) ((base) + 2)
40#define MEC_EMI_EC_ADDRESS_B1(base) ((base) + 3)
41#define MEC_EMI_EC_DATA_B0(base) ((base) + 4)
42#define MEC_EMI_EC_DATA_B1(base) ((base) + 5)
43#define MEC_EMI_EC_DATA_B2(base) ((base) + 6)
44#define MEC_EMI_EC_DATA_B3(base) ((base) + 7)
45
46/*
47 * cros_ec_lpc_mec_emi_write_address
48 *
49 * Initialize EMI read / write at a given address.
50 *
51 * @base: Starting read / write address
52 * @offset: Offset applied to base address
53 * @access_mode: Type of access, typically 32-bit auto-increment
54 */
55static void mec_emi_write_address(uint16_t base, uint16_t offset,
56 enum mec_access_mode access_mode)
57{
58 outb((offset & 0xfc) | access_mode, MEC_EMI_EC_ADDRESS_B0(base));
59 outb((offset >> 8) & 0x7f, MEC_EMI_EC_ADDRESS_B1(base));
60}
61
62uint8_t mec_io_bytes(enum mec_io_type type, uint16_t base,
63 uint16_t offset, void *buffer, size_t size)
64{
65 enum mec_access_mode access_mode, new_access_mode;
66 uint8_t *buf = buffer;
67 uint8_t checksum = 0;
68 int io_addr;
69 int i = 0;
70
71 if (size == 0 || base == 0)
72 return 0;
73
74 /*
75 * Long access cannot be used on misaligned data since reading B0 loads
76 * the data register and writing B3 flushes it.
77 */
78 if ((offset & 0x3) || (size < 4))
79 access_mode = ACCESS_TYPE_BYTE;
80 else
81 access_mode = ACCESS_TYPE_LONG_AUTO_INCREMENT;
82
83 /* Initialize I/O at desired address */
84 mec_emi_write_address(base, offset, access_mode);
85
86 /* Skip bytes in case of misaligned offset */
87 io_addr = MEC_EMI_EC_DATA_B0(base) + (offset & 0x3);
88 while (i < size) {
89 while (io_addr <= MEC_EMI_EC_DATA_B3(base)) {
90 if (type == MEC_IO_WRITE)
91 outb(buf[i], io_addr++);
92 else
93 buf[i] = inb(io_addr++);
94
95 checksum += buf[i++];
96 offset++;
97
98 /* Extra bounds check in case of misaligned size */
99 if (i == size)
100 return checksum;
101 }
102
103 /*
104 * Use long auto-increment access except for misaligned write,
105 * since writing B3 triggers the flush.
106 */
107 if ((size - i) < 4 && type == MEC_IO_WRITE)
108 new_access_mode = ACCESS_TYPE_BYTE;
109 else
110 new_access_mode = ACCESS_TYPE_LONG_AUTO_INCREMENT;
111 if (new_access_mode != access_mode ||
112 access_mode != ACCESS_TYPE_LONG_AUTO_INCREMENT) {
113 access_mode = new_access_mode;
114 mec_emi_write_address(base, offset, access_mode);
115 }
116
117 /* Access [B0, B3] on each loop pass */
118 io_addr = MEC_EMI_EC_DATA_B0(base);
119 }
120
121 return checksum;
122}