blob: 62a7a9236865c2c080c039217ebd0f370c33ddb8 [file] [log] [blame]
Patrick Georgi0588d192009-08-12 15:00:51 +00001##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00002## This file is part of the coreboot project.
Patrick Georgi0588d192009-08-12 15:00:51 +00003##
Alexandru Gagniuc70c660f2012-08-23 02:32:58 -05004## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
Stefan Reinauer16f515a2010-01-20 18:44:30 +00005## Copyright (C) 2009-2010 coresystems GmbH
Patrick Georgi0588d192009-08-12 15:00:51 +00006##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00007## This program is free software; you can redistribute it and/or modify
8## it under the terms of the GNU General Public License as published by
9## the Free Software Foundation; version 2 of the License.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
Patrick Georgi0588d192009-08-12 15:00:51 +000016
Uwe Hermannad8c95f2012-04-12 22:00:03 +020017mainmenu "coreboot configuration"
Patrick Georgi0588d192009-08-12 15:00:51 +000018
Uwe Hermannc04be932009-10-05 13:55:28 +000019menu "General setup"
20
Lee Leahybb70c402017-04-03 07:38:20 -070021config COREBOOT_BUILD
22 bool
23 default y
24
Uwe Hermannc04be932009-10-05 13:55:28 +000025config LOCALVERSION
Uwe Hermann168b11b2009-10-07 16:15:40 +000026 string "Local version string"
Uwe Hermannc04be932009-10-05 13:55:28 +000027 help
28 Append an extra string to the end of the coreboot version.
29
Uwe Hermann168b11b2009-10-07 16:15:40 +000030 This can be useful if, for instance, you want to append the
31 respective board's hostname or some other identifying string to
32 the coreboot version number, so that you can easily distinguish
33 boot logs of different boards from each other.
34
Patrick Georgi4b8a2412010-02-09 19:35:16 +000035config CBFS_PREFIX
36 string "CBFS prefix to use"
37 default "fallback"
38 help
39 Select the prefix to all files put into the image. It's "fallback"
40 by default, "normal" is a common alternative.
41
Patrick Georgi23d89cc2010-03-16 01:17:19 +000042choice
Uwe Hermannad8c95f2012-04-12 22:00:03 +020043 prompt "Compiler to use"
Patrick Georgi23d89cc2010-03-16 01:17:19 +000044 default COMPILER_GCC
45 help
46 This option allows you to select the compiler used for building
47 coreboot.
Martin Rotha5a628e82016-01-19 12:01:09 -070048 You must build the coreboot crosscompiler for the board that you
49 have selected.
50
51 To build all the GCC crosscompilers (takes a LONG time), run:
52 make crossgcc
53
54 For help on individual architectures, run the command:
55 make help_toolchain
Patrick Georgi23d89cc2010-03-16 01:17:19 +000056
57config COMPILER_GCC
58 bool "GCC"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020059 help
60 Use the GNU Compiler Collection (GCC) to build coreboot.
61
62 For details see http://gcc.gnu.org.
63
Patrick Georgi23d89cc2010-03-16 01:17:19 +000064config COMPILER_LLVM_CLANG
Martin Rotha5a628e82016-01-19 12:01:09 -070065 bool "LLVM/clang (TESTING ONLY - Not currently working)"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020066 help
Martin Rotha5a628e82016-01-19 12:01:09 -070067 Use LLVM/clang to build coreboot. To use this, you must build the
68 coreboot version of the clang compiler. Run the command
69 make clang
70 Note that this option is not currently working correctly and should
71 really only be selected if you're trying to work on getting clang
72 operational.
Uwe Hermannad8c95f2012-04-12 22:00:03 +020073
74 For details see http://clang.llvm.org.
75
Patrick Georgi23d89cc2010-03-16 01:17:19 +000076endchoice
77
Patrick Georgi9b0de712013-12-29 18:45:23 +010078config ANY_TOOLCHAIN
79 bool "Allow building with any toolchain"
80 default n
Patrick Georgi9b0de712013-12-29 18:45:23 +010081 help
82 Many toolchains break when building coreboot since it uses quite
83 unusual linker features. Unless developers explicitely request it,
84 we'll have to assume that they use their distro compiler by mistake.
85 Make sure that using patched compilers is a conscious decision.
86
Patrick Georgi516a2a72010-03-25 21:45:25 +000087config CCACHE
Uwe Hermannad8c95f2012-04-12 22:00:03 +020088 bool "Use ccache to speed up (re)compilation"
Patrick Georgi516a2a72010-03-25 21:45:25 +000089 default n
90 help
91 Enables the use of ccache for faster builds.
Uwe Hermannad8c95f2012-04-12 22:00:03 +020092
93 Requires the ccache utility in your system $PATH.
94
95 For details see https://ccache.samba.org.
Patrick Georgi516a2a72010-03-25 21:45:25 +000096
Sol Boucher69b88bf2015-02-26 11:47:19 -080097config FMD_GENPARSER
98 bool "Generate flashmap descriptor parser using flex and bison"
99 default n
Sol Boucher69b88bf2015-02-26 11:47:19 -0800100 help
101 Enable this option if you are working on the flashmap descriptor
102 parser and made changes to fmd_scanner.l or fmd_parser.y.
103
104 Otherwise, say N to use the provided pregenerated scanner/parser.
105
Martin Rothf411b702017-04-09 19:12:42 -0600106config UTIL_GENPARSER
Denis 'GNUtoo' Carikli780e9312018-01-10 14:35:55 +0100107 bool "Generate SCONFIG & BINCFG parser using flex and bison"
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000108 default n
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000109 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200110 Enable this option if you are working on the sconfig device tree
Denis 'GNUtoo' Carikli780e9312018-01-10 14:35:55 +0100111 parser or bincfg and made changes to the .l or .y files.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200112
Sol Boucher69b88bf2015-02-26 11:47:19 -0800113 Otherwise, say N to use the provided pregenerated scanner/parser.
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000114
Joe Korty6d772522010-05-19 18:41:15 +0000115config USE_OPTION_TABLE
116 bool "Use CMOS for configuration values"
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000117 depends on HAVE_OPTION_TABLE
Joe Korty6d772522010-05-19 18:41:15 +0000118 help
119 Enable this option if coreboot shall read options from the "CMOS"
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200120 NVRAM instead of using hard-coded values.
Joe Korty6d772522010-05-19 18:41:15 +0000121
Timothy Pearsonf20c6e82015-02-14 16:15:31 -0600122config STATIC_OPTION_TABLE
123 bool "Load default configuration values into CMOS on each boot"
Timothy Pearsonf20c6e82015-02-14 16:15:31 -0600124 depends on USE_OPTION_TABLE
125 help
126 Enable this option to reset "CMOS" NVRAM values to default on
127 every boot. Use this if you want the NVRAM configuration to
128 never be modified from its default values.
129
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000130config COMPRESS_RAMSTAGE
131 bool "Compress ramstage with LZMA"
Martin Roth75e5cb72016-12-15 15:05:37 -0700132 # Default value set at the end of the file
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000133 help
134 Compress ramstage to save memory in the flash image. Note
135 that decompression might slow down booting if the boot flash
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200136 is connected through a slow link (i.e. SPI).
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000137
Julius Werner09f29212015-09-29 13:51:35 -0700138config COMPRESS_PRERAM_STAGES
139 bool "Compress romstage and verstage with LZ4"
Martin Rothf2e04612016-03-09 15:50:23 -0700140 depends on !ARCH_X86
Martin Roth75e5cb72016-12-15 15:05:37 -0700141 # Default value set at the end of the file
Julius Werner09f29212015-09-29 13:51:35 -0700142 help
143 Compress romstage and (if it exists) verstage with LZ4 to save flash
144 space and speed up boot, since the time for reading the image from SPI
145 (and in the vboot case verifying it) is usually much greater than the
146 time spent decompressing. Doesn't work for XIP stages (assume all
147 ARCH_X86 for now) for obvious reasons.
148
Julius Werner99f46832018-05-16 14:14:04 -0700149config COMPRESS_BOOTBLOCK
150 bool
151 help
152 This option can be used to compress the bootblock with LZ4 and attach
153 a small self-decompression stub to its front. This can drastically
154 reduce boot time on platforms where the bootblock is loaded over a
155 very slow connection and bootblock size trumps all other factors for
Jonathan Neuschäfer2930a722018-09-29 17:42:52 +0200156 speed. Since using this option usually requires changes to the
Julius Werner99f46832018-05-16 14:14:04 -0700157 SoC memlayout and possibly extra support code, it should not be
158 user-selectable. (There's no real point in offering this to the user
159 anyway... if it works and saves boot time, you would always want it.)
160
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200161config INCLUDE_CONFIG_FILE
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200162 bool "Include the coreboot .config file into the ROM image"
Martin Roth75e5cb72016-12-15 15:05:37 -0700163 # Default value set at the end of the file
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200164 help
165 Include the .config file that was used to compile coreboot
166 in the (CBFS) ROM image. This is useful if you want to know which
167 options were used to build a specific coreboot.rom image.
168
Daniele Forsi53847a22014-07-22 18:00:56 +0200169 Saying Y here will increase the image size by 2-3KB.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200170
171 You can use the following command to easily list the options:
172
173 grep -a CONFIG_ coreboot.rom
174
175 Alternatively, you can also use cbfstool to print the image
176 contents (including the raw 'config' item we're looking for).
177
178 Example:
179
180 $ cbfstool coreboot.rom print
181 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
182 offset 0x0
183 Alignment: 64 bytes
Steve Goodrichf0269122012-05-18 11:18:47 -0600184
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200185 Name Offset Type Size
186 cmos_layout.bin 0x0 cmos layout 1159
187 fallback/romstage 0x4c0 stage 339756
Daniele Forsi53847a22014-07-22 18:00:56 +0200188 fallback/ramstage 0x53440 stage 186664
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200189 fallback/payload 0x80dc0 payload 51526
190 config 0x8d740 raw 3324
191 (empty) 0x8e480 null 3610440
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200192
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700193config COLLECT_TIMESTAMPS
194 bool "Create a table of timestamps collected during boot"
Paul Menzel4e4a7632015-10-11 11:57:44 +0200195 default y if ARCH_X86
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700196 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200197 Make coreboot create a table of timer-ID/timer-value pairs to
198 allow measuring time spent at different phases of the boot process.
199
Martin Rothb22bbe22018-03-07 15:32:16 -0700200config TIMESTAMPS_ON_CONSOLE
201 bool "Print the timestamp values on the console"
202 default n
203 depends on COLLECT_TIMESTAMPS
204 help
205 Print the timestamps to the debug console if enabled at level spew.
206
Patrick Georgi7e9b9d82012-04-30 21:06:10 +0200207config USE_BLOBS
208 bool "Allow use of binary-only repository"
Patrick Georgi7e9b9d82012-04-30 21:06:10 +0200209 help
210 This draws in the blobs repository, which contains binary files that
211 might be required for some chipsets or boards.
212 This flag ensures that a "Free" option remains available for users.
213
Stefan Reinauerd37ab452012-12-18 16:23:28 -0800214config COVERAGE
215 bool "Code coverage support"
216 depends on COMPILER_GCC
Stefan Reinauerd37ab452012-12-18 16:23:28 -0800217 help
218 Add code coverage support for coreboot. This will store code
219 coverage information in CBMEM for extraction from user space.
220 If unsure, say N.
221
Ryan Salsamendiab37e9a2017-06-11 21:07:31 -0700222config UBSAN
223 bool "Undefined behavior sanitizer support"
224 default n
225 help
226 Instrument the code with checks for undefined behavior. If unsure,
227 say N because it adds a small performance penalty and may abort
228 on code that happens to work in spite of the UB.
229
Kyösti Mälkki7904e722018-06-03 14:55:10 +0300230config NO_RELOCATABLE_RAMSTAGE
231 bool
232 default n if ARCH_X86
233 default y
234
Stefan Reinauer58470e32014-10-17 13:08:36 +0200235config RELOCATABLE_RAMSTAGE
Kyösti Mälkki730df3c2016-06-18 07:39:31 +0300236 bool
Vladimir Serbinenko633352c2015-05-30 22:21:37 +0200237 depends on EARLY_CBMEM_INIT
Kyösti Mälkki730df3c2016-06-18 07:39:31 +0300238 default !NO_RELOCATABLE_RAMSTAGE
Vladimir Serbinenko633352c2015-05-30 22:21:37 +0200239 select RELOCATABLE_MODULES
Stefan Reinauer58470e32014-10-17 13:08:36 +0200240 help
241 The reloctable ramstage support allows for the ramstage to be built
242 as a relocatable module. The stage loader can identify a place
243 out of the OS way so that copying memory is unnecessary during an S3
244 wake. When selecting this option the romstage is responsible for
245 determing a stack location to use for loading the ramstage.
246
247config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
248 depends on RELOCATABLE_RAMSTAGE
Arthur Heymans410f2562017-01-25 15:27:52 +0100249 bool
Stefan Reinauer58470e32014-10-17 13:08:36 +0200250 help
251 The relocated ramstage is saved in an area specified by the
252 by the board and/or chipset.
253
Stefan Reinauer58470e32014-10-17 13:08:36 +0200254config UPDATE_IMAGE
255 bool "Update existing coreboot.rom image"
Stefan Reinauer58470e32014-10-17 13:08:36 +0200256 help
257 If this option is enabled, no new coreboot.rom file
258 is created. Instead it is expected that there already
259 is a suitable file for further processing.
260 The bootblock will not be modified.
261
Martin Roth5942e062016-01-20 14:59:21 -0700262 If unsure, select 'N'
263
Konstantin Aladyshev6544cb32015-01-24 18:52:10 +0400264config BOOTSPLASH_IMAGE
265 bool "Add a bootsplash image"
266 help
267 Select this option if you have a bootsplash image that you would
268 like to add to your ROM.
269
270 This will only add the image to the ROM. To actually run it check
271 options under 'Display' section.
272
273config BOOTSPLASH_FILE
274 string "Bootsplash path and filename"
275 depends on BOOTSPLASH_IMAGE
Martin Roth75e5cb72016-12-15 15:05:37 -0700276 # Default value set at the end of the file
Konstantin Aladyshev6544cb32015-01-24 18:52:10 +0400277 help
278 The path and filename of the file to use as graphical bootsplash
279 screen. The file format has to be jpg.
280
Uwe Hermannc04be932009-10-05 13:55:28 +0000281endmenu
282
Martin Roth026e4dc2015-06-19 23:17:15 -0600283menu "Mainboard"
284
Stefan Reinauera48ca842015-04-04 01:58:28 +0200285source "src/mainboard/Kconfig"
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000286
Marshall Dawsone9375132016-09-04 08:38:33 -0600287config DEVICETREE
288 string
289 default "devicetree.cb"
290 help
291 This symbol allows mainboards to select a different file under their
292 mainboard directory for the devicetree.cb file. This allows the board
293 variants that need different devicetrees to be in the same directory.
294
295 Examples: "devicetree.variant.cb"
296 "variant/devicetree.cb"
297
Furquan Shaikhf2419982018-06-21 18:50:48 -0700298config OVERRIDE_DEVICETREE
299 string
300 default ""
301 help
302 This symbol allows variants to provide an override devicetree file to
303 override the registers and/or add new devices on top of the ones
304 provided by baseboard devicetree using CONFIG_DEVICETREE.
305
306 Examples: "devicetree.variant-override.cb"
307 "variant/devicetree-override.cb"
308
Martin Roth026e4dc2015-06-19 23:17:15 -0600309config CBFS_SIZE
310 hex "Size of CBFS filesystem in ROM"
Martin Roth75e5cb72016-12-15 15:05:37 -0700311 # Default value set at the end of the file
Martin Roth026e4dc2015-06-19 23:17:15 -0600312 help
313 This is the part of the ROM actually managed by CBFS, located at the
314 end of the ROM (passed through cbfstool -o) on x86 and at at the start
315 of the ROM (passed through cbfstool -s) everywhere else. It defaults
316 to span the whole ROM on all but Intel systems that use an Intel Firmware
317 Descriptor. It can be overridden to make coreboot live alongside other
318 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
319 binaries.
320
Patrick Georgi8a3592e2015-09-16 18:10:52 +0200321config FMDFILE
322 string "fmap description file in fmd format"
Patrick Georgi5d7ab392015-12-12 00:23:15 +0100323 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
Patrick Georgi8a3592e2015-09-16 18:10:52 +0200324 default ""
325 help
326 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
327 but in some cases more complex setups are required.
328 When an fmd is specified, it overrides the default format.
329
Martin Rothda1ca202015-12-26 16:51:16 -0700330endmenu
331
Martin Rothb09a5692016-01-24 19:38:33 -0700332# load site-local kconfig to allow user specific defaults and overrides
333source "site-local/Kconfig"
334
Vladimir Serbinenkoa9db82f2014-10-16 13:21:47 +0200335config SYSTEM_TYPE_LAPTOP
Martin Roth595e7772015-04-26 18:53:26 -0600336 default n
337 bool
Vladimir Serbinenkoa9db82f2014-10-16 13:21:47 +0200338
Werner Zehc0fb3612016-01-14 15:08:36 +0100339config CBFS_AUTOGEN_ATTRIBUTES
340 default n
341 bool
342 help
343 If this option is selected, every file in cbfs which has a constraint
344 regarding position or alignment will get an additional file attribute
345 which describes this constraint.
346
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000347menu "Chipset"
348
Duncan Lauried2119762015-06-08 18:11:56 -0700349comment "SoC"
Chris Chingaa8e5d32017-10-20 10:43:39 -0600350source "src/soc/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000351comment "CPU"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200352source "src/cpu/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000353comment "Northbridge"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200354source "src/northbridge/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000355comment "Southbridge"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200356source "src/southbridge/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000357comment "Super I/O"
Omar Pakker57603e22016-07-29 23:31:45 +0200358source "src/superio/*/*/Kconfig"
Sven Schnelle7592e8b2011-01-27 11:43:03 +0000359comment "Embedded Controllers"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200360source "src/ec/acpi/Kconfig"
361source "src/ec/*/*/Kconfig"
Stefan Reinauer86ddd732016-03-11 20:22:28 -0800362# FIXME move to vendorcode
Marc Jones78687972015-04-22 23:16:31 -0600363source "src/drivers/intel/fsp1_0/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000364
Martin Roth59aa2b12015-06-20 16:17:12 -0600365source "src/southbridge/intel/common/firmware/Kconfig"
Martin Rothe1523ec2015-06-19 22:30:43 -0600366source "src/vendorcode/*/Kconfig"
Martin Roth59aa2b12015-06-20 16:17:12 -0600367
Martin Rothe1523ec2015-06-19 22:30:43 -0600368source "src/arch/*/Kconfig"
369
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000370endmenu
Patrick Georgi0588d192009-08-12 15:00:51 +0000371
Stefan Reinauera48ca842015-04-04 01:58:28 +0200372source "src/device/Kconfig"
Stefan Reinauer95a63962012-11-13 17:00:01 -0800373
Rudolf Marekd9c25492010-05-16 15:31:53 +0000374menu "Generic Drivers"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200375source "src/drivers/*/Kconfig"
Stefan Reinauer86ddd732016-03-11 20:22:28 -0800376source "src/drivers/*/*/Kconfig"
Lee Leahy48dbc662017-05-08 16:56:03 -0700377source "src/commonlib/storage/Kconfig"
Rudolf Marekd9c25492010-05-16 15:31:53 +0000378endmenu
379
Philipp Deppenwiese1899fbe2017-10-16 17:09:33 +0200380menu "Security"
381
382source "src/security/Kconfig"
383
384endmenu
385
Martin Roth09210a12016-05-17 11:28:23 -0600386source "src/acpi/Kconfig"
387
Aaron Durbin4a36c4e2016-08-11 11:02:26 -0500388# This option is for the current boards/chipsets where SPI flash
389# is not the boot device. Currently nearly all boards/chipsets assume
390# SPI flash is the boot device.
391config BOOT_DEVICE_NOT_SPI_FLASH
392 bool
393 default n
394
395config BOOT_DEVICE_SPI_FLASH
396 bool
397 default y if !BOOT_DEVICE_NOT_SPI_FLASH
398 default n
399
Aaron Durbin16c173f2016-08-11 14:04:10 -0500400config BOOT_DEVICE_MEMORY_MAPPED
401 bool
402 default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH
403 default n
404 help
405 Inform system if SPI is memory-mapped or not.
406
Aaron Durbine8e118d2016-08-12 15:00:10 -0500407config BOOT_DEVICE_SUPPORTS_WRITES
408 bool
409 default n
410 help
411 Indicate that the platform has writable boot device
412 support.
413
Patrick Georgi0770f252015-04-22 13:28:21 +0200414config RTC
415 bool
416 default n
417
Patrick Georgi0588d192009-08-12 15:00:51 +0000418config HEAP_SIZE
419 hex
Myles Watson04000f42009-10-16 19:12:49 +0000420 default 0x4000
Patrick Georgi0588d192009-08-12 15:00:51 +0000421
Julius Wernerc3e7c4e2014-09-19 13:18:16 -0700422config STACK_SIZE
423 hex
Julius Werner66a476a2015-10-12 16:45:21 -0700424 default 0x1000 if ARCH_X86
425 default 0x0
Julius Wernerc3e7c4e2014-09-19 13:18:16 -0700426
Patrick Georgi0588d192009-08-12 15:00:51 +0000427config MAX_CPUS
428 int
429 default 1
430
Stefan Reinauera48ca842015-04-04 01:58:28 +0200431source "src/console/Kconfig"
Patrick Georgi0588d192009-08-12 15:00:51 +0000432
433config HAVE_ACPI_RESUME
434 bool
435 default n
436
Kyösti Mälkki9d6f3652016-06-28 07:38:46 +0300437config ACPI_HUGE_LOWMEM_BACKUP
438 bool
Kyösti Mälkki43e9c932016-11-10 11:50:21 +0200439 default n
Kyösti Mälkki9d6f3652016-06-28 07:38:46 +0300440 help
441 On S3 resume path, backup low memory from RAMBASE..RAMTOP in CBMEM.
442
Aaron Durbin87c9fae2016-01-22 15:26:04 -0600443config RESUME_PATH_SAME_AS_BOOT
444 bool
445 default y if ARCH_X86
446 depends on HAVE_ACPI_RESUME
447 help
448 This option indicates that when a system resumes it takes the
449 same path as a regular boot. e.g. an x86 system runs from the
450 reset vector at 0xfffffff0 on both resume and warm/cold boot.
451
Timothy Pearson44d53422015-05-18 16:04:10 -0500452config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
453 bool
Kyösti Mälkkib5664de2016-07-08 13:33:00 +0300454 depends on EARLY_CBMEM_INIT
Timothy Pearson44d53422015-05-18 16:04:10 -0500455 default n
456
Timothy Pearson7b22d842015-08-28 19:52:05 -0500457config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
458 bool
Kyösti Mälkkib5664de2016-07-08 13:33:00 +0300459 depends on EARLY_CBMEM_INIT
Timothy Pearson7b22d842015-08-28 19:52:05 -0500460 default n
461 help
462 This should be enabled on certain plaforms, such as the AMD
463 SR565x, that cannot handle concurrent CBFS accesses from
464 multiple APs during early startup.
465
Timothy Pearsonc764c742015-08-28 20:48:17 -0500466config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
467 bool
Kyösti Mälkkib5664de2016-07-08 13:33:00 +0300468 depends on EARLY_CBMEM_INIT
Timothy Pearsonc764c742015-08-28 20:48:17 -0500469 default n
470
Aaron Durbina4217912013-04-29 22:31:51 -0500471config HAVE_MONOTONIC_TIMER
472 def_bool n
473 help
474 The board/chipset provides a monotonic timer.
475
Aaron Durbine5e36302014-09-25 10:05:15 -0500476config GENERIC_UDELAY
477 def_bool n
478 depends on HAVE_MONOTONIC_TIMER
479 help
480 The board/chipset uses a generic udelay function utilizing the
481 monotonic timer.
482
Aaron Durbin340ca912013-04-30 09:58:12 -0500483config TIMER_QUEUE
484 def_bool n
485 depends on HAVE_MONOTONIC_TIMER
486 help
Kyösti Mälkkiecd84242013-09-13 07:57:49 +0300487 Provide a timer queue for performing time-based callbacks.
Aaron Durbin340ca912013-04-30 09:58:12 -0500488
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500489config COOP_MULTITASKING
490 def_bool n
Aaron Durbin38c326d2013-05-06 12:22:23 -0500491 depends on TIMER_QUEUE && ARCH_X86
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500492 help
493 Cooperative multitasking allows callbacks to be multiplexed on the
494 main thread of ramstage. With this enabled it allows for multiple
495 execution paths to take place when they have udelay() calls within
496 their code.
497
498config NUM_THREADS
499 int
500 default 4
501 depends on COOP_MULTITASKING
502 help
503 How many execution threads to cooperatively multitask with.
504
Patrick Georgi0588d192009-08-12 15:00:51 +0000505config HAVE_OPTION_TABLE
506 bool
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000507 default n
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000508 help
509 This variable specifies whether a given board has a cmos.layout
510 file containing NVRAM/CMOS bit definitions.
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000511 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
Patrick Georgi0588d192009-08-12 15:00:51 +0000512
Patrick Georgi0588d192009-08-12 15:00:51 +0000513config PIRQ_ROUTE
514 bool
515 default n
516
517config HAVE_SMI_HANDLER
518 bool
519 default n
520
521config PCI_IO_CFG_EXT
522 bool
523 default n
524
525config IOAPIC
526 bool
527 default n
528
Myles Watson45bb25f2009-09-22 18:49:08 +0000529config USE_WATCHDOG_ON_BOOT
530 bool
531 default n
532
Myles Watson45bb25f2009-09-22 18:49:08 +0000533config GFXUMA
534 bool
Myles Watsond73c1b52009-10-26 15:14:07 +0000535 default n
Myles Watson45bb25f2009-09-22 18:49:08 +0000536 help
537 Enable Unified Memory Architecture for graphics.
538
Myles Watsonb8e20272009-10-15 13:35:47 +0000539config HAVE_ACPI_TABLES
540 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000541 help
542 This variable specifies whether a given board has ACPI table support.
543 It is usually set in mainboard/*/Kconfig.
Myles Watsonb8e20272009-10-15 13:35:47 +0000544
545config HAVE_MP_TABLE
546 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000547 help
548 This variable specifies whether a given board has MP table support.
549 It is usually set in mainboard/*/Kconfig.
550 Whether or not the MP table is actually generated by coreboot
551 is configurable by the user via GENERATE_MP_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000552
553config HAVE_PIRQ_TABLE
554 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000555 help
556 This variable specifies whether a given board has PIRQ table support.
557 It is usually set in mainboard/*/Kconfig.
558 Whether or not the PIRQ table is actually generated by coreboot
559 is configurable by the user via GENERATE_PIRQ_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000560
Alexandru Gagniuc70c660f2012-08-23 02:32:58 -0500561config MAX_PIRQ_LINKS
562 int
563 default 4
564 help
565 This variable specifies the number of PIRQ interrupt links which are
566 routable. On most chipsets, this is 4, INTA through INTD. Some
567 chipsets offer more than four links, commonly up to INTH. They may
568 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
569 table specifies links greater than 4, pirq_route_irqs will not
570 function properly, unless this variable is correctly set.
571
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200572config COMMON_FADT
573 bool
574 default n
575
Aaron Durbin9420a522015-11-17 16:31:00 -0600576config ACPI_NHLT
577 bool
578 default n
579 help
580 Build support for NHLT (non HD Audio) ACPI table generation.
581
Marshall Dawson991467d2018-09-04 12:32:56 -0600582config ACPI_BERT
583 bool
584 depends on HAVE_ACPI_TABLES
585 help
586 Build an ACPI Boot Error Record Table.
587
Myles Watsond73c1b52009-10-26 15:14:07 +0000588#These Options are here to avoid "undefined" warnings.
589#The actual selection and help texts are in the following menu.
590
Uwe Hermann168b11b2009-10-07 16:15:40 +0000591menu "System tables"
Myles Watson45bb25f2009-09-22 18:49:08 +0000592
Myles Watsonb8e20272009-10-15 13:35:47 +0000593config GENERATE_MP_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800594 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
595 bool
596 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000597 help
598 Generate an MP table (conforming to the Intel MultiProcessor
599 specification 1.4) for this board.
600
601 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000602
Myles Watsonb8e20272009-10-15 13:35:47 +0000603config GENERATE_PIRQ_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800604 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
605 bool
606 default HAVE_PIRQ_TABLE
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000607 help
608 Generate a PIRQ table for this board.
609
610 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000611
Sven Schnelle164bcfd2011-08-14 20:56:34 +0200612config GENERATE_SMBIOS_TABLES
613 depends on ARCH_X86
614 bool "Generate SMBIOS tables"
615 default y
616 help
617 Generate SMBIOS tables for this board.
618
619 If unsure, say Y.
620
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200621config SMBIOS_PROVIDED_BY_MOBO
622 bool
623 default n
624
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200625config MAINBOARD_SERIAL_NUMBER
626 string "SMBIOS Serial Number"
627 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200628 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200629 default "123456789"
Martin Roth595e7772015-04-26 18:53:26 -0600630 help
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200631 The Serial Number to store in SMBIOS structures.
632
633config MAINBOARD_VERSION
634 string "SMBIOS Version Number"
635 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200636 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200637 default "1.0"
638 help
639 The Version Number to store in SMBIOS structures.
640
641config MAINBOARD_SMBIOS_MANUFACTURER
642 string "SMBIOS Manufacturer"
643 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200644 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200645 default MAINBOARD_VENDOR
646 help
647 Override the default Manufacturer stored in SMBIOS structures.
648
649config MAINBOARD_SMBIOS_PRODUCT_NAME
650 string "SMBIOS Product name"
651 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200652 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200653 default MAINBOARD_PART_NUMBER
654 help
655 Override the default Product name stored in SMBIOS structures.
656
Julien Viard de Galbert9d231a92018-02-28 13:39:55 +0100657config SMBIOS_ENCLOSURE_TYPE
658 hex
659 depends on GENERATE_SMBIOS_TABLES
660 default 0x09 if SYSTEM_TYPE_LAPTOP
661 default 0x03
662 help
663 System Enclosure or Chassis Types as defined in SMBIOS specification.
664 The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) or
665 SMBIOS_ENCLOSURE_LAPTOP (0x09) if SYSTEM_TYPE_LAPTOP is set.
666
Myles Watson45bb25f2009-09-22 18:49:08 +0000667endmenu
668
Martin Roth21c06502016-02-04 19:52:27 -0700669source "payloads/Kconfig"
Peter Stugea758ca22009-09-17 16:21:31 +0000670
Uwe Hermann168b11b2009-10-07 16:15:40 +0000671menu "Debugging"
672
Nico Huberd67edca2018-11-13 19:28:07 +0100673comment "CPU Debug Settings"
674source "src/cpu/*/Kconfig.debug"
675
676comment "General Debug Settings"
677
Uwe Hermann168b11b2009-10-07 16:15:40 +0000678# TODO: Better help text and detailed instructions.
Patrick Georgi0588d192009-08-12 15:00:51 +0000679config GDB_STUB
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000680 bool "GDB debugging support"
Rudolf Marek65888022012-03-25 20:51:16 +0200681 default n
Denis 'GNUtoo' Carikli3747ba12015-12-10 22:04:56 +0100682 depends on CONSOLE_SERIAL
Patrick Georgi0588d192009-08-12 15:00:51 +0000683 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000684 If enabled, you will be able to set breakpoints for gdb debugging.
Stefan Reinauer8677a232010-12-11 20:33:41 +0000685 See src/arch/x86/lib/c_start.S for details.
Patrick Georgi0588d192009-08-12 15:00:51 +0000686
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200687config GDB_WAIT
Denis 'GNUtoo' Carikli7d234f22015-12-10 21:58:52 +0100688 bool "Wait for a GDB connection in the ramstage"
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200689 default n
690 depends on GDB_STUB
691 help
Denis 'GNUtoo' Carikli7d234f22015-12-10 21:58:52 +0100692 If enabled, coreboot will wait for a GDB connection in the ramstage.
693
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200694
Julius Wernerd82e0cf2015-02-17 17:27:23 -0800695config FATAL_ASSERTS
696 bool "Halt when hitting a BUG() or assertion error"
697 default n
698 help
699 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
700
Nico Huber371a6672018-11-13 22:06:40 +0100701config HAVE_DEBUG_GPIO
702 bool
703
704config DEBUG_GPIO
705 bool "Output verbose GPIO debug messages"
706 depends on HAVE_DEBUG_GPIO
707
Stefan Reinauerfe422182012-05-02 16:33:18 -0700708config DEBUG_CBFS
709 bool "Output verbose CBFS debug messages"
710 default n
Stefan Reinauerfe422182012-05-02 16:33:18 -0700711 help
712 This option enables additional CBFS related debug messages.
713
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000714config HAVE_DEBUG_RAM_SETUP
715 def_bool n
716
Uwe Hermann01ce6012010-03-05 10:03:50 +0000717config DEBUG_RAM_SETUP
718 bool "Output verbose RAM init debug messages"
719 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000720 depends on HAVE_DEBUG_RAM_SETUP
Uwe Hermann01ce6012010-03-05 10:03:50 +0000721 help
722 This option enables additional RAM init related debug messages.
723 It is recommended to enable this when debugging issues on your
724 board which might be RAM init related.
725
726 Note: This option will increase the size of the coreboot image.
727
728 If unsure, say N.
729
Myles Watson80e914f2010-06-01 19:25:31 +0000730config DEBUG_PIRQ
731 bool "Check PIRQ table consistency"
732 default n
733 depends on GENERATE_PIRQ_TABLE
734 help
735 If unsure, say N.
736
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000737config HAVE_DEBUG_SMBUS
738 def_bool n
739
Uwe Hermann01ce6012010-03-05 10:03:50 +0000740config DEBUG_SMBUS
741 bool "Output verbose SMBus debug messages"
742 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000743 depends on HAVE_DEBUG_SMBUS
Uwe Hermann01ce6012010-03-05 10:03:50 +0000744 help
745 This option enables additional SMBus (and SPD) debug messages.
746
747 Note: This option will increase the size of the coreboot image.
748
749 If unsure, say N.
750
751config DEBUG_SMI
752 bool "Output verbose SMI debug messages"
753 default n
754 depends on HAVE_SMI_HANDLER
Nico Huber9e53db42018-06-05 22:34:08 +0200755 select SPI_FLASH_SMM if SPI_CONSOLE || CONSOLE_SPI_FLASH
Uwe Hermann01ce6012010-03-05 10:03:50 +0000756 help
757 This option enables additional SMI related debug messages.
758
759 Note: This option will increase the size of the coreboot image.
760
761 If unsure, say N.
762
Uwe Hermanna953f372010-11-10 00:14:32 +0000763# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
764# printk(BIOS_DEBUG, ...) calls.
765config DEBUG_MALLOC
Stefan Reinauer95a63962012-11-13 17:00:01 -0800766 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
767 bool
Uwe Hermanna953f372010-11-10 00:14:32 +0000768 default n
Uwe Hermanna953f372010-11-10 00:14:32 +0000769 help
770 This option enables additional malloc related debug messages.
771
772 Note: This option will increase the size of the coreboot image.
773
774 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300775
776# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
777# printk(BIOS_DEBUG, ...) calls.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300778config DEBUG_ACPI
Stefan Reinauer95a63962012-11-13 17:00:01 -0800779 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
780 bool
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300781 default n
782 help
783 This option enables additional ACPI related debug messages.
784
785 Note: This option will slightly increase the size of the coreboot image.
786
787 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300788
Uwe Hermanna953f372010-11-10 00:14:32 +0000789# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
790# printk(BIOS_DEBUG, ...) calls.
Myles Watson6c9bc012010-09-07 22:30:15 +0000791config REALMODE_DEBUG
Stefan Reinauer95a63962012-11-13 17:00:01 -0800792 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
793 bool
Myles Watson6c9bc012010-09-07 22:30:15 +0000794 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000795 depends on PCI_OPTION_ROM_RUN_REALMODE
Myles Watson6c9bc012010-09-07 22:30:15 +0000796 help
797 This option enables additional x86emu related debug messages.
798
799 Note: This option will increase the time to emulate a ROM.
800
801 If unsure, say N.
802
Uwe Hermann01ce6012010-03-05 10:03:50 +0000803config X86EMU_DEBUG
804 bool "Output verbose x86emu debug messages"
805 default n
806 depends on PCI_OPTION_ROM_RUN_YABEL
807 help
808 This option enables additional x86emu related debug messages.
809
810 Note: This option will increase the size of the coreboot image.
811
812 If unsure, say N.
813
814config X86EMU_DEBUG_JMP
815 bool "Trace JMP/RETF"
816 default n
817 depends on X86EMU_DEBUG
818 help
819 Print information about JMP and RETF opcodes from x86emu.
820
821 Note: This option will increase the size of the coreboot image.
822
823 If unsure, say N.
824
825config X86EMU_DEBUG_TRACE
826 bool "Trace all opcodes"
827 default n
828 depends on X86EMU_DEBUG
829 help
830 Print _all_ opcodes that are executed by x86emu.
Stefan Reinauer14e22772010-04-27 06:56:47 +0000831
Uwe Hermann01ce6012010-03-05 10:03:50 +0000832 WARNING: This will produce a LOT of output and take a long time.
833
834 Note: This option will increase the size of the coreboot image.
835
836 If unsure, say N.
837
838config X86EMU_DEBUG_PNP
839 bool "Log Plug&Play accesses"
840 default n
841 depends on X86EMU_DEBUG
842 help
843 Print Plug And Play accesses made by option ROMs.
844
845 Note: This option will increase the size of the coreboot image.
846
847 If unsure, say N.
848
849config X86EMU_DEBUG_DISK
850 bool "Log Disk I/O"
851 default n
852 depends on X86EMU_DEBUG
853 help
854 Print Disk I/O related messages.
855
856 Note: This option will increase the size of the coreboot image.
857
858 If unsure, say N.
859
860config X86EMU_DEBUG_PMM
861 bool "Log PMM"
862 default n
863 depends on X86EMU_DEBUG
864 help
865 Print messages related to POST Memory Manager (PMM).
866
867 Note: This option will increase the size of the coreboot image.
868
869 If unsure, say N.
870
871
872config X86EMU_DEBUG_VBE
873 bool "Debug VESA BIOS Extensions"
874 default n
875 depends on X86EMU_DEBUG
876 help
877 Print messages related to VESA BIOS Extension (VBE) functions.
878
879 Note: This option will increase the size of the coreboot image.
880
881 If unsure, say N.
882
883config X86EMU_DEBUG_INT10
884 bool "Redirect INT10 output to console"
885 default n
886 depends on X86EMU_DEBUG
887 help
888 Let INT10 (i.e. character output) calls print messages to debug output.
889
890 Note: This option will increase the size of the coreboot image.
891
892 If unsure, say N.
893
894config X86EMU_DEBUG_INTERRUPTS
895 bool "Log intXX calls"
896 default n
897 depends on X86EMU_DEBUG
898 help
899 Print messages related to interrupt handling.
900
901 Note: This option will increase the size of the coreboot image.
902
903 If unsure, say N.
904
905config X86EMU_DEBUG_CHECK_VMEM_ACCESS
906 bool "Log special memory accesses"
907 default n
908 depends on X86EMU_DEBUG
909 help
910 Print messages related to accesses to certain areas of the virtual
911 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
912
913 Note: This option will increase the size of the coreboot image.
914
915 If unsure, say N.
916
917config X86EMU_DEBUG_MEM
918 bool "Log all memory accesses"
919 default n
920 depends on X86EMU_DEBUG
921 help
922 Print memory accesses made by option ROM.
923 Note: This also includes accesses to fetch instructions.
924
925 Note: This option will increase the size of the coreboot image.
926
927 If unsure, say N.
928
929config X86EMU_DEBUG_IO
930 bool "Log IO accesses"
931 default n
932 depends on X86EMU_DEBUG
933 help
934 Print I/O accesses made by option ROM.
935
936 Note: This option will increase the size of the coreboot image.
937
938 If unsure, say N.
939
Denis 'GNUtoo' Carikli4cdc5d62013-05-15 00:19:49 +0200940config X86EMU_DEBUG_TIMINGS
941 bool "Output timing information"
942 default n
943 depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
944 help
945 Print timing information needed by i915tool.
946
947 If unsure, say N.
948
Stefan Reinauer1c56d9b2012-05-10 11:27:32 -0700949config DEBUG_SPI_FLASH
950 bool "Output verbose SPI flash debug messages"
951 default n
952 depends on SPI_FLASH
953 help
954 This option enables additional SPI flash related debug messages.
955
Kyösti Mälkki3be80cc2013-06-06 10:46:37 +0300956config DEBUG_USBDEBUG
957 bool "Output verbose USB 2.0 EHCI debug dongle messages"
958 default n
959 depends on USBDEBUG
960 help
961 This option enables additional USB 2.0 debug dongle related messages.
962
963 Select this to debug the connection of usbdebug dongle. Note that
964 you need some other working console to receive the messages.
965
Stefan Reinauer8e073822012-04-04 00:07:22 +0200966if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
967# Only visible with the right southbridge and loglevel.
968config DEBUG_INTEL_ME
969 bool "Verbose logging for Intel Management Engine"
970 default n
971 help
972 Enable verbose logging for Intel Management Engine driver that
973 is present on Intel 6-series chipsets.
974endif
975
Rudolf Marek7f0e9302011-09-02 23:23:41 +0200976config TRACE
977 bool "Trace function calls"
978 default n
979 help
980 If enabled, every function will print information to console once
981 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
982 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
Ben Gardner8420ad42015-11-18 10:46:53 -0600983 of calling function. Please note some printk related functions
Rudolf Marek7f0e9302011-09-02 23:23:41 +0200984 are omitted from trace to have good looking console dumps.
Stefan Reinauerd37ab452012-12-18 16:23:28 -0800985
986config DEBUG_COVERAGE
987 bool "Debug code coverage"
988 default n
989 depends on COVERAGE
990 help
991 If enabled, the code coverage hooks in coreboot will output some
992 information about the coverage data that is dumped.
993
Jonathan Neuschäferfc04f9b2016-06-29 21:59:32 +0200994config DEBUG_BOOT_STATE
995 bool "Debug boot state machine"
996 default n
997 help
998 Control debugging of the boot state machine. When selected displays
999 the state boundaries in ramstage.
1000
Nico Hubere84e62542016-10-05 17:43:56 +02001001config DEBUG_ADA_CODE
1002 bool "Compile debug code in Ada sources"
1003 default n
1004 help
1005 Add the compiler switch `-gnata` to compile code guarded by
1006 `pragma Debug`.
1007
Simon Glass46255f72018-07-12 15:26:07 -06001008config HAVE_EM100_SUPPORT
1009 bool "Platform can support the Dediprog EM100 SPI emulator"
1010 help
1011 This is enabled by platforms which can support using the EM100.
1012
1013config EM100
1014 bool "Configure image for EM100 usage"
1015 depends on HAVE_EM100_SUPPORT
1016 help
1017 The Dediprog EM100 SPI emulator allows fast loading of new SPI images
1018 over USB. However it only supports a maximum SPI clock of 20MHz and
1019 single data output. Enable this option to use a 20MHz SPI clock and
1020 disable "Dual Output Fast Read" Support.
1021
1022 On AMD platforms this changes the SPI speed at run-time if the
1023 mainboard code supports this. On supported Intel platforms this works
1024 by changing the settings in the descriptor.bin file.
1025
Uwe Hermann168b11b2009-10-07 16:15:40 +00001026endmenu
1027
Martin Roth8e4aafb2016-12-15 15:25:15 -07001028
1029###############################################################################
1030# Set variables with no prompt - these can be set anywhere, and putting at
1031# the end of this file gives the most flexibility.
Nico Huber3db76532017-05-18 18:07:34 +02001032
1033source "src/lib/Kconfig"
1034
Myles Watsond73c1b52009-10-26 15:14:07 +00001035config ENABLE_APIC_EXT_ID
1036 bool
1037 default n
Myles Watson2e672732009-11-12 16:38:03 +00001038
1039config WARNINGS_ARE_ERRORS
1040 bool
Edward O'Callaghan63f6dc72014-11-18 03:17:54 +11001041 default y
Patrick Georgi436f99b2009-11-27 16:55:13 +00001042
Peter Stuge51eafde2010-10-13 06:23:02 +00001043# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1044# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1045# mutually exclusive. One of these options must be selected in the
1046# mainboard Kconfig if the chipset supports enabling and disabling of
1047# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1048# in mainboard/Kconfig to know if the button should be enabled or not.
1049
1050config POWER_BUTTON_DEFAULT_ENABLE
1051 def_bool n
1052 help
1053 Select when the board has a power button which can optionally be
1054 disabled by the user.
1055
1056config POWER_BUTTON_DEFAULT_DISABLE
1057 def_bool n
1058 help
1059 Select when the board has a power button which can optionally be
1060 enabled by the user, e.g. when the board ships with a jumper over
1061 the power switch contacts.
1062
1063config POWER_BUTTON_FORCE_ENABLE
1064 def_bool n
1065 help
1066 Select when the board requires that the power button is always
1067 enabled.
1068
1069config POWER_BUTTON_FORCE_DISABLE
1070 def_bool n
1071 help
1072 Select when the board requires that the power button is always
1073 disabled, e.g. when it has been hardwired to ground.
1074
1075config POWER_BUTTON_IS_OPTIONAL
1076 bool
1077 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1078 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1079 help
1080 Internal option that controls ENABLE_POWER_BUTTON visibility.
Duncan Laurie72748002013-10-31 08:26:23 -07001081
1082config REG_SCRIPT
1083 bool
Duncan Laurie72748002013-10-31 08:26:23 -07001084 default n
1085 help
1086 Internal option that controls whether we compile in register scripts.
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07001087
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07001088config MAX_REBOOT_CNT
1089 int
1090 default 3
Timothy Pearson17ada2e2015-03-18 01:31:34 -05001091 help
1092 Internal option that sets the maximum number of bootblock executions allowed
1093 with the normal image enabled before assuming the normal image is defective
Vadim Bendebury9c9c3362014-07-23 09:40:02 -07001094 and switching to the fallback image.
Martin Roth59ff3402016-02-09 09:06:46 -07001095
Lee Leahyfc3741f2016-05-26 17:12:17 -07001096config CREATE_BOARD_CHECKLIST
1097 bool
1098 default n
1099 help
1100 When selected, creates a webpage showing the implementation status for
1101 the board. Routines highlighted in green are complete, yellow are
1102 optional and red are required and must be implemented. A table is
1103 produced for each stage of the boot process except the bootblock. The
1104 red items may be used as an implementation checklist for the board.
1105
1106config MAKE_CHECKLIST_PUBLIC
1107 bool
1108 default n
1109 help
1110 When selected, build/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html
1111 is copied into the Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board
1112 directory.
1113
1114config CHECKLIST_DATA_FILE_LOCATION
1115 string
1116 help
1117 Location of the <stage>_complete.dat and <stage>_optional.dat files
1118 that are consumed during checklist processing. <stage>_complete.dat
1119 contains the symbols that are expected to be in the resulting image.
1120 <stage>_optional.dat is a subset of <stage>_complete.dat and contains
1121 a list of weak symbols which the resulting image may consume. Other
1122 symbols contained only in <stage>_complete.dat will be flagged as
1123 required and not implemented if a weak implementation is found in the
1124 resulting image.
Nico Hubere0ed9022016-10-07 12:58:17 +02001125
Martin Roth8e4aafb2016-12-15 15:25:15 -07001126config UNCOMPRESSED_RAMSTAGE
1127 bool
1128
1129config NO_XIP_EARLY_STAGES
1130 bool
1131 default n if ARCH_X86
1132 default y
1133 help
1134 Identify if early stages are eXecute-In-Place(XIP).
1135
1136config EARLY_CBMEM_INIT
1137 def_bool !LATE_CBMEM_INIT
1138
1139config EARLY_CBMEM_LIST
1140 bool
1141 default n
1142 help
1143 Enable display of CBMEM during romstage and postcar.
1144
1145config RELOCATABLE_MODULES
1146 bool
1147 help
1148 If RELOCATABLE_MODULES is selected then support is enabled for
1149 building relocatable modules in the RAM stage. Those modules can be
1150 loaded anywhere and all the relocations are handled automatically.
1151
1152config NO_STAGE_CACHE
1153 bool
Kyösti Mälkkia8c0cb32018-06-25 15:38:45 +03001154 default y if !HAVE_ACPI_RESUME
Martin Roth8e4aafb2016-12-15 15:25:15 -07001155 help
1156 Do not save any component in stage cache for resume path. On resume,
1157 all components would be read back from CBFS again.
1158
1159config GENERIC_GPIO_LIB
1160 bool
1161 help
1162 If enabled, compile the generic GPIO library. A "generic" GPIO
1163 implies configurability usually found on SoCs, particularly the
1164 ability to control internal pull resistors.
1165
1166config GENERIC_SPD_BIN
1167 bool
1168 help
1169 If enabled, add support for adding spd.hex files in cbfs as spd.bin
1170 and locating it runtime to load SPD. Additionally provide provision to
1171 fetch SPD over SMBus.
1172
1173config DIMM_MAX
1174 int
1175 default 4
1176 depends on GENERIC_SPD_BIN
1177 help
1178 Total number of memory DIMM slots available on motherboard.
1179 It is multiplication of number of channel to number of DIMMs per
1180 channel
1181
1182config DIMM_SPD_SIZE
1183 int
1184 default 256
Martin Roth8e4aafb2016-12-15 15:25:15 -07001185 help
1186 Total SPD size that will be used for DIMM.
1187 Ex: DDR3 256, DDR4 512.
1188
Kane Chen66f1f382017-10-16 19:40:18 +08001189config SPD_READ_BY_WORD
1190 bool
1191
Martin Roth8e4aafb2016-12-15 15:25:15 -07001192config BOOTBLOCK_CUSTOM
1193 # To be selected by arch, SoC or mainboard if it does not want use the normal
1194 # src/lib/bootblock.c#main() C entry point.
1195 bool
1196
1197config C_ENVIRONMENT_BOOTBLOCK
1198 # To be selected by arch or platform if a C environment is available during the
1199 # bootblock. Normally this signifies availability of RW memory (e.g. SRAM).
1200 bool
1201
Martin Roth75e5cb72016-12-15 15:05:37 -07001202###############################################################################
1203# Set default values for symbols created before mainboards. This allows the
1204# option to be displayed in the general menu, but the default to be loaded in
1205# the mainboard if desired.
1206config COMPRESS_RAMSTAGE
1207 default y if !UNCOMPRESSED_RAMSTAGE
1208
1209config COMPRESS_PRERAM_STAGES
1210 depends on !ARCH_X86
1211 default y
1212
1213config INCLUDE_CONFIG_FILE
1214 default y
1215
Martin Roth75e5cb72016-12-15 15:05:37 -07001216config BOOTSPLASH_FILE
1217 depends on BOOTSPLASH_IMAGE
1218 default "bootsplash.jpg"
1219
1220config CBFS_SIZE
1221 default ROM_SIZE