blob: e065422fb29e6dbf9dab5eb9b60e9a51984e22e3 [file] [log] [blame]
Vadim Bendeburyab0f7102014-08-21 14:19:31 -07001#
2# This file is part of the coreboot project.
3#
4# Copyright (C) 2014 Imagination Technologies
5#
6# This program is free software; you can redistribute it and/or
7# modify it under the terms of the GNU General Public License as
8# published by the Free Software Foundation; version 2 of
9# the License.
10#
11# This program is distributed in the hope that it will be useful,
12# but WITHOUT ANY WARRANTY; without even the implied warranty of
13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14# GNU General Public License for more details.
15#
16# You should have received a copy of the GNU General Public License
17# along with this program; if not, write to the Free Software
18# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
19# MA 02110-1301 USA
20#
21
22if BOARD_GOOGLE_URARA
23
24config BOARD_SPECIFIC_OPTIONS
25 def_bool y
Vadim Bendeburycbc44f72014-11-29 15:28:23 -080026 select BOARD_ROMSIZE_KB_512
Ionela Voinescu92da7782015-01-08 11:56:36 +000027 select BOARD_ID_SUPPORT
Vadim Bendeburyab0f7102014-08-21 14:19:31 -070028 select BOOTBLOCK_CONSOLE
Vadim Bendeburyd0daeba2014-10-28 18:23:28 -070029 select MAINBOARD_HAS_CHROMEOS
Ionela Voinescudfd441d2014-11-11 13:39:18 +000030 select SPI_FLASH_WINBOND
Vadim Bendebury2d510d02014-09-29 12:43:40 -070031 select CPU_IMGTEC_PISTACHIO
Vadim Bendeburyab0f7102014-08-21 14:19:31 -070032 select COMMON_CBFS_SPI_WRAPPER
33 select MAINBOARD_HAS_BOOTBLOCK_INIT
34 select SPI_FLASH
35
36config MAINBOARD_DIR
37 string
38 default "google/urara"
39
40config MAINBOARD_PART_NUMBER
41 string
Vadim Bendebury2d510d02014-09-29 12:43:40 -070042 default "ImgTec Pistachio Virtual Platform"
Vadim Bendeburyab0f7102014-08-21 14:19:31 -070043
Ionela Voinescub3f666b2015-01-18 22:37:11 +000044config BOOTBLOCK_MAINBOARD_INIT
45 string
46 default "mainboard/google/urara/bootblock.c"
47
Vadim Bendeburyab0f7102014-08-21 14:19:31 -070048config DRAM_SIZE_MB
49 int
50 default 256
51
Ionela Voinescu33c10f82014-10-30 14:49:53 +000052config TTYS0_LCS
53 int
54 default 3
55
David Hendricks352135e2015-01-26 07:15:01 -080056config CONSOLE_SERIAL_UART_ADDRESS
57 hex
58 depends on DRIVERS_UART
59 default 0xB8101500
60
Ionela Voinescudfd441d2014-11-11 13:39:18 +000061config BOOT_MEDIA_SPI_BUS
62 int
63 default 1
64
Vadim Bendeburyab0f7102014-08-21 14:19:31 -070065endif