blob: ab4864b880458ce5a7bf8dd2d91886fe66681caf [file] [log] [blame]
Damien Zammit43a1f782015-08-19 15:16:59 +10001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 secunet Security Networks AG
5 * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <stdint.h>
18#include <arch/io.h>
Martin Rothcbe38922016-01-05 19:40:41 -070019#include "iomap.h"
Arthur Heymans349e0852017-04-09 20:48:37 +020020#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)
Martin Rothcbe38922016-01-05 19:40:41 -070021#include <southbridge/intel/i82801gx/i82801gx.h> /* DEFAULT_PMBASE */
Arthur Heymans349e0852017-04-09 20:48:37 +020022#else
23#include <southbridge/intel/i82801jx/i82801jx.h> /* DEFAULT_PMBASE */
24#endif
Arthur Heymanseff0c6a2016-06-18 21:52:30 +020025#include <pc80/mc146818rtc.h>
Damien Zammit43a1f782015-08-19 15:16:59 +100026#include "x4x.h"
Arthur Heymansef7e98a2016-12-30 21:07:18 +010027#include <cbmem.h>
28#include <console/console.h>
29#include <halt.h>
30#include <romstage_handoff.h>
Damien Zammit43a1f782015-08-19 15:16:59 +100031
32void x4x_early_init(void)
33{
Antonello Dettori60a6e152016-09-03 10:45:33 +020034 const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0);
Damien Zammit43a1f782015-08-19 15:16:59 +100035
36 /* Setup MCHBAR. */
37 pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1);
38
39 /* Setup DMIBAR. */
40 pci_write_config32(d0f0, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1);
41
42 /* Setup EPBAR. */
43 pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1);
44
45 /* Setup PMBASE */
Damien Zammitfe9876a2016-01-22 19:11:05 +110046 pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
Arthur Heymans70a1dda2017-03-09 01:58:24 +010047 pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x80);
Damien Zammit43a1f782015-08-19 15:16:59 +100048
49 /* Setup HECIBAR */
Arthur Heymans70a1dda2017-03-09 01:58:24 +010050 pci_write_config32(PCI_DEV(0, 3, 0), 0x10, DEFAULT_HECIBAR);
Damien Zammit43a1f782015-08-19 15:16:59 +100051
52 /* Set C0000-FFFFF to access RAM on both reads and writes */
53 pci_write_config8(d0f0, D0F0_PAM(0), 0x30);
54 pci_write_config8(d0f0, D0F0_PAM(1), 0x33);
55 pci_write_config8(d0f0, D0F0_PAM(2), 0x33);
56 pci_write_config8(d0f0, D0F0_PAM(3), 0x33);
57 pci_write_config8(d0f0, D0F0_PAM(4), 0x33);
58 pci_write_config8(d0f0, D0F0_PAM(5), 0x33);
59 pci_write_config8(d0f0, D0F0_PAM(6), 0x33);
60
Arthur Heymansd6f3dd82017-12-27 00:12:35 +010061 printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
62 RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
63 outw(1 << 11, DEFAULT_PMBASE + 0x60 + 0x08); /* halt timer */
64 outw(1 << 3, DEFAULT_PMBASE + 0x60 + 0x04); /* clear timeout */
65 outw(1 << 1, DEFAULT_PMBASE + 0x60 + 0x06); /* clear 2nd timeout */
66 printk(BIOS_DEBUG, " done.\n");
67
Arthur Heymans5e3cb722017-03-05 10:57:02 +010068 if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) {
69 /* Enable internal GFX */
70 pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN);
Arthur Heymanseff0c6a2016-06-18 21:52:30 +020071
Nico Hubercfd433b2017-05-12 17:10:58 +020072 /* Set preallocated IGD size from cmos */
73 u8 gfxsize = 6; /* 6 for 64MiB, default if not set in cmos */
74 get_option(&gfxsize, "gfx_uma_size");
75 if (gfxsize > 12)
Arthur Heymans5e3cb722017-03-05 10:57:02 +010076 gfxsize = 6;
Nico Hubercfd433b2017-05-12 17:10:58 +020077 pci_write_config16(d0f0, D0F0_GGC, 0x0100 | (gfxsize + 1) << 4);
Arthur Heymans5e3cb722017-03-05 10:57:02 +010078 } else { /* Does not feature internal graphics */
79 pci_write_config32(d0f0, D0F0_DEVEN, D0EN | D1EN | PEG1EN);
80 pci_write_config16(d0f0, D0F0_GGC, (1 << 1));
Arthur Heymanseff0c6a2016-06-18 21:52:30 +020081 }
Damien Zammit43a1f782015-08-19 15:16:59 +100082}
Arthur Heymansef7e98a2016-12-30 21:07:18 +010083
84static void init_egress(void)
85{
86 u32 reg32;
87
88 /* VC0: TC0 only */
89 EPBAR8(0x14) = 1;
90 EPBAR8(0x4) = 1;
91
92 switch (MCHBAR32(0xc00) & 0x7) {
93 case 0x0:
94 /* FSB 1066 */
95 EPBAR32(0x2c) = 0x0001a6db;
96 break;
97 case 0x2:
98 /* FSB 800 */
99 EPBAR32(0x2c) = 0x00014514;
100 break;
101 default:
102 case 0x4:
103 /* FSB 1333 */
104 EPBAR32(0x2c) = 0x00022861;
105 break;
106 }
107 EPBAR32(0x28) = 0x0a0a0a0a;
108 EPBAR8(0xc) = (EPBAR8(0xc) & ~0xe) | 2;
109 EPBAR32(0x1c) = (EPBAR32(0x1c) & ~0x7f0000) | 0x0a0000;
110 MCHBAR8(0x3c) = MCHBAR8(0x3c) | 0x7;
111
112 /* VC1: ID1, TC7 */
113 reg32 = (EPBAR32(0x20) & ~(7 << 24)) | (1 << 24);
114 reg32 = (reg32 & ~0xfe) | (1 << 7);
115 EPBAR32(0x20) = reg32;
116
117 /* Init VC1 port arbitration table */
118 EPBAR32(0x100) = 0x001000001;
119 EPBAR32(0x104) = 0x000040000;
120 EPBAR32(0x108) = 0x000001000;
121 EPBAR32(0x10c) = 0x000000040;
122 EPBAR32(0x110) = 0x001000001;
123 EPBAR32(0x114) = 0x000040000;
124 EPBAR32(0x118) = 0x000001000;
125 EPBAR32(0x11c) = 0x000000040;
126
127 /* Load table */
128 reg32 = EPBAR32(0x20) | (1 << 16);
129 EPBAR32(0x20) = reg32;
130 asm("nop");
131 EPBAR32(0x20) = reg32;
132
133 /* Wait for table load */
Arthur Heymans70a1dda2017-03-09 01:58:24 +0100134 while ((EPBAR8(0x26) & (1 << 0)) != 0)
135 ;
Arthur Heymansef7e98a2016-12-30 21:07:18 +0100136
137 /* VC1: enable */
138 EPBAR32(0x20) |= 1 << 31;
139
140 /* Wait for VC1 */
Arthur Heymans70a1dda2017-03-09 01:58:24 +0100141 while ((EPBAR8(0x26) & (1 << 1)) != 0)
142 ;
Arthur Heymansef7e98a2016-12-30 21:07:18 +0100143
144 printk(BIOS_DEBUG, "Done Egress Port\n");
145}
146
147static void init_dmi(void)
148{
149 u32 reg32;
150 u16 reg16;
151
152 /* Assume IGD present */
153
154 /* Clear error status */
155 DMIBAR32(0x1c4) = 0xffffffff;
156 DMIBAR32(0x1d0) = 0xffffffff;
157
158 /* VC0: TC0 only */
159 DMIBAR8(DMIVC0RCTL) = 1;
160 DMIBAR8(0x4) = 1;
161
162 /* VC1: ID1, TC7 */
163 reg32 = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24);
164 reg32 = (reg32 & ~0xff) | 1 << 7;
165
166 /* VC1: enable */
167 reg32 |= 1 << 31;
168 reg32 = (reg32 & ~(0x7 << 17)) | (0x4 << 17);
169
170 DMIBAR32(DMIVC1RCTL) = reg32;
171
172 /* Set up VCs in southbridge RCBA */
173 RCBA8(0x3022) &= ~1;
174
175 reg32 = (0x5 << 28) | (1 << 6); /* PCIe x4 */
176 RCBA32(0x2020) = (RCBA32(0x2020) & ~((0xf << 28) | (0x7 << 6))) | reg32;
177
178 /* Assign VC1 id 1 */
179 RCBA32(0x20) = (RCBA32(0x20) & ~(0x7 << 24)) | (1 << 24);
180
181 /* Map TC7 to VC1 */
182 RCBA8(0x20) &= 1;
183 RCBA8(0x20) |= 1 << 7;
184
185 /* Map TC0 to VC0 */
186 RCBA8(0x14) &= 1;
187
188 /* Init DMI VC1 port arbitration table */
189 RCBA32(0x20) &= 0xfff1ffff;
190 RCBA32(0x20) |= 1 << 19;
191
192 RCBA32(0x30) = 0x0000000f;
193 RCBA32(0x34) = 0x000f0000;
194 RCBA32(0x38) = 0;
195 RCBA32(0x3c) = 0x000000f0;
196 RCBA32(0x40) = 0x0f000000;
197 RCBA32(0x44) = 0;
198 RCBA32(0x48) = 0x0000f000;
199 RCBA32(0x4c) = 0;
200 RCBA32(0x50) = 0x0000000f;
201 RCBA32(0x54) = 0x000f0000;
202 RCBA32(0x58) = 0;
203 RCBA32(0x5c) = 0x000000f0;
204 RCBA32(0x60) = 0x0f000000;
205 RCBA32(0x64) = 0;
206 RCBA32(0x68) = 0x0000f000;
207 RCBA32(0x6c) = 0;
208
209 RCBA32(0x20) |= 1 << 16;
210
211 /* Enable VC1 */
212 RCBA32(0x20) |= 1 << 31;
213
214 /* Wait for VC1 */
Arthur Heymans70a1dda2017-03-09 01:58:24 +0100215 while ((RCBA8(0x26) & (1 << 1)) != 0)
216 ;
Arthur Heymansef7e98a2016-12-30 21:07:18 +0100217
218 /* Wait for table load */
Arthur Heymans70a1dda2017-03-09 01:58:24 +0100219 while ((RCBA8(0x26) & (1 << 0)) != 0)
220 ;
Arthur Heymansef7e98a2016-12-30 21:07:18 +0100221
222 /* ASPM on DMI link */
223 RCBA16(0x1a8) &= ~0x3;
224 reg16 = RCBA16(0x1a8);
225 RCBA32(0x2010) = (RCBA32(0x2010) & ~(0x3 << 10)) | (1 << 10);
226 reg32 = RCBA32(0x2010);
227
228 /* Set up VC1 max time */
229 RCBA32(0x1c) = (RCBA32(0x1c) & ~0x7f0000) | 0x120000;
230
Arthur Heymans70a1dda2017-03-09 01:58:24 +0100231 while ((DMIBAR32(0x26) & (1 << 1)) != 0)
232 ;
Arthur Heymansef7e98a2016-12-30 21:07:18 +0100233 printk(BIOS_DEBUG, "Done DMI setup\n");
234
235 /* ASPM on DMI */
236 DMIBAR32(0x200) &= ~(0x3 << 26);
237 DMIBAR16(0x210) = (DMIBAR16(0x210) & ~(0xff7)) | 0x101;
238 DMIBAR32(0x88) &= ~0x3;
239 DMIBAR32(0x88) |= 0x3;
240 reg16 = DMIBAR16(0x88);
241}
242
243static void x4x_prepare_resume(int s3resume)
244{
Arthur Heymansef7e98a2016-12-30 21:07:18 +0100245 romstage_handoff_init(s3resume);
246}
247
248void x4x_late_init(int s3resume)
249{
250 init_egress();
251 init_dmi();
252 x4x_prepare_resume(s3resume);
253}