blob: 15cd29b10626f652151dd9dcbd9a85276b726ea4 [file] [log] [blame]
Arthur Heymans0c290a02016-06-18 23:26:46 +02001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2007-2008 coresystems GmbH
5## Copyright (C) 2014 Vladimir Serbinenko
6##
7## This program is free software; you can redistribute it and/or modify
8## it under the terms of the GNU General Public License as published by
9## the Free Software Foundation; version 2 of the License.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16
17# -----------------------------------------------------------------
18entries
19
20# -----------------------------------------------------------------
21# Status Register A
22# -----------------------------------------------------------------
23# Status Register B
24# -----------------------------------------------------------------
25# Status Register C
26#96 4 r 0 status_c_rsvd
27#100 1 r 0 uf_flag
28#101 1 r 0 af_flag
29#102 1 r 0 pf_flag
30#103 1 r 0 irqf_flag
31# -----------------------------------------------------------------
32# Status Register D
33#104 7 r 0 status_d_rsvd
34#111 1 r 0 valid_cmos_ram
35# -----------------------------------------------------------------
36# Diagnostic Status Register
37#112 8 r 0 diag_rsvd1
38
39# -----------------------------------------------------------------
400 120 r 0 reserved_memory
41#120 264 r 0 unused
42
43# -----------------------------------------------------------------
44# RTC_BOOT_BYTE (coreboot hardcoded)
45384 1 e 4 boot_option
Nico Huberd23ee5d2016-08-11 22:45:55 +020046388 4 h 0 reboot_counter
Arthur Heymans0c290a02016-06-18 23:26:46 +020047#390 2 r 0 unused?
48
49# -----------------------------------------------------------------
50# coreboot config options: console
Arthur Heymansb29078e2017-05-12 21:16:41 +020051#392 3 r 0 unused
Arthur Heymans0c290a02016-06-18 23:26:46 +020052395 4 e 6 debug_level
53#399 1 r 0 unused
54
55# coreboot config options: southbridge
56408 1 e 1 nmi
57409 2 e 7 power_on_after_fail
58
59# coreboot config options: cpu
60#424 1 e 2 hyper_threading
61#425 7 r 0 unused
62
63# coreboot config options: northbridge
64432 4 e 11 gfx_uma_size
65#435 549 r 0 unused
66
67
68# coreboot config options: check sums
69984 16 h 0 check_sum
70
Arthur Heymans97e13d82016-11-30 18:40:38 +0100711024 144 r 0 recv_enable_results
Arthur Heymans0c290a02016-06-18 23:26:46 +020072# -----------------------------------------------------------------
73
74enumerations
75
76#ID value text
771 0 Disable
781 1 Enable
792 0 Enable
802 1 Disable
814 0 Fallback
824 1 Normal
Arthur Heymansc1413232018-01-09 16:51:33 +0100836 0 Emergency
846 1 Alert
856 2 Critical
866 3 Error
876 4 Warning
886 5 Notice
896 6 Info
906 7 Debug
916 8 Spew
Arthur Heymans0c290a02016-06-18 23:26:46 +0200927 0 Disable
937 1 Enable
947 2 Keep
9511 0 1M
9611 1 4M
9711 2 8M
9811 3 16M
9911 4 32M
10011 5 48M
10111 6 64M
10211 7 128M
10311 8 256M
10411 9 96M
10511 10 160M
10611 11 224M
10711 12 352M
108
109# -----------------------------------------------------------------
110checksums
111
112checksum 392 983 984