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Arthur Heymansbe913982016-10-15 18:00:22 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2008 coresystems GmbH
5 * Copyright (C) 2016 Arthur Heymans arthur@aheymans.xyz
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17// __PRE_RAM__ means: use "unsigned" for device, not a struct.
18
19#include <stdint.h>
20#include <string.h>
21#include <arch/io.h>
22#include <device/pci_def.h>
23#include <device/pnp_def.h>
24#include <cpu/x86/lapic.h>
25#include <lib.h>
26#include <arch/acpi.h>
27#include <cbmem.h>
Paul Menzel6c20b652016-12-29 22:54:02 +010028#include <timestamp.h>
Arthur Heymansbe913982016-10-15 18:00:22 +020029#include <superio/ite/it8718f/it8718f.h>
30#include <superio/ite/common/ite.h>
31#include <pc80/mc146818rtc.h>
32#include <console/console.h>
33#include <cpu/x86/bist.h>
34#include <cpu/intel/romstage.h>
35#include <northbridge/intel/i945/i945.h>
36#include <northbridge/intel/i945/raminit.h>
37#include <southbridge/intel/i82801gx/i82801gx.h>
38
39#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
40#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
41#define EC_DEV PNP_DEV(0x2e, IT8718F_EC)
42#define SUPERIO_DEV PNP_DEV(0x2e, 0)
43
Arthur Heymansbe913982016-10-15 18:00:22 +020044static void setup_sio(void)
45{
46 /* Set default GPIOs on superio */
47 ite_reg_write(GPIO_DEV, 0x25, 0x40);
48 ite_reg_write(GPIO_DEV, 0x26, 0x3f);
49 ite_reg_write(GPIO_DEV, 0x28, 0x41);
50 ite_reg_write(GPIO_DEV, 0x29, 0x88);
51 ite_reg_write(GPIO_DEV, 0x2c, 0x1c);
52 ite_reg_write(GPIO_DEV, 0x62, 0x08);
Arthur Heymans37d15c62016-11-14 00:05:29 +010053 ite_kill_watchdog(GPIO_DEV);
Arthur Heymansbe913982016-10-15 18:00:22 +020054 ite_reg_write(GPIO_DEV, 0xb1, 0x01);
55 ite_reg_write(GPIO_DEV, 0xb8, 0x80);
56 ite_reg_write(GPIO_DEV, 0xbb, 0x40);
57 ite_reg_write(GPIO_DEV, 0xc0, 0x00);
58 ite_reg_write(GPIO_DEV, 0xc3, 0x00);
59 ite_reg_write(GPIO_DEV, 0xc8, 0x00);
60 ite_reg_write(GPIO_DEV, 0xcb, 0x00);
61 ite_reg_write(GPIO_DEV, 0xf6, 0x26);
Arthur Heymans37d15c62016-11-14 00:05:29 +010062 ite_reg_write(GPIO_DEV, 0xfc, 0x01);
Arthur Heymansbe913982016-10-15 18:00:22 +020063
64 ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9
65 ite_reg_write(EC_DEV, 0x30, 0xff); // Enable
66}
67
68static void ich7_enable_lpc(void)
69{
70 // Enable Serial IRQ
Arthur Heymansb451df22017-08-15 20:59:09 +020071 pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
Arthur Heymansbe913982016-10-15 18:00:22 +020072 // Set COM1/COM2 decode range
Arthur Heymansb451df22017-08-15 20:59:09 +020073 pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0000);
Arthur Heymansbe913982016-10-15 18:00:22 +020074 // Enable COM1
Arthur Heymansb451df22017-08-15 20:59:09 +020075 pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN
76 | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
77 | COMA_LPC_EN);
Arthur Heymansbe913982016-10-15 18:00:22 +020078 // Enable SuperIO Power Management Events
Arthur Heymansb451df22017-08-15 20:59:09 +020079 pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0801);
Arthur Heymans59bf3092016-11-23 16:03:54 +010080 /* LPC decode range 2: Environment Controller */
Arthur Heymansb451df22017-08-15 20:59:09 +020081 pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00040291);
Arthur Heymansbe913982016-10-15 18:00:22 +020082}
83
84static void rcba_config(void)
85{
86 /* Enable IOAPIC */
Arthur Heymansb451df22017-08-15 20:59:09 +020087 RCBA8(OIC) = 0x03;
Arthur Heymansbe913982016-10-15 18:00:22 +020088
89 /* Disable unused devices */
Arthur Heymansb451df22017-08-15 20:59:09 +020090 RCBA32(FD) = 0x003c0061;
Arthur Heymansbe913982016-10-15 18:00:22 +020091
92 /* Enable PCIe Root Port Clock Gate */
Arthur Heymansb451df22017-08-15 20:59:09 +020093 RCBA32(CG) = 0x00000001;
Arthur Heymansbe913982016-10-15 18:00:22 +020094}
95
96static void early_ich7_init(void)
97{
98 uint8_t reg8;
99 uint32_t reg32;
100
101 // program secondary mlt XXX byte?
102 pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
103
104 // reset rtc power status
105 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
106 reg8 &= ~(1 << 2);
107 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
108
109 // usb transient disconnect
110 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
111 reg8 |= (3 << 0);
112 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
113
114 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
115 reg32 |= (1 << 29) | (1 << 17);
116 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
117
118 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
119 reg32 |= (1 << 31) | (1 << 27);
120 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
121
122 RCBA32(0x0088) = 0x0011d000;
123 RCBA16(0x01fc) = 0x060f;
124 RCBA32(0x01f4) = 0x86000040;
125 RCBA32(0x0214) = 0x10030509;
126 RCBA32(0x0218) = 0x00020504;
127 RCBA8(0x0220) = 0xc5;
Arthur Heymansb451df22017-08-15 20:59:09 +0200128 reg32 = RCBA32(GCS);
Arthur Heymansbe913982016-10-15 18:00:22 +0200129 reg32 |= (1 << 6);
Arthur Heymansb451df22017-08-15 20:59:09 +0200130 RCBA32(GCS) = reg32;
Arthur Heymansbe913982016-10-15 18:00:22 +0200131 reg32 = RCBA32(0x3430);
132 reg32 &= ~(3 << 0);
133 reg32 |= (1 << 0);
134 RCBA32(0x3430) = reg32;
Arthur Heymansb451df22017-08-15 20:59:09 +0200135 RCBA32(FD) |= (1 << 0);
Arthur Heymansbe913982016-10-15 18:00:22 +0200136 RCBA16(0x0200) = 0x2008;
137 RCBA8(0x2027) = 0x0d;
138 RCBA16(0x3e08) |= (1 << 7);
139 RCBA16(0x3e48) |= (1 << 7);
140 RCBA32(0x3e0e) |= (1 << 7);
141 RCBA32(0x3e4e) |= (1 << 7);
142
143 // next step only on ich7m b0 and later:
144 reg32 = RCBA32(0x2034);
145 reg32 &= ~(0x0f << 16);
146 reg32 |= (5 << 16);
147 RCBA32(0x2034) = reg32;
148}
149
150void mainboard_romstage_entry(unsigned long bist)
151{
152 int s3resume = 0, boot_mode = 0;
153
Paul Menzel6c20b652016-12-29 22:54:02 +0100154
155 timestamp_init(get_initial_timestamp());
156 timestamp_add_now(TS_START_ROMSTAGE);
157
Arthur Heymansbe913982016-10-15 18:00:22 +0200158 if (bist == 0)
159 enable_lapic();
160
161 ich7_enable_lpc();
162 /* Enable SuperIO PM */
163 setup_sio();
164 ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
165
166 /* Disable SIO reboot */
167 ite_reg_write(GPIO_DEV, 0xEF, 0x7E);
168
169 /* Set up the console */
170 console_init();
171
172 /* Halt if there was a built in self test failure */
173 report_bist_failure(bist);
174
175 if (MCHBAR16(SSKPD) == 0xCAFE) {
176 printk(BIOS_DEBUG, "soft reset detected.\n");
177 boot_mode = 1;
178 }
179
180 /* Perform some early chipset initialization required
181 * before RAM initialization can work
182 */
183 i945_early_initialization();
184
185 s3resume = southbridge_detect_s3_resume();
186
187 /* Enable SPD ROMs and DDR-II DRAM */
188 enable_smbus();
189
190#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
191 dump_spd_registers();
192#endif
Paul Menzel6c20b652016-12-29 22:54:02 +0100193
194 timestamp_add_now(TS_BEFORE_INITRAM);
Arthur Heymansbe913982016-10-15 18:00:22 +0200195 sdram_initialize(s3resume ? 2 : boot_mode, NULL);
Paul Menzel6c20b652016-12-29 22:54:02 +0100196 timestamp_add_now(TS_AFTER_INITRAM);
Arthur Heymansbe913982016-10-15 18:00:22 +0200197
198 /* Perform some initialization that must run before stage2 */
199 early_ich7_init();
200
201 /* This should probably go away. Until now it is required
202 * and mainboard specific
203 */
204 rcba_config();
205
206 /* Chipset Errata! */
207 fixup_i945_errata();
208
209 /* Initialize the internal PCIe links before we go into stage2 */
210 i945_late_initialization(s3resume);
211}