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Furquan Shaikh24869572014-07-17 11:36:08 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2014 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#ifndef __ARCH_ARM64_MMU_H__
21#define __ARCH_ARM64_MMU_H__
22
23#include <memrange.h>
24
Furquan Shaikh24869572014-07-17 11:36:08 -070025/* Memory attributes for mmap regions
26 * These attributes act as tag values for memrange regions
27 */
28
29/* Normal memory / device */
30#define MA_MEM (1 << 0)
31#define MA_DEV (0 << 0)
32
33/* Secure / non-secure */
34#define MA_NS (1 << 1)
35#define MA_S (0 << 1)
36
37/* Read only / Read-write */
38#define MA_RO (1 << 2)
39#define MA_RW (0 << 2)
40
Aaron Durbin4633dc12014-08-12 17:40:38 -050041/* Non-cacheable memory. */
42#define MA_MEM_NC (1 << 3)
43
Furquan Shaikh24869572014-07-17 11:36:08 -070044/* Descriptor attributes */
45
46#define INVALID_DESC 0x0
47#define BLOCK_DESC 0x1
48#define TABLE_DESC 0x3
49#define PAGE_DESC 0x3
50
51/* Block descriptor */
52#define BLOCK_NS (1 << 5)
53
54#define BLOCK_AP_RW (0 << 7)
55#define BLOCK_AP_RO (1 << 7)
56
57#define BLOCK_ACCESS (1 << 10)
58
Furquan Shaikh55aa17b2015-03-27 22:52:18 -070059#define BLOCK_SH_SHIFT (8)
60#define BLOCK_SH_NON_SHAREABLE (0 << BLOCK_SH_SHIFT)
61#define BLOCK_SH_UNPREDICTABLE (1 << BLOCK_SH_SHIFT)
62#define BLOCK_SH_OUTER_SHAREABLE (2 << BLOCK_SH_SHIFT)
63#define BLOCK_SH_INNER_SHAREABLE (3 << BLOCK_SH_SHIFT)
64
Furquan Shaikh24869572014-07-17 11:36:08 -070065/* XLAT Table Init Attributes */
66
67#define VA_START 0x0
Furquan Shaikh24869572014-07-17 11:36:08 -070068#define BITS_PER_VA 33
Jimmy Huangdea45972015-04-13 20:28:38 +080069/* Granule size of 4KB is being used */
70#define GRANULE_SIZE_SHIFT 12
Furquan Shaikh24869572014-07-17 11:36:08 -070071#define GRANULE_SIZE (1 << GRANULE_SIZE_SHIFT)
Jimmy Huangdea45972015-04-13 20:28:38 +080072#define XLAT_TABLE_MASK (~(0UL) << GRANULE_SIZE_SHIFT)
73#define GRANULE_SIZE_MASK ((1 << GRANULE_SIZE_SHIFT) - 1)
Furquan Shaikh24869572014-07-17 11:36:08 -070074
Jimmy Huangdea45972015-04-13 20:28:38 +080075#define BITS_RESOLVED_PER_LVL (GRANULE_SIZE_SHIFT - 3)
76#define L1_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 2)
77#define L2_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 1)
78#define L3_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 0)
Furquan Shaikh24869572014-07-17 11:36:08 -070079
Jimmy Huangdea45972015-04-13 20:28:38 +080080#if BITS_PER_VA > L1_ADDR_SHIFT + BITS_RESOLVED_PER_LVL
81 #error "BITS_PER_VA too large (we don't have L0 table support)"
82#endif
Furquan Shaikh24869572014-07-17 11:36:08 -070083
Jimmy Huangdea45972015-04-13 20:28:38 +080084#define L1_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L1_ADDR_SHIFT)
85#define L2_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L2_ADDR_SHIFT)
86#define L3_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L3_ADDR_SHIFT)
Furquan Shaikh24869572014-07-17 11:36:08 -070087
88/* These macros give the size of the region addressed by each entry of a xlat
89 table at any given level */
Jimmy Huangdea45972015-04-13 20:28:38 +080090#define L3_XLAT_SIZE (1UL << L3_ADDR_SHIFT)
91#define L2_XLAT_SIZE (1UL << L2_ADDR_SHIFT)
92#define L1_XLAT_SIZE (1UL << L1_ADDR_SHIFT)
Furquan Shaikh24869572014-07-17 11:36:08 -070093
94/* Block indices required for MAIR */
95#define BLOCK_INDEX_MEM_DEV_NGNRNE 0
96#define BLOCK_INDEX_MEM_DEV_NGNRE 1
97#define BLOCK_INDEX_MEM_DEV_GRE 2
98#define BLOCK_INDEX_MEM_NORMAL_NC 3
99#define BLOCK_INDEX_MEM_NORMAL 4
100
101#define BLOCK_INDEX_SHIFT 2
102
103/* MAIR attributes */
104#define MAIR_ATTRIBUTES ((0x00 << (BLOCK_INDEX_MEM_DEV_NGNRNE*8)) | \
105 (0x04 << (BLOCK_INDEX_MEM_DEV_NGNRE*8)) | \
106 (0x0c << (BLOCK_INDEX_MEM_DEV_GRE*8)) | \
107 (0x44 << (BLOCK_INDEX_MEM_NORMAL_NC*8)) | \
108 (0xffUL << (BLOCK_INDEX_MEM_NORMAL*8)))
109
110/* TCR attributes */
111#define TCR_TOSZ (64 - BITS_PER_VA)
112
113#define TCR_IRGN0_SHIFT 8
114#define TCR_IRGN0_NM_NC (0x00 << TCR_IRGN0_SHIFT)
115#define TCR_IRGN0_NM_WBWAC (0x01 << TCR_IRGN0_SHIFT)
116#define TCR_IRGN0_NM_WTC (0x02 << TCR_IRGN0_SHIFT)
117#define TCR_IRGN0_NM_WBNWAC (0x03 << TCR_IRGN0_SHIFT)
118
119#define TCR_ORGN0_SHIFT 10
120#define TCR_ORGN0_NM_NC (0x00 << TCR_ORGN0_SHIFT)
121#define TCR_ORGN0_NM_WBWAC (0x01 << TCR_ORGN0_SHIFT)
122#define TCR_ORGN0_NM_WTC (0x02 << TCR_ORGN0_SHIFT)
123#define TCR_ORGN0_NM_WBNWAC (0x03 << TCR_ORGN0_SHIFT)
124
125#define TCR_SH0_SHIFT 12
126#define TCR_SH0_NC (0x0 << TCR_SH0_SHIFT)
127#define TCR_SH0_OS (0x2 << TCR_SH0_SHIFT)
128#define TCR_SH0_IS (0x3 << TCR_SH0_SHIFT)
129
130#define TCR_TG0_SHIFT 14
131#define TCR_TG0_4KB (0x0 << TCR_TG0_SHIFT)
132#define TCR_TG0_64KB (0x1 << TCR_TG0_SHIFT)
133#define TCR_TG0_16KB (0x2 << TCR_TG0_SHIFT)
134
135#define TCR_PS_SHIFT 16
136#define TCR_PS_4GB (0x0 << TCR_PS_SHIFT)
137#define TCR_PS_64GB (0x1 << TCR_PS_SHIFT)
138#define TCR_PS_1TB (0x2 << TCR_PS_SHIFT)
139#define TCR_PS_4TB (0x3 << TCR_PS_SHIFT)
140#define TCR_PS_16TB (0x4 << TCR_PS_SHIFT)
141#define TCR_PS_256TB (0x5 << TCR_PS_SHIFT)
142
143#define TCR_TBI_SHIFT 20
144#define TCR_TBI_USED (0x0 << TCR_TBI_SHIFT)
145#define TCR_TBI_IGNORED (0x1 << TCR_TBI_SHIFT)
146
Aaron Durbin339f8b32014-08-27 14:58:43 -0500147/* Initialize the MMU TTB tables provide the range sequence and ttb buffer. */
148void mmu_init(struct memranges *ranges, uint64_t *ttb, uint64_t ttb_size);
149/* Enable the mmu based on previous mmu_init(). */
150void mmu_enable(void);
Furquan Shaikh24869572014-07-17 11:36:08 -0700151
152#endif // __ARCH_ARM64_MMU_H__