Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <console/console.h> |
| 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <device/pciexp.h> |
| 25 | #include <device/pci_def.h> |
| 26 | #include <device/pci_ids.h> |
| 27 | #include <broadwell/gpio.h> |
| 28 | #include <broadwell/lpc.h> |
| 29 | #include <broadwell/iobp.h> |
| 30 | #include <broadwell/pch.h> |
| 31 | #include <broadwell/pci_devs.h> |
| 32 | #include <broadwell/rcba.h> |
| 33 | #include <chip.h> |
| 34 | |
| 35 | static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or); |
| 36 | static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or); |
| 37 | |
| 38 | /* Low Power variant has 6 root ports. */ |
| 39 | #define NUM_ROOT_PORTS 6 |
| 40 | |
| 41 | struct root_port_config { |
| 42 | /* RPFN is a write-once register so keep a copy until it is written */ |
| 43 | u32 orig_rpfn; |
| 44 | u32 new_rpfn; |
| 45 | u32 pin_ownership; |
| 46 | u32 strpfusecfg1; |
| 47 | u32 strpfusecfg2; |
| 48 | u32 strpfusecfg3; |
| 49 | u32 b0d28f0_32c; |
| 50 | u32 b0d28f4_32c; |
| 51 | u32 b0d28f5_32c; |
| 52 | int coalesce; |
| 53 | int gbe_port; |
| 54 | int num_ports; |
| 55 | device_t ports[NUM_ROOT_PORTS]; |
| 56 | }; |
| 57 | |
| 58 | static struct root_port_config rpc; |
| 59 | |
| 60 | static inline int root_port_is_first(device_t dev) |
| 61 | { |
| 62 | return PCI_FUNC(dev->path.pci.devfn) == 0; |
| 63 | } |
| 64 | |
| 65 | static inline int root_port_is_last(device_t dev) |
| 66 | { |
| 67 | return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1); |
| 68 | } |
| 69 | |
| 70 | /* Root ports are numbered 1..N in the documentation. */ |
| 71 | static inline int root_port_number(device_t dev) |
| 72 | { |
| 73 | return PCI_FUNC(dev->path.pci.devfn) + 1; |
| 74 | } |
| 75 | |
| 76 | static void root_port_config_update_gbe_port(void) |
| 77 | { |
| 78 | /* Is the Gbe Port enabled? */ |
| 79 | if (!((rpc.strpfusecfg1 >> 19) & 1)) |
| 80 | return; |
| 81 | |
| 82 | switch ((rpc.strpfusecfg1 >> 16) & 0x7) { |
| 83 | case 0: |
| 84 | rpc.gbe_port = 3; |
| 85 | break; |
| 86 | case 1: |
| 87 | rpc.gbe_port = 4; |
| 88 | break; |
| 89 | case 2: |
| 90 | case 3: |
| 91 | case 4: |
| 92 | case 5: |
| 93 | /* Lanes 0-4 of Root Port 5. */ |
| 94 | rpc.gbe_port = 5; |
| 95 | break; |
| 96 | default: |
| 97 | printk(BIOS_DEBUG, "Invalid GbE Port Selection.\n"); |
| 98 | } |
| 99 | } |
| 100 | |
| 101 | static void root_port_init_config(device_t dev) |
| 102 | { |
| 103 | int rp; |
| 104 | |
| 105 | if (root_port_is_first(dev)) { |
| 106 | rpc.orig_rpfn = RCBA32(RPFN); |
| 107 | rpc.new_rpfn = rpc.orig_rpfn; |
| 108 | rpc.num_ports = NUM_ROOT_PORTS; |
| 109 | rpc.gbe_port = -1; |
| 110 | |
| 111 | rpc.pin_ownership = pci_read_config32(dev, 0x410); |
| 112 | root_port_config_update_gbe_port(); |
| 113 | |
| 114 | if (dev->chip_info != NULL) { |
| 115 | config_t *config = dev->chip_info; |
| 116 | rpc.coalesce = config->pcie_port_coalesce; |
| 117 | } |
| 118 | } |
| 119 | |
| 120 | rp = root_port_number(dev); |
| 121 | if (rp > rpc.num_ports) { |
| 122 | printk(BIOS_ERR, "Found Root Port %d, expecting %d\n", |
| 123 | rp, rpc.num_ports); |
| 124 | return; |
| 125 | } |
| 126 | |
| 127 | /* Read the fuse configuration and pin ownership. */ |
| 128 | switch (rp) { |
| 129 | case 1: |
| 130 | rpc.strpfusecfg1 = pci_read_config32(dev, 0xfc); |
| 131 | rpc.b0d28f0_32c = pci_read_config32(dev, 0x32c); |
| 132 | break; |
| 133 | case 5: |
| 134 | rpc.strpfusecfg2 = pci_read_config32(dev, 0xfc); |
| 135 | rpc.b0d28f4_32c = pci_read_config32(dev, 0x32c); |
| 136 | break; |
| 137 | case 6: |
| 138 | rpc.b0d28f5_32c = pci_read_config32(dev, 0x32c); |
| 139 | rpc.strpfusecfg3 = pci_read_config32(dev, 0xfc); |
| 140 | break; |
| 141 | default: |
| 142 | break; |
| 143 | } |
| 144 | |
| 145 | /* Cache pci device. */ |
| 146 | rpc.ports[rp - 1] = dev; |
| 147 | } |
| 148 | |
| 149 | /* Update devicetree with new Root Port function number assignment */ |
| 150 | static void pch_pcie_device_set_func(int index, int pci_func) |
| 151 | { |
| 152 | device_t dev; |
| 153 | unsigned new_devfn; |
| 154 | |
| 155 | dev = rpc.ports[index]; |
| 156 | |
| 157 | /* Set the new PCI function field for this Root Port. */ |
| 158 | rpc.new_rpfn &= ~RPFN_FNMASK(index); |
| 159 | rpc.new_rpfn |= RPFN_FNSET(index, pci_func); |
| 160 | |
| 161 | /* Determine the new devfn for this port */ |
| 162 | new_devfn = PCI_DEVFN(PCH_DEV_SLOT_PCIE, pci_func); |
| 163 | |
| 164 | if (dev->path.pci.devfn != new_devfn) { |
| 165 | printk(BIOS_DEBUG, |
| 166 | "PCH: PCIe map %02x.%1x -> %02x.%1x\n", |
| 167 | PCI_SLOT(dev->path.pci.devfn), |
| 168 | PCI_FUNC(dev->path.pci.devfn), |
| 169 | PCI_SLOT(new_devfn), PCI_FUNC(new_devfn)); |
| 170 | |
| 171 | dev->path.pci.devfn = new_devfn; |
| 172 | } |
| 173 | } |
| 174 | |
| 175 | static void pcie_enable_clock_gating(void) |
| 176 | { |
| 177 | int i; |
| 178 | int enabled_ports = 0; |
| 179 | |
| 180 | for (i = 0; i < rpc.num_ports; i++) { |
| 181 | device_t dev; |
| 182 | int rp; |
| 183 | |
| 184 | dev = rpc.ports[i]; |
| 185 | rp = root_port_number(dev); |
| 186 | |
| 187 | if (!dev->enabled) { |
| 188 | /* Configure shared resource clock gating. */ |
| 189 | if (rp == 1 || rp == 5 || rp == 6) |
| 190 | pcie_update_cfg8(dev, 0xe1, 0xc3, 0x3c); |
| 191 | |
| 192 | pcie_update_cfg8(dev, 0xe2, ~(3 << 4), (3 << 4)); |
| 193 | pcie_update_cfg(dev, 0x420, ~(1 << 31), (1 << 31)); |
| 194 | |
| 195 | /* Per-Port CLKREQ# handling. */ |
| 196 | if (gpio_is_native(18 + rp - 1)) |
| 197 | pcie_update_cfg(dev, 0x420, ~0, (3 << 29)); |
| 198 | |
| 199 | /* Enable static clock gating. */ |
| 200 | if (rp == 1 && !rpc.ports[1]->enabled && |
| 201 | !rpc.ports[2]->enabled && !rpc.ports[3]->enabled) { |
| 202 | pcie_update_cfg8(dev, 0xe2, ~1, 1); |
| 203 | pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80); |
| 204 | } else if (rp == 5 || rp == 6) { |
| 205 | pcie_update_cfg8(dev, 0xe2, ~1, 1); |
| 206 | pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80); |
| 207 | } |
| 208 | continue; |
| 209 | } |
| 210 | |
| 211 | enabled_ports++; |
| 212 | |
| 213 | /* Enable dynamic clock gating. */ |
| 214 | pcie_update_cfg8(dev, 0xe1, 0xfc, 0x03); |
| 215 | pcie_update_cfg8(dev, 0xe2, ~(1 << 6), (1 << 6)); |
| 216 | pcie_update_cfg8(dev, 0xe8, ~(3 << 2), (2 << 2)); |
| 217 | |
| 218 | /* Update PECR1 register. */ |
| 219 | pcie_update_cfg8(dev, 0xe8, ~0, 1); |
| 220 | pcie_update_cfg8(dev, 0x324, ~(1 << 5), (1 < 5)); |
| 221 | |
| 222 | /* Per-Port CLKREQ# handling. */ |
| 223 | if (gpio_is_native(18 + rp - 1)) |
| 224 | pcie_update_cfg(dev, 0x420, ~0, (3 << 29)); |
| 225 | |
| 226 | /* Configure shared resource clock gating. */ |
| 227 | if (rp == 1 || rp == 5 || rp == 6) |
| 228 | pcie_update_cfg8(dev, 0xe1, 0xc3, 0x3c); |
| 229 | } |
| 230 | |
| 231 | if (!enabled_ports) |
| 232 | pcie_update_cfg8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6)); |
| 233 | } |
| 234 | |
| 235 | static void root_port_commit_config(void) |
| 236 | { |
| 237 | int i; |
| 238 | |
| 239 | /* If the first root port is disabled the coalesce ports. */ |
| 240 | if (!rpc.ports[0]->enabled) |
| 241 | rpc.coalesce = 1; |
| 242 | |
| 243 | /* Perform clock gating configuration. */ |
| 244 | pcie_enable_clock_gating(); |
| 245 | |
| 246 | for (i = 0; i < rpc.num_ports; i++) { |
| 247 | device_t dev; |
| 248 | u32 reg32; |
| 249 | |
| 250 | dev = rpc.ports[i]; |
| 251 | |
| 252 | if (dev == NULL) { |
| 253 | printk(BIOS_ERR, "Root Port %d device is NULL?\n", i+1); |
| 254 | continue; |
| 255 | } |
| 256 | |
| 257 | if (dev->enabled) |
| 258 | continue; |
| 259 | |
| 260 | printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); |
| 261 | |
| 262 | /* Ensure memory, io, and bus master are all disabled */ |
| 263 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 264 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 265 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 266 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 267 | |
| 268 | /* Disable this device if possible */ |
| 269 | pch_disable_devfn(dev); |
| 270 | } |
| 271 | |
| 272 | if (rpc.coalesce) { |
| 273 | int current_func; |
| 274 | |
| 275 | /* For all Root Ports N enabled ports get assigned the lower |
| 276 | * PCI function number. The disabled ones get upper PCI |
| 277 | * function numbers. */ |
| 278 | current_func = 0; |
| 279 | for (i = 0; i < rpc.num_ports; i++) { |
| 280 | if (!rpc.ports[i]->enabled) |
| 281 | continue; |
| 282 | pch_pcie_device_set_func(i, current_func); |
| 283 | current_func++; |
| 284 | } |
| 285 | |
| 286 | /* Allocate the disabled devices' PCI function number. */ |
| 287 | for (i = 0; i < rpc.num_ports; i++) { |
| 288 | if (rpc.ports[i]->enabled) |
| 289 | continue; |
| 290 | pch_pcie_device_set_func(i, current_func); |
| 291 | current_func++; |
| 292 | } |
| 293 | } |
| 294 | |
| 295 | printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", |
| 296 | rpc.orig_rpfn, rpc.new_rpfn); |
| 297 | RCBA32(RPFN) = rpc.new_rpfn; |
| 298 | } |
| 299 | |
| 300 | static void root_port_mark_disable(device_t dev) |
| 301 | { |
| 302 | /* Mark device as disabled. */ |
| 303 | dev->enabled = 0; |
| 304 | /* Mark device to be hidden. */ |
| 305 | rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); |
| 306 | } |
| 307 | |
| 308 | static void root_port_check_disable(device_t dev) |
| 309 | { |
| 310 | int rp; |
| 311 | |
| 312 | /* Device already disabled. */ |
| 313 | if (!dev->enabled) { |
| 314 | root_port_mark_disable(dev); |
| 315 | return; |
| 316 | } |
| 317 | |
| 318 | rp = root_port_number(dev); |
| 319 | |
| 320 | /* Is the GbE port mapped to this Root Port? */ |
| 321 | if (rp == rpc.gbe_port) { |
| 322 | root_port_mark_disable(dev); |
| 323 | return; |
| 324 | } |
| 325 | |
| 326 | /* Check Root Port Configuration. */ |
| 327 | switch (rp) { |
| 328 | case 2: |
| 329 | /* Root Port 2 is disabled for all lane configurations |
| 330 | * but config 00b (4x1 links). */ |
| 331 | if ((rpc.strpfusecfg1 >> 14) & 0x3) { |
| 332 | root_port_mark_disable(dev); |
| 333 | return; |
| 334 | } |
| 335 | break; |
| 336 | case 3: |
| 337 | /* Root Port 3 is disabled in config 11b (1x4 links). */ |
| 338 | if (((rpc.strpfusecfg1 >> 14) & 0x3) == 0x3) { |
| 339 | root_port_mark_disable(dev); |
| 340 | return; |
| 341 | } |
| 342 | break; |
| 343 | case 4: |
| 344 | /* Root Port 4 is disabled in configs 11b (1x4 links) |
| 345 | * and 10b (2x2 links). */ |
| 346 | if ((rpc.strpfusecfg1 >> 14) & 0x2) { |
| 347 | root_port_mark_disable(dev); |
| 348 | return; |
| 349 | } |
| 350 | break; |
| 351 | } |
| 352 | |
| 353 | /* Check Pin Ownership. */ |
| 354 | switch (rp) { |
| 355 | case 1: |
| 356 | /* Bit 0 is Root Port 1 ownership. */ |
| 357 | if ((rpc.pin_ownership & 0x1) == 0) { |
| 358 | root_port_mark_disable(dev); |
| 359 | return; |
| 360 | } |
| 361 | break; |
| 362 | case 2: |
| 363 | /* Bit 2 is Root Port 2 ownership. */ |
| 364 | if ((rpc.pin_ownership & 0x4) == 0) { |
| 365 | root_port_mark_disable(dev); |
| 366 | return; |
| 367 | } |
| 368 | break; |
| 369 | case 6: |
| 370 | /* Bits 7:4 are Root Port 6 pin-lane ownership. */ |
| 371 | if ((rpc.pin_ownership & 0xf0) == 0) { |
| 372 | root_port_mark_disable(dev); |
| 373 | return; |
| 374 | } |
| 375 | break; |
| 376 | } |
| 377 | } |
| 378 | |
| 379 | static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or) |
| 380 | { |
| 381 | u8 reg8; |
| 382 | |
| 383 | reg8 = pci_read_config8(dev, reg); |
| 384 | reg8 &= mask; |
| 385 | reg8 |= or; |
| 386 | pci_write_config8(dev, reg, reg8); |
| 387 | } |
| 388 | |
| 389 | static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) |
| 390 | { |
| 391 | u32 reg32; |
| 392 | |
| 393 | reg32 = pci_read_config32(dev, reg); |
| 394 | reg32 &= mask; |
| 395 | reg32 |= or; |
| 396 | pci_write_config32(dev, reg, reg32); |
| 397 | } |
| 398 | |
| 399 | static void pcie_add_0x0202000_iobp(u32 reg) |
| 400 | { |
| 401 | u32 reg32; |
| 402 | |
| 403 | reg32 = pch_iobp_read(reg); |
| 404 | reg32 += (0x2 << 16) | (0x2 << 8); |
| 405 | pch_iobp_write(reg, reg32); |
| 406 | } |
| 407 | |
| 408 | static void pch_pcie_early(struct device *dev) |
| 409 | { |
| 410 | config_t *config = dev->chip_info; |
| 411 | int do_aspm = 0; |
| 412 | int rp = root_port_number(dev); |
| 413 | |
| 414 | switch (rp) { |
| 415 | case 1: |
| 416 | case 2: |
| 417 | case 3: |
| 418 | case 4: |
| 419 | /* |
| 420 | * Bits 31:28 of b0d28f0 0x32c register correspnd to |
| 421 | * Root Ports 4:1. |
| 422 | */ |
| 423 | do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1))); |
| 424 | break; |
| 425 | case 5: |
| 426 | /* |
| 427 | * Bit 28 of b0d28f4 0x32c register correspnd to |
| 428 | * Root Ports 4:1. |
| 429 | */ |
| 430 | do_aspm = !!(rpc.b0d28f4_32c & (1 << 28)); |
| 431 | break; |
| 432 | case 6: |
| 433 | /* |
| 434 | * Bit 28 of b0d28f5 0x32c register correspnd to |
| 435 | * Root Ports 4:1. |
| 436 | */ |
| 437 | do_aspm = !!(rpc.b0d28f5_32c & (1 << 28)); |
| 438 | break; |
| 439 | } |
| 440 | |
| 441 | /* Allow ASPM to be forced on in devicetree */ |
| 442 | if (config && (config->pcie_port_force_aspm & (1 << (rp - 1)))) |
| 443 | do_aspm = 1; |
| 444 | |
| 445 | printk(BIOS_DEBUG, "PCIe Root Port %d ASPM is %sabled\n", |
| 446 | rp, do_aspm ? "en" : "dis"); |
| 447 | |
| 448 | if (do_aspm) { |
| 449 | /* Set ASPM bits in MPC2 register. */ |
| 450 | pcie_update_cfg(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2)); |
| 451 | |
| 452 | /* Set unique clock exit latency in MPC register. */ |
| 453 | pcie_update_cfg(dev, 0xd8, ~(0x7 << 18), (0x7 << 18)); |
| 454 | |
| 455 | /* Set L1 exit latency in LCAP register. */ |
| 456 | pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); |
| 457 | |
| 458 | switch (rp) { |
| 459 | case 1: |
| 460 | pcie_add_0x0202000_iobp(0xe9002440); |
| 461 | break; |
| 462 | case 2: |
| 463 | pcie_add_0x0202000_iobp(0xe9002640); |
| 464 | break; |
| 465 | case 3: |
| 466 | pcie_add_0x0202000_iobp(0xe9000840); |
| 467 | break; |
| 468 | case 4: |
| 469 | pcie_add_0x0202000_iobp(0xe9000a40); |
| 470 | break; |
| 471 | case 5: |
| 472 | pcie_add_0x0202000_iobp(0xe9000c40); |
| 473 | pcie_add_0x0202000_iobp(0xe9000e40); |
| 474 | pcie_add_0x0202000_iobp(0xe9001040); |
| 475 | pcie_add_0x0202000_iobp(0xe9001240); |
| 476 | break; |
| 477 | case 6: |
| 478 | /* Update IOBP based on lane ownership. */ |
| 479 | if (rpc.pin_ownership & (1 << 4)) |
| 480 | pcie_add_0x0202000_iobp(0xea002040); |
| 481 | if (rpc.pin_ownership & (1 << 5)) |
| 482 | pcie_add_0x0202000_iobp(0xea002240); |
| 483 | if (rpc.pin_ownership & (1 << 6)) |
| 484 | pcie_add_0x0202000_iobp(0xea002440); |
| 485 | if (rpc.pin_ownership & (1 << 7)) |
| 486 | pcie_add_0x0202000_iobp(0xea002640); |
| 487 | break; |
| 488 | } |
| 489 | |
| 490 | pcie_update_cfg(dev, 0x338, ~(1 << 26), 0); |
| 491 | } |
| 492 | |
| 493 | /* Enable LTR in Root Port. */ |
| 494 | pcie_update_cfg(dev, 0x64, ~(1 << 11), (1 << 11)); |
| 495 | pcie_update_cfg(dev, 0x68, ~(1 << 10), (1 << 10)); |
| 496 | |
| 497 | pcie_update_cfg(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); |
| 498 | |
| 499 | /* Set L1 exit latency in LCAP register. */ |
| 500 | if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1)) |
| 501 | pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); |
| 502 | else |
| 503 | pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); |
| 504 | |
| 505 | pcie_update_cfg(dev, 0x314, 0x0, 0x743a361b); |
| 506 | |
| 507 | /* Set Common Clock Exit Latency in MPC register. */ |
| 508 | pcie_update_cfg(dev, 0xd8, ~(0x7 << 15), (0x3 << 15)); |
| 509 | |
| 510 | pcie_update_cfg(dev, 0x33c, ~0x00ffffff, 0x854c74); |
| 511 | |
| 512 | /* Set Invalid Recieve Range Check Enable in MPC register. */ |
| 513 | pcie_update_cfg(dev, 0xd8, ~0, (1 << 25)); |
| 514 | |
| 515 | pcie_update_cfg8(dev, 0xf5, 0x3f, 0); |
| 516 | |
| 517 | if (rp == 1 || rp == 5 || rp == 6) |
| 518 | pcie_update_cfg8(dev, 0xf7, ~0xc, 0); |
| 519 | |
| 520 | /* Set EOI forwarding disable. */ |
| 521 | pcie_update_cfg(dev, 0xd4, ~0, (1 << 1)); |
| 522 | |
| 523 | /* Set something involving advanced error reporting. */ |
| 524 | pcie_update_cfg(dev, 0x100, ~((1 << 20) - 1), 0x10001); |
| 525 | pcie_update_cfg(dev, 0x100, ~0, (1 << 29)); |
| 526 | |
| 527 | /* Read and write back write-once capability registers. */ |
| 528 | pcie_update_cfg(dev, 0x34, ~0, 0); |
| 529 | pcie_update_cfg(dev, 0x40, ~0, 0); |
| 530 | pcie_update_cfg(dev, 0x80, ~0, 0); |
| 531 | pcie_update_cfg(dev, 0x90, ~0, 0); |
| 532 | } |
| 533 | |
| 534 | static void pch_pcie_init(struct device *dev) |
| 535 | { |
| 536 | u16 reg16; |
| 537 | u32 reg32; |
| 538 | |
| 539 | printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); |
| 540 | |
| 541 | /* Enable SERR */ |
| 542 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 543 | reg32 |= PCI_COMMAND_SERR; |
| 544 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 545 | |
| 546 | /* Enable Bus Master */ |
| 547 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 548 | reg32 |= PCI_COMMAND_MASTER; |
| 549 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 550 | |
| 551 | /* Set Cache Line Size to 0x10 */ |
| 552 | pci_write_config8(dev, 0x0c, 0x10); |
| 553 | |
| 554 | reg16 = pci_read_config16(dev, 0x3e); |
| 555 | reg16 &= ~(1 << 0); /* disable parity error response */ |
| 556 | reg16 |= (1 << 2); /* ISA enable */ |
| 557 | pci_write_config16(dev, 0x3e, reg16); |
| 558 | |
| 559 | #ifdef EVEN_MORE_DEBUG |
| 560 | reg32 = pci_read_config32(dev, 0x20); |
| 561 | printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); |
| 562 | reg32 = pci_read_config32(dev, 0x24); |
| 563 | printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32); |
| 564 | reg32 = pci_read_config32(dev, 0x28); |
| 565 | printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32); |
| 566 | reg32 = pci_read_config32(dev, 0x2c); |
| 567 | printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32); |
| 568 | #endif |
| 569 | |
| 570 | /* Clear errors in status registers */ |
| 571 | reg16 = pci_read_config16(dev, 0x06); |
| 572 | pci_write_config16(dev, 0x06, reg16); |
| 573 | reg16 = pci_read_config16(dev, 0x1e); |
| 574 | pci_write_config16(dev, 0x1e, reg16); |
| 575 | } |
| 576 | |
| 577 | static void pch_pcie_enable(device_t dev) |
| 578 | { |
| 579 | /* Add this device to the root port config structure. */ |
| 580 | root_port_init_config(dev); |
| 581 | |
| 582 | /* Check to see if this Root Port should be disabled. */ |
| 583 | root_port_check_disable(dev); |
| 584 | |
| 585 | /* Power Management init before enumeration */ |
| 586 | if (dev->enabled) |
| 587 | pch_pcie_early(dev); |
| 588 | |
| 589 | /* |
| 590 | * When processing the last PCIe root port we can now |
| 591 | * update the Root Port Function Number and Hide register. |
| 592 | */ |
| 593 | if (root_port_is_last(dev)) |
| 594 | root_port_commit_config(); |
| 595 | } |
| 596 | |
| 597 | static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 598 | { |
| 599 | /* NOTE: This is not the default position! */ |
| 600 | if (!vendor || !device) |
| 601 | pci_write_config32(dev, 0x94, pci_read_config32(dev, 0)); |
| 602 | else |
| 603 | pci_write_config32(dev, 0x94, (device << 16) | vendor); |
| 604 | } |
| 605 | |
| 606 | static struct pci_operations pcie_ops = { |
| 607 | .set_subsystem = pcie_set_subsystem, |
| 608 | }; |
| 609 | |
| 610 | static struct device_operations device_ops = { |
| 611 | .read_resources = pci_bus_read_resources, |
| 612 | .set_resources = pci_dev_set_resources, |
| 613 | .enable_resources = pci_bus_enable_resources, |
| 614 | .init = pch_pcie_init, |
| 615 | .enable = pch_pcie_enable, |
| 616 | .scan_bus = pciexp_scan_bridge, |
| 617 | .ops_pci = &pcie_ops, |
| 618 | }; |
| 619 | |
| 620 | static const unsigned short pcie_device_ids[] = { |
| 621 | /* Lynxpoint-LP */ |
| 622 | 0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a, |
| 623 | /* WildcatPoint */ |
| 624 | 0x9c90, 0x9c92, 0x9c94, 0x9c96, 0x9c98, 0x9c9a, 0x2448, |
| 625 | 0 |
| 626 | }; |
| 627 | |
| 628 | static const struct pci_driver pch_pcie __pci_driver = { |
| 629 | .ops = &device_ops, |
| 630 | .vendor = PCI_VENDOR_ID_INTEL, |
| 631 | .devices = pcie_device_ids, |
| 632 | }; |