Uwe Hermann | b80dbf0 | 2007-04-22 19:08:13 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Uwe Hermann | b80dbf0 | 2007-04-22 19:08:13 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2005 Linux Networx |
| 5 | * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx) |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
Patrick Georgi | b890a12 | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 18 | * Foundation, Inc. |
Uwe Hermann | b80dbf0 | 2007-04-22 19:08:13 +0000 | [diff] [blame] | 19 | */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 20 | |
| 21 | #include <console/console.h> |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 22 | #include <delay.h> |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <device/pciexp.h> |
| 27 | |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 28 | #if IS_ENABLED(CONFIG_MMCONF_SUPPORT) |
| 29 | unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap) |
| 30 | { |
| 31 | unsigned int this_cap_offset, next_cap_offset; |
| 32 | unsigned int this_cap, cafe; |
| 33 | |
| 34 | this_cap_offset = PCIE_EXT_CAP_OFFSET; |
| 35 | do { |
| 36 | this_cap = pci_mmio_read_config32(dev, this_cap_offset); |
| 37 | next_cap_offset = this_cap >> 20; |
| 38 | this_cap &= 0xffff; |
| 39 | cafe = pci_mmio_read_config32(dev, this_cap_offset + 4); |
| 40 | cafe &= 0xffff; |
| 41 | if (this_cap == cap) |
| 42 | return this_cap_offset; |
| 43 | else if (cafe == cap) |
| 44 | return this_cap_offset + 4; |
| 45 | else |
| 46 | this_cap_offset = next_cap_offset; |
| 47 | } while (next_cap_offset != 0); |
| 48 | |
| 49 | return 0; |
| 50 | } |
| 51 | #endif |
| 52 | |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 53 | #if CONFIG_PCIEXP_COMMON_CLOCK |
| 54 | /* |
| 55 | * Re-train a PCIe link |
| 56 | */ |
| 57 | #define PCIE_TRAIN_RETRY 10000 |
| 58 | static int pciexp_retrain_link(device_t dev, unsigned cap) |
| 59 | { |
| 60 | unsigned try = PCIE_TRAIN_RETRY; |
| 61 | u16 lnk; |
| 62 | |
| 63 | /* Start link retraining */ |
| 64 | lnk = pci_read_config16(dev, cap + PCI_EXP_LNKCTL); |
| 65 | lnk |= PCI_EXP_LNKCTL_RL; |
| 66 | pci_write_config16(dev, cap + PCI_EXP_LNKCTL, lnk); |
| 67 | |
| 68 | /* Wait for training to complete */ |
| 69 | while (try--) { |
| 70 | lnk = pci_read_config16(dev, cap + PCI_EXP_LNKSTA); |
| 71 | if (!(lnk & PCI_EXP_LNKSTA_LT)) |
| 72 | return 0; |
| 73 | udelay(100); |
| 74 | } |
| 75 | |
| 76 | printk(BIOS_ERR, "%s: Link Retrain timeout\n", dev_path(dev)); |
| 77 | return -1; |
| 78 | } |
| 79 | |
| 80 | /* |
| 81 | * Check the Slot Clock Configuration for root port and endpoint |
| 82 | * and enable Common Clock Configuration if possible. If CCC is |
| 83 | * enabled the link must be retrained. |
| 84 | */ |
| 85 | static void pciexp_enable_common_clock(device_t root, unsigned root_cap, |
| 86 | device_t endp, unsigned endp_cap) |
| 87 | { |
| 88 | u16 root_scc, endp_scc, lnkctl; |
| 89 | |
| 90 | /* Get Slot Clock Configuration for root port */ |
| 91 | root_scc = pci_read_config16(root, root_cap + PCI_EXP_LNKSTA); |
| 92 | root_scc &= PCI_EXP_LNKSTA_SLC; |
| 93 | |
| 94 | /* Get Slot Clock Configuration for endpoint */ |
| 95 | endp_scc = pci_read_config16(endp, endp_cap + PCI_EXP_LNKSTA); |
| 96 | endp_scc &= PCI_EXP_LNKSTA_SLC; |
| 97 | |
| 98 | /* Enable Common Clock Configuration and retrain */ |
| 99 | if (root_scc && endp_scc) { |
| 100 | printk(BIOS_INFO, "Enabling Common Clock Configuration\n"); |
| 101 | |
| 102 | /* Set in endpoint */ |
| 103 | lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL); |
| 104 | lnkctl |= PCI_EXP_LNKCTL_CCC; |
| 105 | pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); |
| 106 | |
| 107 | /* Set in root port */ |
| 108 | lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL); |
| 109 | lnkctl |= PCI_EXP_LNKCTL_CCC; |
| 110 | pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl); |
| 111 | |
| 112 | /* Retrain link if CCC was enabled */ |
| 113 | pciexp_retrain_link(root, root_cap); |
| 114 | } |
| 115 | } |
| 116 | #endif /* CONFIG_PCIEXP_COMMON_CLOCK */ |
| 117 | |
Kane Chen | 18cb134 | 2014-10-01 11:13:54 +0800 | [diff] [blame] | 118 | #if CONFIG_PCIEXP_CLK_PM |
| 119 | static void pciexp_enable_clock_power_pm(device_t endp, unsigned endp_cap) |
| 120 | { |
| 121 | /* check if per port clk req is supported in device */ |
| 122 | u32 endp_ca; |
| 123 | u16 lnkctl; |
| 124 | endp_ca = pci_read_config32(endp, endp_cap + PCI_EXP_LNKCAP); |
| 125 | if ((endp_ca & PCI_EXP_CLK_PM) == 0) { |
| 126 | printk(BIOS_INFO, "PCIE CLK PM is not supported by endpoint"); |
| 127 | return; |
| 128 | } |
| 129 | lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL); |
| 130 | lnkctl = lnkctl | PCI_EXP_EN_CLK_PM; |
| 131 | pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); |
| 132 | } |
| 133 | #endif /* CONFIG_PCIEXP_CLK_PM */ |
| 134 | |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 135 | #if IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE) && IS_ENABLED(CONFIG_MMCONF_SUPPORT) |
| 136 | static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) |
| 137 | { |
| 138 | u32 reg32; |
| 139 | |
| 140 | reg32 = pci_mmio_read_config32(dev, reg); |
| 141 | reg32 &= mask; |
| 142 | reg32 |= or; |
| 143 | pci_mmio_write_config32(dev, reg, reg32); |
| 144 | } |
| 145 | |
| 146 | static void pciexp_config_max_latency(device_t root, device_t dev) |
| 147 | { |
| 148 | unsigned int cap; |
| 149 | cap = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_LTR_ID); |
| 150 | if (root->ops->ops_pci->set_L1_ss_latency != NULL) |
| 151 | root->ops->ops_pci->set_L1_ss_latency(dev, cap + 4); |
| 152 | } |
| 153 | |
| 154 | static void pciexp_enable_ltr(device_t dev) |
| 155 | { |
| 156 | unsigned int cap; |
| 157 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); |
| 158 | |
| 159 | pcie_update_cfg(dev, cap + 0x28, ~(1 << 10), 1 << 10); |
| 160 | } |
| 161 | |
| 162 | static unsigned char pciexp_L1_substate_cal(device_t dev, unsigned int endp_cap, |
| 163 | unsigned int *data) |
| 164 | { |
| 165 | unsigned char mult[4] = {2, 10, 100, 0}; |
| 166 | |
| 167 | unsigned int L1SubStateSupport = *data & 0xf; |
| 168 | unsigned int comm_mode_rst_time = (*data >> 8) & 0xff; |
| 169 | unsigned int power_on_scale = (*data >> 16) & 0x3; |
| 170 | unsigned int power_on_value = (*data >> 19) & 0x1f; |
| 171 | |
| 172 | unsigned int endp_data = pci_mmio_read_config32(dev, endp_cap + 4); |
| 173 | unsigned int endp_L1SubStateSupport = endp_data & 0xf; |
| 174 | unsigned int endp_comm_mode_restore_time = (endp_data >> 8) & 0xff; |
| 175 | unsigned int endp_power_on_scale = (endp_data >> 16) & 0x3; |
| 176 | unsigned int endp_power_on_value = (endp_data >> 19) & 0x1f; |
| 177 | |
| 178 | L1SubStateSupport &= endp_L1SubStateSupport; |
| 179 | |
| 180 | if (L1SubStateSupport == 0) |
| 181 | return 0; |
| 182 | |
| 183 | if (power_on_value * mult[power_on_scale] < |
| 184 | endp_power_on_value * mult[endp_power_on_scale]) { |
| 185 | power_on_value = endp_power_on_value; |
| 186 | power_on_scale = endp_power_on_scale; |
| 187 | } |
| 188 | if (comm_mode_rst_time < endp_comm_mode_restore_time) |
| 189 | comm_mode_rst_time = endp_comm_mode_restore_time; |
| 190 | |
| 191 | *data = (comm_mode_rst_time << 8) | (power_on_scale << 16) |
| 192 | | (power_on_value << 19) | L1SubStateSupport; |
| 193 | |
| 194 | return 1; |
| 195 | } |
| 196 | |
| 197 | static void pciexp_L1_substate_commit(device_t root, device_t dev, |
| 198 | unsigned int root_cap, unsigned int end_cap) |
| 199 | { |
| 200 | device_t dev_t; |
| 201 | unsigned char L1_ss_ok; |
| 202 | unsigned int rp_L1_support = pci_mmio_read_config32(root, root_cap + 4); |
| 203 | unsigned int L1SubStateSupport; |
| 204 | unsigned int comm_mode_rst_time; |
| 205 | unsigned int power_on_scale; |
| 206 | unsigned int endp_power_on_value; |
| 207 | |
| 208 | for (dev_t = dev; dev_t; dev_t = dev_t->sibling) { |
| 209 | /* |
| 210 | * rp_L1_support is init'd above from root port. |
| 211 | * it needs coordination with endpoints to reach in common. |
| 212 | * if certain endpoint doesn't support L1 Sub-State, abort |
| 213 | * this feature enabling. |
| 214 | */ |
| 215 | L1_ss_ok = pciexp_L1_substate_cal(dev_t, end_cap, |
| 216 | &rp_L1_support); |
| 217 | if (!L1_ss_ok) |
| 218 | return; |
| 219 | } |
| 220 | |
| 221 | L1SubStateSupport = rp_L1_support & 0xf; |
| 222 | comm_mode_rst_time = (rp_L1_support >> 8) & 0xff; |
| 223 | power_on_scale = (rp_L1_support >> 16) & 0x3; |
| 224 | endp_power_on_value = (rp_L1_support >> 19) & 0x1f; |
| 225 | |
| 226 | printk(BIOS_INFO, "L1 Sub-State supported from root port %d\n", |
| 227 | root->path.pci.devfn >> 3); |
| 228 | printk(BIOS_INFO, "L1 Sub-State Support = 0x%x\n", L1SubStateSupport); |
| 229 | printk(BIOS_INFO, "CommonModeRestoreTime = 0x%x\n", comm_mode_rst_time); |
| 230 | printk(BIOS_INFO, "Power On Value = 0x%x, Power On Scale = 0x%x\n", |
| 231 | endp_power_on_value, power_on_scale); |
| 232 | |
| 233 | pciexp_enable_ltr(root); |
| 234 | |
| 235 | pcie_update_cfg(root, root_cap + 0x08, ~0xff00, |
| 236 | (comm_mode_rst_time << 8)); |
| 237 | |
| 238 | pcie_update_cfg(root, root_cap + 0x0c , 0xffffff04, |
| 239 | (endp_power_on_value << 3) | (power_on_scale)); |
| 240 | |
| 241 | pcie_update_cfg(root, root_cap + 0x08, ~0xe3ff0000, |
| 242 | (1 << 21) | (1 << 23) | (1 << 30)); |
| 243 | |
Kenji Chen | a874a7c | 2015-01-30 13:57:42 +0800 | [diff] [blame] | 244 | pcie_update_cfg(root, root_cap + 0x08, ~0x1f, |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 245 | L1SubStateSupport); |
| 246 | |
| 247 | for (dev_t = dev; dev_t; dev_t = dev_t->sibling) { |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 248 | pcie_update_cfg(dev_t, end_cap + 0x0c , 0xffffff04, |
| 249 | (endp_power_on_value << 3) | (power_on_scale)); |
| 250 | |
| 251 | pcie_update_cfg(dev_t, end_cap + 0x08, ~0xe3ff0000, |
| 252 | (1 << 21) | (1 << 23) | (1 << 30)); |
| 253 | |
Kenji Chen | a874a7c | 2015-01-30 13:57:42 +0800 | [diff] [blame] | 254 | pcie_update_cfg(dev_t, end_cap + 0x08, ~0x1f, |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 255 | L1SubStateSupport); |
| 256 | |
| 257 | pciexp_enable_ltr(dev_t); |
| 258 | |
| 259 | pciexp_config_max_latency(root, dev_t); |
| 260 | } |
| 261 | } |
| 262 | |
| 263 | static void pciexp_config_L1_sub_state(device_t root, device_t dev) |
| 264 | { |
| 265 | unsigned int root_cap, end_cap; |
| 266 | |
| 267 | /* Do it for function 0 only */ |
| 268 | if (dev->path.pci.devfn & 0x7) |
| 269 | return; |
| 270 | |
| 271 | root_cap = pciexp_find_extended_cap(root, PCIE_EXT_CAP_L1SS_ID); |
| 272 | if (!root_cap) |
| 273 | return; |
| 274 | |
| 275 | end_cap = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_L1SS_ID); |
| 276 | if (!end_cap) { |
| 277 | end_cap = pciexp_find_extended_cap(dev, 0xcafe); |
| 278 | if (!end_cap) |
| 279 | return; |
| 280 | } |
| 281 | |
| 282 | pciexp_L1_substate_commit(root, dev, root_cap, end_cap); |
| 283 | } |
| 284 | #endif /* CONFIG_PCIEXP_L1_SUB_STATE */ |
| 285 | |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 286 | #if CONFIG_PCIEXP_ASPM |
| 287 | /* |
| 288 | * Determine the ASPM L0s or L1 exit latency for a link |
| 289 | * by checking both root port and endpoint and returning |
| 290 | * the highest latency value. |
| 291 | */ |
| 292 | static int pciexp_aspm_latency(device_t root, unsigned root_cap, |
| 293 | device_t endp, unsigned endp_cap, |
| 294 | enum aspm_type type) |
| 295 | { |
| 296 | int root_lat = 0, endp_lat = 0; |
| 297 | u32 root_lnkcap, endp_lnkcap; |
| 298 | |
| 299 | root_lnkcap = pci_read_config32(root, root_cap + PCI_EXP_LNKCAP); |
| 300 | endp_lnkcap = pci_read_config32(endp, endp_cap + PCI_EXP_LNKCAP); |
| 301 | |
| 302 | /* Make sure the link supports this ASPM type by checking |
| 303 | * capability bits 11:10 with aspm_type offset by 1 */ |
| 304 | if (!(root_lnkcap & (1 << (type + 9))) || |
| 305 | !(endp_lnkcap & (1 << (type + 9)))) |
| 306 | return -1; |
| 307 | |
| 308 | /* Find the one with higher latency */ |
| 309 | switch (type) { |
| 310 | case PCIE_ASPM_L0S: |
| 311 | root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12; |
| 312 | endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12; |
| 313 | break; |
| 314 | case PCIE_ASPM_L1: |
| 315 | root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15; |
| 316 | endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15; |
| 317 | break; |
| 318 | default: |
| 319 | return -1; |
| 320 | } |
| 321 | |
| 322 | return (endp_lat > root_lat) ? endp_lat : root_lat; |
| 323 | } |
| 324 | |
| 325 | /* |
| 326 | * Enable ASPM on PCIe root port and endpoint. |
| 327 | * |
| 328 | * Returns APMC value: |
| 329 | * -1 = Error |
| 330 | * 0 = no ASPM |
| 331 | * 1 = L0s Enabled |
| 332 | * 2 = L1 Enabled |
| 333 | * 3 = L0s and L1 Enabled |
| 334 | */ |
| 335 | static enum aspm_type pciexp_enable_aspm(device_t root, unsigned root_cap, |
| 336 | device_t endp, unsigned endp_cap) |
| 337 | { |
| 338 | const char *aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" }; |
| 339 | enum aspm_type apmc = PCIE_ASPM_NONE; |
| 340 | int exit_latency, ok_latency; |
| 341 | u16 lnkctl; |
| 342 | u32 devcap; |
| 343 | |
| 344 | /* Get endpoint device capabilities for acceptable limits */ |
| 345 | devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP); |
| 346 | |
| 347 | /* Enable L0s if it is within endpoint acceptable limit */ |
| 348 | ok_latency = (devcap & PCI_EXP_DEVCAP_L0S) >> 6; |
| 349 | exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap, |
| 350 | PCIE_ASPM_L0S); |
| 351 | if (exit_latency >= 0 && exit_latency <= ok_latency) |
| 352 | apmc |= PCIE_ASPM_L0S; |
| 353 | |
| 354 | /* Enable L1 if it is within endpoint acceptable limit */ |
| 355 | ok_latency = (devcap & PCI_EXP_DEVCAP_L1) >> 9; |
| 356 | exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap, |
| 357 | PCIE_ASPM_L1); |
| 358 | if (exit_latency >= 0 && exit_latency <= ok_latency) |
| 359 | apmc |= PCIE_ASPM_L1; |
| 360 | |
| 361 | if (apmc != PCIE_ASPM_NONE) { |
| 362 | /* Set APMC in root port first */ |
| 363 | lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL); |
| 364 | lnkctl |= apmc; |
| 365 | pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl); |
| 366 | |
| 367 | /* Set APMC in endpoint device next */ |
| 368 | lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL); |
| 369 | lnkctl |= apmc; |
| 370 | pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); |
| 371 | } |
| 372 | |
| 373 | printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]); |
| 374 | return apmc; |
| 375 | } |
| 376 | #endif /* CONFIG_PCIEXP_ASPM */ |
| 377 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 378 | static void pciexp_tune_dev(device_t dev) |
| 379 | { |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 380 | device_t root = dev->bus->dev; |
| 381 | unsigned int root_cap, cap; |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 382 | |
| 383 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 384 | if (!cap) |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 385 | return; |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 386 | |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 387 | root_cap = pci_find_capability(root, PCI_CAP_ID_PCIE); |
| 388 | if (!root_cap) |
| 389 | return; |
Stefan Reinauer | f6eb88a | 2010-01-17 13:54:08 +0000 | [diff] [blame] | 390 | |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 391 | #if CONFIG_PCIEXP_COMMON_CLOCK |
| 392 | /* Check for and enable Common Clock */ |
| 393 | pciexp_enable_common_clock(root, root_cap, dev, cap); |
| 394 | #endif |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 395 | |
Kane Chen | 18cb134 | 2014-10-01 11:13:54 +0800 | [diff] [blame] | 396 | #if CONFIG_PCIEXP_CLK_PM |
| 397 | /* Check if per port CLK req is supported by endpoint*/ |
| 398 | pciexp_enable_clock_power_pm(dev, cap); |
| 399 | #endif |
| 400 | |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 401 | #if CONFIG_PCIEXP_L1_SUB_STATE |
| 402 | /* Enable L1 Sub-State when both root port and endpoint support */ |
| 403 | pciexp_config_L1_sub_state(root, dev); |
| 404 | #endif /* CONFIG_PCIEXP_L1_SUB_STATE */ |
| 405 | |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 406 | #if CONFIG_PCIEXP_ASPM |
| 407 | /* Check for and enable ASPM */ |
| 408 | enum aspm_type apmc = pciexp_enable_aspm(root, root_cap, dev, cap); |
| 409 | |
| 410 | if (apmc != PCIE_ASPM_NONE) { |
| 411 | /* Enable ASPM role based error reporting. */ |
| 412 | u32 reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP); |
| 413 | reg32 |= PCI_EXP_DEVCAP_RBER; |
| 414 | pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32); |
| 415 | } |
Stefan Reinauer | f6eb88a | 2010-01-17 13:54:08 +0000 | [diff] [blame] | 416 | #endif |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 417 | } |
| 418 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 419 | unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, |
| 420 | unsigned int max_devfn, unsigned int max) |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 421 | { |
| 422 | device_t child; |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 423 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 424 | max = pci_scan_bus(bus, min_devfn, max_devfn, max); |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 425 | |
| 426 | for (child = bus->children; child; child = child->sibling) { |
| 427 | if ((child->path.pci.devfn < min_devfn) || |
| 428 | (child->path.pci.devfn > max_devfn)) { |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 429 | continue; |
| 430 | } |
| 431 | pciexp_tune_dev(child); |
| 432 | } |
| 433 | return max; |
| 434 | } |
| 435 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 436 | unsigned int pciexp_scan_bridge(device_t dev, unsigned int max) |
| 437 | { |
| 438 | return do_pci_scan_bridge(dev, max, pciexp_scan_bus); |
| 439 | } |
| 440 | |
| 441 | /** Default device operations for PCI Express bridges */ |
| 442 | static struct pci_operations pciexp_bus_ops_pci = { |
| 443 | .set_subsystem = 0, |
| 444 | }; |
| 445 | |
| 446 | struct device_operations default_pciexp_ops_bus = { |
| 447 | .read_resources = pci_bus_read_resources, |
| 448 | .set_resources = pci_dev_set_resources, |
| 449 | .enable_resources = pci_bus_enable_resources, |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 450 | .init = 0, |
| 451 | .scan_bus = pciexp_scan_bridge, |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 452 | .enable = 0, |
| 453 | .reset_bus = pci_bus_reset, |
| 454 | .ops_pci = &pciexp_bus_ops_pci, |
| 455 | }; |