blob: c68c70bd311ffb1e5be622b23e7847c755f4113d [file] [log] [blame]
Patrick Georgiac959032020-05-05 22:49:26 +02001/* SPDX-License-Identifier: GPL-2.0-or-later */
Damien Zammit4b513a62015-08-20 00:37:05 +10002
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +02003#include <device/pci_ops.h>
Kyösti Mälkki1a1b04e2020-01-07 22:34:33 +02004#include <device/smbus_host.h>
Damien Zammit4b513a62015-08-20 00:37:05 +10005#include <cbmem.h>
Elyes HAOUASb559b3c2019-04-28 17:52:10 +02006#include <cf9_reset.h>
Damien Zammit4b513a62015-08-20 00:37:05 +10007#include <console/console.h>
Elyes HAOUASd2b9ec12018-10-27 09:41:02 +02008#include <arch/cpu.h>
Damien Zammit4b513a62015-08-20 00:37:05 +10009#include <spd.h>
10#include <string.h>
Arthur Heymans3cf94032017-04-05 16:17:26 +020011#include <device/dram/ddr2.h>
Arthur Heymans1848ba32017-04-11 17:09:31 +020012#include <device/dram/ddr3.h>
Arthur Heymansadc571a2017-09-25 09:40:54 +020013#include <mrc_cache.h>
Elyes HAOUASf5a57a82019-01-08 22:15:53 +010014#include <timestamp.h>
Elyes HAOUAS51401c32019-05-15 21:09:30 +020015#include <types.h>
Arthur Heymansadc571a2017-09-25 09:40:54 +020016
Elyes HAOUASbf0970e2019-03-21 11:10:03 +010017#include "iomap.h"
18#include "x4x.h"
19
Arthur Heymansadc571a2017-09-25 09:40:54 +020020#define MRC_CACHE_VERSION 0
Damien Zammit4b513a62015-08-20 00:37:05 +100021
Arthur Heymans1848ba32017-04-11 17:09:31 +020022static u16 ddr2_get_crc(u8 device, u8 len)
23{
24 u8 raw_spd[128] = {};
Kyösti Mälkkic01a5052019-01-30 09:39:23 +020025 i2c_eeprom_read(device, 64, 9, &raw_spd[64]);
26 i2c_eeprom_read(device, 93, 6, &raw_spd[93]);
Arthur Heymans1848ba32017-04-11 17:09:31 +020027 return spd_ddr2_calc_unique_crc(raw_spd, len);
28}
29
30static u16 ddr3_get_crc(u8 device, u8 len)
31{
32 u8 raw_spd[256] = {};
Kyösti Mälkkic01a5052019-01-30 09:39:23 +020033 i2c_eeprom_read(device, 117, 11, &raw_spd[117]);
Arthur Heymans1848ba32017-04-11 17:09:31 +020034 return spd_ddr3_calc_unique_crc(raw_spd, len);
35}
36
Arthur Heymansadc571a2017-09-25 09:40:54 +020037static enum cb_err verify_spds(const u8 *spd_map,
38 const struct sysinfo *ctrl_cached)
39{
40 int i;
Arthur Heymansadc571a2017-09-25 09:40:54 +020041 u16 crc;
42
43 for (i = 0; i < TOTAL_DIMMS; i++) {
44 if (!(spd_map[i]))
45 continue;
46 int len = smbus_read_byte(spd_map[i], 0);
47 if (len < 0 && ctrl_cached->dimms[i].card_type
48 == RAW_CARD_UNPOPULATED)
49 continue;
50 if (len > 0 && ctrl_cached->dimms[i].card_type
51 == RAW_CARD_UNPOPULATED)
52 return CB_ERR;
53
Arthur Heymans1848ba32017-04-11 17:09:31 +020054 if (ctrl_cached->spd_type == DDR2)
55 crc = ddr2_get_crc(spd_map[i], len);
56 else
57 crc = ddr3_get_crc(spd_map[i], len);
58
Arthur Heymansadc571a2017-09-25 09:40:54 +020059 if (crc != ctrl_cached->dimms[i].spd_crc)
60 return CB_ERR;
61 }
62 return CB_SUCCESS;
63}
64
Arthur Heymans3cf94032017-04-05 16:17:26 +020065struct abs_timings {
66 u32 min_tclk;
67 u32 min_tRAS;
68 u32 min_tRP;
69 u32 min_tRCD;
70 u32 min_tWR;
71 u32 min_tRFC;
72 u32 min_tWTR;
73 u32 min_tRRD;
74 u32 min_tRTP;
Arthur Heymans1848ba32017-04-11 17:09:31 +020075 u32 min_tAA;
Arthur Heymans3cf94032017-04-05 16:17:26 +020076 u32 min_tCLK_cas[8];
77 u32 cas_supported;
78};
79
80#define CTRL_MIN_TCLK_DDR2 TCK_400MHZ
81
82static void select_cas_dramfreq_ddr2(struct sysinfo *s,
83 const struct abs_timings *saved_timings)
Damien Zammit4b513a62015-08-20 00:37:05 +100084{
Arthur Heymans3cf94032017-04-05 16:17:26 +020085 u8 try_cas;
86 /* Currently only these CAS are supported */
87 u8 cas_mask = SPD_CAS_LATENCY_DDR2_5 | SPD_CAS_LATENCY_DDR2_6;
Arthur Heymanscfa2eaa2017-03-20 16:32:07 +010088
Arthur Heymans3cf94032017-04-05 16:17:26 +020089 cas_mask &= saved_timings->cas_supported;
90 try_cas = spd_get_msbs(cas_mask);
Damien Zammit4b513a62015-08-20 00:37:05 +100091
Arthur Heymans3cf94032017-04-05 16:17:26 +020092 while (cas_mask & (1 << try_cas) && try_cas > 0) {
93 s->selected_timings.CAS = try_cas;
94 s->selected_timings.tclk = saved_timings->min_tCLK_cas[try_cas];
95 if (s->selected_timings.tclk >= CTRL_MIN_TCLK_DDR2 &&
96 saved_timings->min_tCLK_cas[try_cas] !=
97 saved_timings->min_tCLK_cas[try_cas - 1])
Arthur Heymans70a1dda2017-03-09 01:58:24 +010098 break;
Arthur Heymans3cf94032017-04-05 16:17:26 +020099 try_cas--;
Damien Zammit4b513a62015-08-20 00:37:05 +1000100 }
Damien Zammit4b513a62015-08-20 00:37:05 +1000101
Arthur Heymans3cf94032017-04-05 16:17:26 +0200102 if ((s->selected_timings.CAS < 3) || (s->selected_timings.tclk == 0))
103 die("Could not find common memory frequency and CAS\n");
104
105 switch (s->selected_timings.tclk) {
106 case TCK_200MHZ:
107 case TCK_266MHZ:
108 /* FIXME: this works on vendor BIOS */
109 die("Selected dram frequency not supported\n");
110 case TCK_333MHZ:
111 s->selected_timings.mem_clk = MEM_CLOCK_667MHz;
112 break;
113 case TCK_400MHZ:
114 s->selected_timings.mem_clk = MEM_CLOCK_800MHz;
115 break;
Damien Zammit4b513a62015-08-20 00:37:05 +1000116 }
Damien Zammit4b513a62015-08-20 00:37:05 +1000117}
118
119static void mchinfo_ddr2(struct sysinfo *s)
120{
121 const u32 eax = cpuid_ext(0x04, 0).eax;
Arthur Heymans3cf94032017-04-05 16:17:26 +0200122 printk(BIOS_WARNING, "%d CPU cores\n", ((eax >> 26) & 0x3f) + 1);
Damien Zammit4b513a62015-08-20 00:37:05 +1000123
Angel Ponsd1c590a2020-08-03 16:01:39 +0200124 u32 capid = pci_read_config16(HOST_BRIDGE, 0xe8);
Arthur Heymans70a1dda2017-03-09 01:58:24 +0100125 if (!(capid & (1<<(79-64))))
Damien Zammit4b513a62015-08-20 00:37:05 +1000126 printk(BIOS_WARNING, "iTPM enabled\n");
Damien Zammit4b513a62015-08-20 00:37:05 +1000127
Angel Ponsd1c590a2020-08-03 16:01:39 +0200128 capid = pci_read_config32(HOST_BRIDGE, 0xe4);
Arthur Heymans70a1dda2017-03-09 01:58:24 +0100129 if (!(capid & (1<<(57-32))))
Damien Zammit4b513a62015-08-20 00:37:05 +1000130 printk(BIOS_WARNING, "ME enabled\n");
Damien Zammit4b513a62015-08-20 00:37:05 +1000131
Arthur Heymans70a1dda2017-03-09 01:58:24 +0100132 if (!(capid & (1<<(56-32))))
Damien Zammit4b513a62015-08-20 00:37:05 +1000133 printk(BIOS_WARNING, "AMT enabled\n");
Damien Zammit4b513a62015-08-20 00:37:05 +1000134
Arthur Heymans70a1dda2017-03-09 01:58:24 +0100135 if (!(capid & (1<<(48-32))))
Damien Zammit4b513a62015-08-20 00:37:05 +1000136 printk(BIOS_WARNING, "VT-d enabled\n");
Damien Zammit4b513a62015-08-20 00:37:05 +1000137}
138
Arthur Heymans3cf94032017-04-05 16:17:26 +0200139static int ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd,
140 struct abs_timings *saved_timings, struct sysinfo *s)
Damien Zammit4b513a62015-08-20 00:37:05 +1000141{
Arthur Heymansfc31e442018-02-12 15:12:34 +0100142 struct dimm_attr_ddr2_st decoded_dimm;
Arthur Heymans3cf94032017-04-05 16:17:26 +0200143 int i;
Damien Zammit4b513a62015-08-20 00:37:05 +1000144
Arthur Heymans3cf94032017-04-05 16:17:26 +0200145 if (spd_decode_ddr2(&decoded_dimm, raw_spd) != SPD_STATUS_OK) {
146 printk(BIOS_DEBUG, "Problems decoding SPD\n");
147 return CB_ERR;
148 }
Damien Zammit7c2e5392016-07-24 03:28:42 +1000149
Julius Wernercd49cce2019-03-05 16:53:33 -0800150 if (CONFIG(DEBUG_RAM_SETUP))
Arthur Heymans3cf94032017-04-05 16:17:26 +0200151 dram_print_spd_ddr2(&decoded_dimm);
152
153 if (!(decoded_dimm.width & (0x08 | 0x10))) {
154
155 printk(BIOS_ERR,
156 "DIMM%d Unsupported width: x%d. Disabling dimm\n",
157 dimm_idx, s->dimms[dimm_idx].width);
158 return CB_ERR;
159 }
160 s->dimms[dimm_idx].width = (decoded_dimm.width >> 3) - 1;
161 /*
162 * This boils down to:
163 * "Except for the x16 configuration, all DDR2 devices have a
164 * 1KB page size. For the x16 configuration, the page size is 2KB
165 * for all densities except the 256Mb device, which has a 1KB page
166 * size." Micron, 'TN-47-16 Designing for High-Density DDR2 Memory'
Arthur Heymansd4e57622017-12-25 17:01:33 +0100167 * The formula is pagesize in KiB = width * 2^col_bits / 8.
Arthur Heymans3cf94032017-04-05 16:17:26 +0200168 */
Arthur Heymansd4e57622017-12-25 17:01:33 +0100169 s->dimms[dimm_idx].page_size = decoded_dimm.width *
170 (1 << decoded_dimm.col_bits) / 8;
Arthur Heymans3cf94032017-04-05 16:17:26 +0200171
172 switch (decoded_dimm.banks) {
173 case 4:
174 s->dimms[dimm_idx].n_banks = N_BANKS_4;
175 break;
176 case 8:
177 s->dimms[dimm_idx].n_banks = N_BANKS_8;
178 break;
179 default:
180 printk(BIOS_ERR,
181 "DIMM%d Unsupported #banks: x%d. Disabling dimm\n",
182 dimm_idx, decoded_dimm.banks);
183 return CB_ERR;
184 }
185
186 s->dimms[dimm_idx].ranks = decoded_dimm.ranks;
187 s->dimms[dimm_idx].rows = decoded_dimm.row_bits;
188 s->dimms[dimm_idx].cols = decoded_dimm.col_bits;
189
190 saved_timings->cas_supported &= decoded_dimm.cas_supported;
191
192 saved_timings->min_tRAS =
193 MAX(saved_timings->min_tRAS, decoded_dimm.tRAS);
194 saved_timings->min_tRP =
195 MAX(saved_timings->min_tRP, decoded_dimm.tRP);
196 saved_timings->min_tRCD =
197 MAX(saved_timings->min_tRCD, decoded_dimm.tRCD);
198 saved_timings->min_tWR =
199 MAX(saved_timings->min_tWR, decoded_dimm.tWR);
200 saved_timings->min_tRFC =
201 MAX(saved_timings->min_tRFC, decoded_dimm.tRFC);
202 saved_timings->min_tWTR =
203 MAX(saved_timings->min_tWTR, decoded_dimm.tWTR);
204 saved_timings->min_tRRD =
205 MAX(saved_timings->min_tRRD, decoded_dimm.tRRD);
206 saved_timings->min_tRTP =
207 MAX(saved_timings->min_tRTP, decoded_dimm.tRTP);
208 for (i = 0; i < 8; i++) {
209 if (!(saved_timings->cas_supported & (1 << i)))
210 saved_timings->min_tCLK_cas[i] = 0;
211 else
212 saved_timings->min_tCLK_cas[i] =
213 MAX(saved_timings->min_tCLK_cas[i],
214 decoded_dimm.cycle_time[i]);
215 }
Arthur Heymansadc571a2017-09-25 09:40:54 +0200216
217 s->dimms[dimm_idx].spd_crc = spd_ddr2_calc_unique_crc(raw_spd,
218 spd_decode_spd_size_ddr2(raw_spd[0]));
Arthur Heymans3cf94032017-04-05 16:17:26 +0200219 return CB_SUCCESS;
220}
221
Arthur Heymans1848ba32017-04-11 17:09:31 +0200222static void normalize_tCLK(u32 *tCLK)
223{
224 if (*tCLK <= TCK_666MHZ)
225 *tCLK = TCK_666MHZ;
226 else if (*tCLK <= TCK_533MHZ)
227 *tCLK = TCK_533MHZ;
228 else if (*tCLK <= TCK_400MHZ)
229 *tCLK = TCK_400MHZ;
230 else
231 *tCLK = 0;
232}
233
234static void select_cas_dramfreq_ddr3(struct sysinfo *s,
235 struct abs_timings *saved_timings)
236{
237 /*
238 * various constraints must be fulfilled:
239 * CAS * tCK < 20ns == 160MTB
240 * tCK_max >= tCK >= tCK_min
241 * CAS >= roundup(tAA_min/tCK)
242 * CAS supported
243 * AND BTW: Clock(MT) = 2000 / tCK(ns) - intel uses MTs but calls them MHz
244 */
245
246 u32 min_tCLK;
247 u8 try_CAS;
Angel Ponsd1c590a2020-08-03 16:01:39 +0200248 u16 capid = (pci_read_config16(HOST_BRIDGE, 0xea) >> 4) & 0x3f;
Arthur Heymans1848ba32017-04-11 17:09:31 +0200249
250 switch (s->max_fsb) {
251 default:
252 case FSB_CLOCK_800MHz:
253 min_tCLK = TCK_400MHZ;
254 break;
255 case FSB_CLOCK_1066MHz:
256 min_tCLK = TCK_533MHZ;
257 break;
258 case FSB_CLOCK_1333MHz:
259 min_tCLK = TCK_666MHZ;
260 break;
261 }
262
263 switch (capid >> 3) {
264 default: /* Should not happen */
265 min_tCLK = TCK_400MHZ;
266 break;
267 case 1:
268 min_tCLK = MAX(min_tCLK, TCK_400MHZ);
269 break;
270 case 2:
271 min_tCLK = MAX(min_tCLK, TCK_533MHZ);
272 break;
273 case 3: /* Only on P45 */
Arthur Heymansb1ba6622018-10-14 13:22:16 +0200274 case 0:
Arthur Heymans1848ba32017-04-11 17:09:31 +0200275 min_tCLK = MAX(min_tCLK, TCK_666MHZ);
276 break;
277 }
278
279 min_tCLK = MAX(min_tCLK, saved_timings->min_tclk);
280 if (min_tCLK == 0) {
281 printk(BIOS_ERR, "DRAM frequency is under lowest supported "
Jonathan Neuschäfer0f14df42018-10-30 10:50:47 +0100282 "frequency (400 MHz). Increasing to 400 MHz "
Arthur Heymans1848ba32017-04-11 17:09:31 +0200283 "as last resort");
284 min_tCLK = TCK_400MHZ;
285 }
286
287 while (1) {
288 normalize_tCLK(&min_tCLK);
289 if (min_tCLK == 0)
290 die("Couldn't find compatible clock / CAS settings.\n");
291 try_CAS = DIV_ROUND_UP(saved_timings->min_tAA, min_tCLK);
292 printk(BIOS_SPEW, "Trying CAS %u, tCK %u.\n", try_CAS, min_tCLK);
293 for (; try_CAS <= DDR3_MAX_CAS; try_CAS++) {
294 /*
295 * cas_supported is encoded like the SPD which starts
296 * at CAS=4.
297 */
298 if ((saved_timings->cas_supported << 4) & (1 << try_CAS))
299 break;
300 }
301 if ((try_CAS <= DDR3_MAX_CAS) && (try_CAS * min_tCLK < 20 * 256)) {
302 /* Found good CAS. */
303 printk(BIOS_SPEW, "Found compatible tCLK / CAS pair: %u / %u.\n",
304 min_tCLK, try_CAS);
305 break;
306 }
307 /*
308 * If no valid tCLK / CAS pair could be found for a tCLK
309 * increase it after which it gets normalised. This means
310 * that a lower frequency gets tried.
311 */
312 min_tCLK++;
313 }
314
315 s->selected_timings.tclk = min_tCLK;
316 s->selected_timings.CAS = try_CAS;
317
318 switch (s->selected_timings.tclk) {
319 case TCK_400MHZ:
320 s->selected_timings.mem_clk = MEM_CLOCK_800MHz;
321 break;
322 case TCK_533MHZ:
323 s->selected_timings.mem_clk = MEM_CLOCK_1066MHz;
324 break;
325 case TCK_666MHZ:
326 s->selected_timings.mem_clk = MEM_CLOCK_1333MHz;
327 break;
328 }
329}
330
Arthur Heymans5a9dbde2018-05-26 15:05:09 +0200331/* With DDR3 and 533MHz mem clock and an enabled internal gfx device the display
332 is not usable in non stacked mode, so select stacked mode accordingly */
333static void workaround_stacked_mode(struct sysinfo *s)
334{
335 u32 deven;
336 /* Only a problem on DDR3 */
337 if (s->spd_type == DDR2)
338 return;
339 /* Does not matter if only one channel is populated */
340 if (!CHANNEL_IS_POPULATED(s->dimms, 0)
341 || !CHANNEL_IS_POPULATED(s->dimms, 1))
342 return;
343 if (s->selected_timings.mem_clk != MEM_CLOCK_1066MHz)
344 return;
345 /* IGD0EN gets disabled if not present before this code runs */
Angel Ponsd1c590a2020-08-03 16:01:39 +0200346 deven = pci_read_config32(HOST_BRIDGE, D0F0_DEVEN);
Arthur Heymans5a9dbde2018-05-26 15:05:09 +0200347 if (deven & IGD0EN)
348 s->stacked_mode = 1;
349}
350
Arthur Heymans1848ba32017-04-11 17:09:31 +0200351static int ddr3_save_dimminfo(u8 dimm_idx, u8 *raw_spd,
352 struct abs_timings *saved_timings, struct sysinfo *s)
353{
354 struct dimm_attr_st decoded_dimm;
355
356 if (spd_decode_ddr3(&decoded_dimm, raw_spd) != SPD_STATUS_OK)
357 return CB_ERR;
358
Julius Wernercd49cce2019-03-05 16:53:33 -0800359 if (CONFIG(DEBUG_RAM_SETUP))
Arthur Heymans1848ba32017-04-11 17:09:31 +0200360 dram_print_spd_ddr3(&decoded_dimm);
361
362 /* x4 DIMMs are not supported (true for both ddr2 and ddr3) */
363 if (!(decoded_dimm.width & (0x8 | 0x10))) {
364 printk(BIOS_ERR, "DIMM%d Unsupported width: x%d. Disabling dimm\n",
365 dimm_idx, s->dimms[dimm_idx].width);
366 return CB_ERR;
367 }
368 s->dimms[dimm_idx].width = (decoded_dimm.width >> 3) - 1;
369 /*
370 * This boils down to:
371 * "Except for the x16 configuration, all DDR3 devices have a
372 * 1KB page size. For the x16 configuration, the page size is 2KB
373 * for all densities except the 256Mb device, which has a 1KB page size."
374 * Micron, 'TN-47-16 Designing for High-Density DDR2 Memory'
375 */
376 s->dimms[dimm_idx].page_size = decoded_dimm.width *
377 (1 << decoded_dimm.col_bits) / 8;
378
379 s->dimms[dimm_idx].n_banks = N_BANKS_8; /* Always 8 banks on ddr3?? */
380
381 s->dimms[dimm_idx].ranks = decoded_dimm.ranks;
382 s->dimms[dimm_idx].rows = decoded_dimm.row_bits;
383 s->dimms[dimm_idx].cols = decoded_dimm.col_bits;
384
385 saved_timings->min_tRAS =
386 MAX(saved_timings->min_tRAS, decoded_dimm.tRAS);
387 saved_timings->min_tRP =
388 MAX(saved_timings->min_tRP, decoded_dimm.tRP);
389 saved_timings->min_tRCD =
390 MAX(saved_timings->min_tRCD, decoded_dimm.tRCD);
391 saved_timings->min_tWR =
392 MAX(saved_timings->min_tWR, decoded_dimm.tWR);
393 saved_timings->min_tRFC =
394 MAX(saved_timings->min_tRFC, decoded_dimm.tRFC);
395 saved_timings->min_tWTR =
396 MAX(saved_timings->min_tWTR, decoded_dimm.tWTR);
397 saved_timings->min_tRRD =
398 MAX(saved_timings->min_tRRD, decoded_dimm.tRRD);
399 saved_timings->min_tRTP =
400 MAX(saved_timings->min_tRTP, decoded_dimm.tRTP);
401 saved_timings->min_tAA =
402 MAX(saved_timings->min_tAA, decoded_dimm.tAA);
403 saved_timings->cas_supported &= decoded_dimm.cas_supported;
404
405 s->dimms[dimm_idx].spd_crc = spd_ddr3_calc_unique_crc(raw_spd,
406 raw_spd[0]);
Arthur Heymansf1287262017-12-25 18:30:01 +0100407
408 s->dimms[dimm_idx].mirrored = decoded_dimm.flags.pins_mirrored;
409
Arthur Heymans1848ba32017-04-11 17:09:31 +0200410 return CB_SUCCESS;
411}
412
Arthur Heymans3cf94032017-04-05 16:17:26 +0200413static void select_discrete_timings(struct sysinfo *s,
414 const struct abs_timings *timings)
415{
416 s->selected_timings.tRAS = DIV_ROUND_UP(timings->min_tRAS,
417 s->selected_timings.tclk);
418 s->selected_timings.tRP = DIV_ROUND_UP(timings->min_tRP,
419 s->selected_timings.tclk);
420 s->selected_timings.tRCD = DIV_ROUND_UP(timings->min_tRCD,
421 s->selected_timings.tclk);
422 s->selected_timings.tWR = DIV_ROUND_UP(timings->min_tWR,
423 s->selected_timings.tclk);
424 s->selected_timings.tRFC = DIV_ROUND_UP(timings->min_tRFC,
425 s->selected_timings.tclk);
426 s->selected_timings.tWTR = DIV_ROUND_UP(timings->min_tWTR,
427 s->selected_timings.tclk);
428 s->selected_timings.tRRD = DIV_ROUND_UP(timings->min_tRRD,
429 s->selected_timings.tclk);
430 s->selected_timings.tRTP = DIV_ROUND_UP(timings->min_tRTP,
431 s->selected_timings.tclk);
432}
433static void print_selected_timings(struct sysinfo *s)
434{
435 printk(BIOS_DEBUG, "Selected timings:\n");
436 printk(BIOS_DEBUG, "\tFSB: %dMHz\n",
Elyes HAOUASe951e8e2019-06-15 11:03:00 +0200437 fsb_to_mhz(s->selected_timings.fsb_clk));
Arthur Heymans3cf94032017-04-05 16:17:26 +0200438 printk(BIOS_DEBUG, "\tDDR: %dMHz\n",
Elyes HAOUASe951e8e2019-06-15 11:03:00 +0200439 ddr_to_mhz(s->selected_timings.mem_clk));
Arthur Heymans3cf94032017-04-05 16:17:26 +0200440
441 printk(BIOS_DEBUG, "\tCAS: %d\n", s->selected_timings.CAS);
442 printk(BIOS_DEBUG, "\ttRAS: %d\n", s->selected_timings.tRAS);
443 printk(BIOS_DEBUG, "\ttRP: %d\n", s->selected_timings.tRP);
444 printk(BIOS_DEBUG, "\ttRCD: %d\n", s->selected_timings.tRCD);
445 printk(BIOS_DEBUG, "\ttWR: %d\n", s->selected_timings.tWR);
446 printk(BIOS_DEBUG, "\ttRFC: %d\n", s->selected_timings.tRFC);
447 printk(BIOS_DEBUG, "\ttWTR: %d\n", s->selected_timings.tWTR);
448 printk(BIOS_DEBUG, "\ttRRD: %d\n", s->selected_timings.tRRD);
449 printk(BIOS_DEBUG, "\ttRTP: %d\n", s->selected_timings.tRTP);
450}
451
452static void find_fsb_speed(struct sysinfo *s)
453{
Damien Zammit4b513a62015-08-20 00:37:05 +1000454 switch (MCHBAR32(0xc00) & 0x7) {
455 case 0x0:
456 s->max_fsb = FSB_CLOCK_1066MHz;
457 break;
458 case 0x2:
459 s->max_fsb = FSB_CLOCK_800MHz;
460 break;
461 case 0x4:
462 s->max_fsb = FSB_CLOCK_1333MHz;
463 break;
464 default:
465 s->max_fsb = FSB_CLOCK_800MHz;
466 printk(BIOS_WARNING, "Can't detect FSB, setting 800MHz\n");
467 break;
468 }
Arthur Heymans3cf94032017-04-05 16:17:26 +0200469 s->selected_timings.fsb_clk = s->max_fsb;
470}
Damien Zammit4b513a62015-08-20 00:37:05 +1000471
Arthur Heymans3cf94032017-04-05 16:17:26 +0200472static void decode_spd_select_timings(struct sysinfo *s)
473{
474 unsigned int device;
475 u8 dram_type_mask = (1 << DDR2) | (1 << DDR3);
476 u8 dimm_mask = 0;
477 u8 raw_spd[256];
478 int i, j;
479 struct abs_timings saved_timings;
480 memset(&saved_timings, 0, sizeof(saved_timings));
481 saved_timings.cas_supported = UINT32_MAX;
Damien Zammit4b513a62015-08-20 00:37:05 +1000482
Arthur Heymans3cf94032017-04-05 16:17:26 +0200483 FOR_EACH_DIMM(i) {
484 s->dimms[i].card_type = RAW_CARD_POPULATED;
485 device = s->spd_map[i];
486 if (!device) {
487 s->dimms[i].card_type = RAW_CARD_UNPOPULATED;
488 continue;
Damien Zammit4b513a62015-08-20 00:37:05 +1000489 }
Kyösti Mälkkibd659852020-01-05 20:00:18 +0200490 switch (smbus_read_byte(s->spd_map[i], SPD_MEMORY_TYPE)) {
Arthur Heymans3cf94032017-04-05 16:17:26 +0200491 case DDR2SPD:
492 dram_type_mask &= 1 << DDR2;
493 s->spd_type = DDR2;
Damien Zammit4b513a62015-08-20 00:37:05 +1000494 break;
Arthur Heymans3cf94032017-04-05 16:17:26 +0200495 case DDR3SPD:
496 dram_type_mask &= 1 << DDR3;
497 s->spd_type = DDR3;
Damien Zammit4b513a62015-08-20 00:37:05 +1000498 break;
499 default:
Arthur Heymans3cf94032017-04-05 16:17:26 +0200500 s->dimms[i].card_type = RAW_CARD_UNPOPULATED;
501 continue;
Damien Zammit4b513a62015-08-20 00:37:05 +1000502 }
Arthur Heymans3cf94032017-04-05 16:17:26 +0200503 if (!dram_type_mask)
504 die("Mixing up dimm types is not supported!\n");
Damien Zammit4b513a62015-08-20 00:37:05 +1000505
Arthur Heymans3cf94032017-04-05 16:17:26 +0200506 printk(BIOS_DEBUG, "Decoding dimm %d\n", i);
Kyösti Mälkkic01a5052019-01-30 09:39:23 +0200507 if (i2c_eeprom_read(device, 0, 128, raw_spd) != 128) {
Arthur Heymans1848ba32017-04-11 17:09:31 +0200508 printk(BIOS_DEBUG, "i2c block operation failed,"
509 " trying smbus byte operation.\n");
510 for (j = 0; j < 128; j++)
Kyösti Mälkkibd659852020-01-05 20:00:18 +0200511 raw_spd[j] = smbus_read_byte(device, j);
Arthur Heymans1848ba32017-04-11 17:09:31 +0200512 }
513
Arthur Heymans3cf94032017-04-05 16:17:26 +0200514 if (s->spd_type == DDR2){
Arthur Heymans3cf94032017-04-05 16:17:26 +0200515 if (ddr2_save_dimminfo(i, raw_spd, &saved_timings, s)) {
516 printk(BIOS_WARNING,
517 "Encountered problems with SPD, "
518 "skipping this DIMM.\n");
519 s->dimms[i].card_type = RAW_CARD_UNPOPULATED;
520 continue;
521 }
Arthur Heymans1848ba32017-04-11 17:09:31 +0200522 } else { /* DDR3 */
523 if (ddr3_save_dimminfo(i, raw_spd, &saved_timings, s)) {
524 printk(BIOS_WARNING,
525 "Encountered problems with SPD, "
526 "skipping this DIMM.\n");
527 /* something in decoded SPD was unsupported */
528 s->dimms[i].card_type = RAW_CARD_UNPOPULATED;
529 continue;
530 }
Arthur Heymans3cf94032017-04-05 16:17:26 +0200531 }
532 dimm_mask |= (1 << i);
Damien Zammit4b513a62015-08-20 00:37:05 +1000533 }
Arthur Heymans3cf94032017-04-05 16:17:26 +0200534 if (!dimm_mask)
535 die("No memory installed.\n");
536
537 if (s->spd_type == DDR2)
538 select_cas_dramfreq_ddr2(s, &saved_timings);
Arthur Heymans1848ba32017-04-11 17:09:31 +0200539 else
540 select_cas_dramfreq_ddr3(s, &saved_timings);
Arthur Heymans3cf94032017-04-05 16:17:26 +0200541 select_discrete_timings(s, &saved_timings);
Arthur Heymans5a9dbde2018-05-26 15:05:09 +0200542 workaround_stacked_mode(s);
Arthur Heymans3cf94032017-04-05 16:17:26 +0200543}
544
545static void find_dimm_config(struct sysinfo *s)
546{
547 int chan, i;
548
549 FOR_EACH_POPULATED_CHANNEL(s->dimms, chan) {
550 FOR_EACH_POPULATED_DIMM_IN_CHANNEL(s->dimms, chan, i) {
551 int dimm_config;
552 if (s->dimms[i].ranks == 1) {
553 if (s->dimms[i].width == 0) /* x8 */
554 dimm_config = 1;
555 else /* x16 */
556 dimm_config = 3;
557 } else {
558 if (s->dimms[i].width == 0) /* x8 */
559 dimm_config = 2;
560 else
561 die("Dual-rank x16 not supported\n");
562 }
563 s->dimm_config[chan] |=
564 dimm_config << (i % DIMMS_PER_CHANNEL) * 2;
565 }
566 printk(BIOS_DEBUG, " Config[CH%d] : %d\n", chan,
567 s->dimm_config[chan]);
568 }
569
Damien Zammit4b513a62015-08-20 00:37:05 +1000570}
571
Arthur Heymansbb5e77c2016-11-30 20:37:29 +0100572static void checkreset_ddr2(int boot_path)
573{
574 u8 pmcon2;
575 u32 pmsts;
576
577 if (boot_path >= 1) {
578 pmsts = MCHBAR32(PMSTS_MCHBAR);
579 if (!(pmsts & 1))
580 printk(BIOS_DEBUG,
581 "Channel 0 possibly not in self refresh\n");
582 if (!(pmsts & 2))
583 printk(BIOS_DEBUG,
584 "Channel 1 possibly not in self refresh\n");
585 }
586
587 pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
588
589 if (pmcon2 & 0x80) {
590 pmcon2 &= ~0x80;
591 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2);
592
593 /* do magic 0xf0 thing. */
Angel Ponsd1c590a2020-08-03 16:01:39 +0200594 pci_and_config8(HOST_BRIDGE, 0xf0, ~(1 << 2));
Angel Pons4a9569a2020-06-08 01:39:25 +0200595
Angel Ponsd1c590a2020-08-03 16:01:39 +0200596 pci_or_config8(HOST_BRIDGE, 0xf0, (1 << 2));
Arthur Heymansbb5e77c2016-11-30 20:37:29 +0100597
Elyes HAOUAS1bc7b6e2019-05-05 16:29:41 +0200598 full_reset();
Arthur Heymansbb5e77c2016-11-30 20:37:29 +0100599 }
600 pmcon2 |= 0x80;
601 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2);
602}
603
Damien Zammit4b513a62015-08-20 00:37:05 +1000604/**
605 * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3
606 */
607void sdram_initialize(int boot_path, const u8 *spd_map)
608{
Arthur Heymansadc571a2017-09-25 09:40:54 +0200609 struct sysinfo s, *ctrl_cached;
Damien Zammit4b513a62015-08-20 00:37:05 +1000610 u8 reg8;
Shelley Chenad9cd682020-07-23 16:10:52 -0700611 int fast_boot, cbmem_was_inited;
612 size_t mrc_size;
Damien Zammit4b513a62015-08-20 00:37:05 +1000613
Elyes HAOUASf5a57a82019-01-08 22:15:53 +0100614 timestamp_add_now(TS_BEFORE_INITRAM);
Damien Zammit4b513a62015-08-20 00:37:05 +1000615 printk(BIOS_DEBUG, "Setting up RAM controller.\n");
616
Angel Ponsd1c590a2020-08-03 16:01:39 +0200617 pci_write_config8(HOST_BRIDGE, 0xdf, 0xff);
Damien Zammit4b513a62015-08-20 00:37:05 +1000618
619 memset(&s, 0, sizeof(struct sysinfo));
620
Shelley Chenad9cd682020-07-23 16:10:52 -0700621 ctrl_cached = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
622 MRC_CACHE_VERSION,
623 &mrc_size);
Damien Zammit4b513a62015-08-20 00:37:05 +1000624
Shelley Chenad9cd682020-07-23 16:10:52 -0700625 if (!ctrl_cached || mrc_size < sizeof(s)) {
Arthur Heymansadc571a2017-09-25 09:40:54 +0200626 if (boot_path == BOOT_PATH_RESUME) {
627 /* Failed S3 resume, reset to come up cleanly */
Elyes HAOUASb559b3c2019-04-28 17:52:10 +0200628 system_reset();
Arthur Heymansdf946b82018-06-14 10:53:51 +0200629 } else if (boot_path == BOOT_PATH_WARM_RESET) {
630 /* On warm reset some of dram calibrations fail
631 and therefore requiring valid cached settings */
Elyes HAOUASb559b3c2019-04-28 17:52:10 +0200632 full_reset();
Arthur Heymansadc571a2017-09-25 09:40:54 +0200633 }
Arthur Heymansadc571a2017-09-25 09:40:54 +0200634 }
Arthur Heymansbb5e77c2016-11-30 20:37:29 +0100635
Arthur Heymansadc571a2017-09-25 09:40:54 +0200636 /* verify MRC cache for fast boot */
637 if (boot_path != BOOT_PATH_RESUME && ctrl_cached) {
638 /* check SPD checksum to make sure the DIMMs haven't been
639 * replaced */
640 fast_boot = verify_spds(spd_map, ctrl_cached) == CB_SUCCESS;
Arthur Heymansb0c6cff2018-09-05 20:39:39 +0200641 if (!fast_boot) {
Arthur Heymansadc571a2017-09-25 09:40:54 +0200642 printk(BIOS_DEBUG, "SPD checksums don't match,"
643 " dimm's have been replaced\n");
Arthur Heymansb0c6cff2018-09-05 20:39:39 +0200644 } else {
645 find_fsb_speed(&s);
646 fast_boot = s.max_fsb == ctrl_cached->max_fsb;
647 if (!fast_boot)
648 printk(BIOS_DEBUG,
649 "CPU FSB does not match and has been replaced\n");
650 }
Arthur Heymansadc571a2017-09-25 09:40:54 +0200651 } else {
652 fast_boot = boot_path == BOOT_PATH_RESUME;
653 }
Damien Zammit4b513a62015-08-20 00:37:05 +1000654
Arthur Heymansadc571a2017-09-25 09:40:54 +0200655 if (fast_boot) {
656 printk(BIOS_DEBUG, "Using cached raminit settings\n");
657 memcpy(&s, ctrl_cached, sizeof(s));
658 s.boot_path = boot_path;
659 mchinfo_ddr2(&s);
660 print_selected_timings(&s);
661 } else {
662 s.boot_path = boot_path;
663 s.spd_map[0] = spd_map[0];
664 s.spd_map[1] = spd_map[1];
665 s.spd_map[2] = spd_map[2];
666 s.spd_map[3] = spd_map[3];
667 checkreset_ddr2(s.boot_path);
Damien Zammit4b513a62015-08-20 00:37:05 +1000668
Arthur Heymansadc571a2017-09-25 09:40:54 +0200669 /* Detect dimms per channel */
Angel Ponsd1c590a2020-08-03 16:01:39 +0200670 reg8 = pci_read_config8(HOST_BRIDGE, 0xe9);
Arthur Heymansadc571a2017-09-25 09:40:54 +0200671 printk(BIOS_DEBUG, "Dimms per channel: %d\n",
672 (reg8 & 0x10) ? 1 : 2);
673
674 mchinfo_ddr2(&s);
675
676 find_fsb_speed(&s);
677 decode_spd_select_timings(&s);
678 print_selected_timings(&s);
679 find_dimm_config(&s);
680 }
Damien Zammit4b513a62015-08-20 00:37:05 +1000681
Arthur Heymansa2cc2312017-05-15 10:13:36 +0200682 do_raminit(&s, fast_boot);
Damien Zammit4b513a62015-08-20 00:37:05 +1000683
Angel Pons4a9569a2020-06-08 01:39:25 +0200684 pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~0x80);
Damien Zammit4b513a62015-08-20 00:37:05 +1000685
Angel Ponsd1c590a2020-08-03 16:01:39 +0200686 pci_or_config8(HOST_BRIDGE, 0xf4, 1);
Angel Pons4a9569a2020-06-08 01:39:25 +0200687
Damien Zammit4b513a62015-08-20 00:37:05 +1000688 printk(BIOS_DEBUG, "RAM initialization finished.\n");
Arthur Heymansadc571a2017-09-25 09:40:54 +0200689
690 cbmem_was_inited = !cbmem_recovery(s.boot_path == BOOT_PATH_RESUME);
691 if (!fast_boot)
692 mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION,
693 &s, sizeof(s));
694 if (s.boot_path == BOOT_PATH_RESUME && !cbmem_was_inited) {
695 /* Failed S3 resume, reset to come up cleanly */
Elyes HAOUASb559b3c2019-04-28 17:52:10 +0200696 system_reset();
Arthur Heymansadc571a2017-09-25 09:40:54 +0200697 }
Elyes HAOUASf5a57a82019-01-08 22:15:53 +0100698
699 timestamp_add_now(TS_AFTER_INITRAM);
Elyes HAOUASf5a57a82019-01-08 22:15:53 +0100700 printk(BIOS_DEBUG, "Memory initialized\n");
Damien Zammit4b513a62015-08-20 00:37:05 +1000701}