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Angel Pons4b429832020-04-02 23:48:50 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Damien Zammit62477932015-05-03 21:34:38 +10002
Damien Zammit62477932015-05-03 21:34:38 +10003#define __SIMPLE_DEVICE__
4
Kyösti Mälkkia963acd2019-08-16 20:34:25 +03005#include <arch/romstage.h>
Angel Pons69356482020-08-03 15:16:12 +02006#include <commonlib/helpers.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +02007#include <device/pci_ops.h>
Damien Zammitf7060f12015-11-14 00:59:21 +11008#include <device/device.h>
9#include <device/pci_def.h>
10#include <console/console.h>
Damien Zammit62477932015-05-03 21:34:38 +100011#include <cbmem.h>
12#include <northbridge/intel/pineview/pineview.h>
Arthur Heymans62e784b2017-04-21 15:54:44 +020013#include <cpu/x86/mtrr.h>
Kyösti Mälkkid53fd702019-08-14 06:25:55 +030014#include <cpu/x86/smm.h>
Kyösti Mälkkif091f4d2019-08-14 03:49:21 +030015#include <cpu/intel/smm_reloc.h>
Kyösti Mälkkiaba8fb12019-08-02 06:11:28 +030016#include <stdint.h>
Damien Zammit62477932015-05-03 21:34:38 +100017
Angel Pons653d8712020-08-03 15:40:54 +020018int decode_pcie_bar(u32 *const base, u32 *const len)
Damien Zammit62477932015-05-03 21:34:38 +100019{
Damien Zammitf7060f12015-11-14 00:59:21 +110020 *base = 0;
21 *len = 0;
Angel Pons90de10c2020-08-03 15:47:30 +020022
Damien Zammitf7060f12015-11-14 00:59:21 +110023 const struct {
24 u16 num_buses;
25 u32 addr_mask;
26 } busmask[] = {
27 {256, 0xf0000000},
28 {128, 0xf8000000},
29 {64, 0xfc000000},
30 {0, 0},
31 };
Damien Zammit62477932015-05-03 21:34:38 +100032
Angel Pons90de10c2020-08-03 15:47:30 +020033 const u32 pciexbar_reg = pci_read_config32(HOST_BRIDGE, PCIEXBAR);
Damien Zammitf7060f12015-11-14 00:59:21 +110034
Angel Pons39ff7032020-03-09 21:39:44 +010035 /* MMCFG not supported or not enabled */
Damien Zammitf7060f12015-11-14 00:59:21 +110036 if (!(pciexbar_reg & (1 << 0))) {
37 printk(BIOS_WARNING, "WARNING: MMCONF not set\n");
38 return 0;
Damien Zammit62477932015-05-03 21:34:38 +100039 }
Damien Zammitf7060f12015-11-14 00:59:21 +110040
Angel Pons90de10c2020-08-03 15:47:30 +020041 const u32 index = (pciexbar_reg >> 1) & 3;
42 const u32 pciexbar = pciexbar_reg & busmask[index].addr_mask;
43 const int max_buses = busmask[index].num_buses;
Damien Zammitf7060f12015-11-14 00:59:21 +110044
45 if (!pciexbar) {
46 printk(BIOS_WARNING, "WARNING: pciexbar invalid\n");
47 return 0;
48 }
49
50 *base = pciexbar;
Angel Pons69356482020-08-03 15:16:12 +020051 *len = max_buses * MiB;
Damien Zammitf7060f12015-11-14 00:59:21 +110052 return 1;
Damien Zammit62477932015-05-03 21:34:38 +100053}
54
Damien Zammitf7060f12015-11-14 00:59:21 +110055/** Decodes used Graphics Mode Select (GMS) to kilobytes. */
56u32 decode_igd_memory_size(const u32 gms)
Damien Zammit62477932015-05-03 21:34:38 +100057{
Angel Pons39ff7032020-03-09 21:39:44 +010058 const u32 gmssize[] = {0, 1, 4, 8, 16, 32, 48, 64, 128, 256};
Damien Zammitf7060f12015-11-14 00:59:21 +110059
60 if (gms > 9) {
61 printk(BIOS_DEBUG, "Bad Graphics Mode Select (GMS) value.\n");
62 return 0;
63 }
64 return gmssize[gms] << 10;
65}
66
67/** Decodes used Graphics Stolen Memory (GSM) to kilobytes. */
68u32 decode_igd_gtt_size(const u32 gsm)
69{
Angel Pons39ff7032020-03-09 21:39:44 +010070 const u8 gsmsize[] = {0, 1, 0, 0};
Damien Zammitf7060f12015-11-14 00:59:21 +110071
72 if (gsm > 3) {
73 printk(BIOS_DEBUG, "Bad Graphics Stolen Memory (GSM) value.\n");
74 return 0;
75 }
76 return (u32)(gsmsize[gsm] << 10);
Damien Zammit62477932015-05-03 21:34:38 +100077}
Arthur Heymans62e784b2017-04-21 15:54:44 +020078
Arthur Heymansde6bda62018-04-10 13:40:39 +020079/** Decodes used TSEG size to bytes. */
80static u32 decode_tseg_size(const u32 esmramc)
81{
82 if (!(esmramc & 1))
83 return 0;
84
85 switch ((esmramc >> 1) & 3) {
86 case 0:
Angel Pons69356482020-08-03 15:16:12 +020087 return 1 * MiB;
Arthur Heymansde6bda62018-04-10 13:40:39 +020088 case 1:
Angel Pons69356482020-08-03 15:16:12 +020089 return 2 * MiB;
Arthur Heymansde6bda62018-04-10 13:40:39 +020090 case 2:
Angel Pons69356482020-08-03 15:16:12 +020091 return 8 * MiB;
Arthur Heymansde6bda62018-04-10 13:40:39 +020092 case 3:
93 default:
94 die("Bad TSEG setting.\n");
95 }
96}
97
Kyösti Mälkkid53fd702019-08-14 06:25:55 +030098static size_t northbridge_get_tseg_size(void)
Arthur Heymansde6bda62018-04-10 13:40:39 +020099{
Angel Pons39ff7032020-03-09 21:39:44 +0100100 const u8 esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC);
Arthur Heymansde6bda62018-04-10 13:40:39 +0200101 return decode_tseg_size(esmramc);
102}
103
Kyösti Mälkkid53fd702019-08-14 06:25:55 +0300104static uintptr_t northbridge_get_tseg_base(void)
Arthur Heymansde6bda62018-04-10 13:40:39 +0200105{
Angel Pons39ff7032020-03-09 21:39:44 +0100106 return pci_read_config32(HOST_BRIDGE, TSEG);
Arthur Heymansde6bda62018-04-10 13:40:39 +0200107}
108
Angel Pons39ff7032020-03-09 21:39:44 +0100109/*
110 * Depending of UMA and TSEG configuration, TSEG might start at any 1 MiB alignment.
111 * As this may cause very greedy MTRR setup, push CBMEM top downwards to 4 MiB boundary.
Arthur Heymans62e784b2017-04-21 15:54:44 +0200112 */
Arthur Heymans340e4b82019-10-23 17:25:58 +0200113void *cbmem_top_chipset(void)
Arthur Heymans62e784b2017-04-21 15:54:44 +0200114{
Angel Pons39ff7032020-03-09 21:39:44 +0100115 return (void *) ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB);
Arthur Heymansde6bda62018-04-10 13:40:39 +0200116
Arthur Heymans62e784b2017-04-21 15:54:44 +0200117}
118
Kyösti Mälkkid53fd702019-08-14 06:25:55 +0300119void smm_region(uintptr_t *start, size_t *size)
Kyösti Mälkkiaba8fb12019-08-02 06:11:28 +0300120{
Kyösti Mälkkid53fd702019-08-14 06:25:55 +0300121 *start = northbridge_get_tseg_base();
Angel Pons39ff7032020-03-09 21:39:44 +0100122 *size = northbridge_get_tseg_size();
Kyösti Mälkkiaba8fb12019-08-02 06:11:28 +0300123}
124
Kyösti Mälkki5bc641a2019-08-09 09:37:49 +0300125void fill_postcar_frame(struct postcar_frame *pcf)
Arthur Heymans62e784b2017-04-21 15:54:44 +0200126{
Arthur Heymans62e784b2017-04-21 15:54:44 +0200127 uintptr_t top_of_ram;
128
Angel Pons39ff7032020-03-09 21:39:44 +0100129 /*
130 * Cache 8 MiB region below the top of RAM and 2 MiB above top of RAM to cover both
131 * CBMEM and the TSEG region.
Arthur Heymans62e784b2017-04-21 15:54:44 +0200132 */
133 top_of_ram = (uintptr_t)cbmem_top();
Angel Pons39ff7032020-03-09 21:39:44 +0100134 postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK);
135 postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(),
136 MTRR_TYPE_WRBACK);
Arthur Heymans62e784b2017-04-21 15:54:44 +0200137}