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Angel Pons4b429832020-04-02 23:48:50 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Aaron Durbin76c37002012-10-30 09:03:43 -05002
3#ifndef __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__
Edward O'Callaghan089a5102015-01-06 02:48:57 +11004#define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__
Aaron Durbin76c37002012-10-30 09:03:43 -05005
6/* Chipset types */
7#define HASWELL_MOBILE 0
8#define HASWELL_DESKTOP 1
9#define HASWELL_SERVER 2
10
Angel Ponsa3cb3222020-09-14 13:15:19 +020011#include "memmap.h"
Matt DeVilliera51e3792018-03-04 01:44:15 -060012
Aaron Durbin76c37002012-10-30 09:03:43 -050013#include <southbridge/intel/lynxpoint/pch.h>
14
15/* Everything below this line is ignored in the DSDT */
16#ifndef __ACPI__
17
18/* Device 0:0.0 PCI configuration space (Host Bridge) */
Angel Pons1db5bc72020-01-15 00:49:03 +010019#define HOST_BRIDGE PCI_DEV(0, 0, 0)
Aaron Durbin76c37002012-10-30 09:03:43 -050020
Angel Ponse4156c32020-09-14 15:47:59 +020021#include "registers/host_bridge.h"
Matt DeVilliera51e3792018-03-04 01:44:15 -060022
Aaron Durbin76c37002012-10-30 09:03:43 -050023/* Device 0:2.0 PCI configuration space (Graphics Device) */
24
25#define MSAC 0x62 /* Multi Size Aperture Control */
Aaron Durbin76c37002012-10-30 09:03:43 -050026
27/*
28 * MCHBAR
29 */
30
Angel Pons1db5bc72020-01-15 00:49:03 +010031#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x))))
32#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
33#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
34#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and))
35#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and))
36#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and))
37#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or))
38#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or))
39#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or))
40#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or))
41#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or))
42#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
Aaron Durbin76c37002012-10-30 09:03:43 -050043
Angel Pons1db5bc72020-01-15 00:49:03 +010044/* As there are many registers, define them on a separate file */
Angel Ponse4156c32020-09-14 15:47:59 +020045#include "registers/mchbar.h"
Duncan Lauriec70353f2013-06-28 14:40:38 -070046
Angel Ponse220e312020-07-22 00:55:38 +020047#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */
48#define DMAR_LCKDN (1 << 31)
49#define SPCAPCTRL (1 << 25)
50#define L3HIT2PEND_DIS (1 << 20)
51#define PRSCAPDIS (1 << 2)
52#define GLBIOTLBINV (1 << 1)
53#define GLBCTXTINV (1 << 0)
54
Aaron Durbin76c37002012-10-30 09:03:43 -050055/*
56 * EPBAR - Egress Port Root Complex Register Block
57 */
58
Angel Ponse5ec50c2020-09-14 13:22:01 +020059#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + (x)))
60#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + (x)))
61#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + (x)))
Aaron Durbin76c37002012-10-30 09:03:43 -050062
Angel Pons75594e92020-09-14 14:04:50 +020063#include "registers/epbar.h"
Aaron Durbin76c37002012-10-30 09:03:43 -050064
Aaron Durbin76c37002012-10-30 09:03:43 -050065/*
66 * DMIBAR
67 */
68
Angel Ponse5ec50c2020-09-14 13:22:01 +020069#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + (x)))
70#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + (x)))
71#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + (x)))
Aaron Durbin76c37002012-10-30 09:03:43 -050072
Angel Pons75594e92020-09-14 14:04:50 +020073#include "registers/dmibar.h"
Angel Pons598ec6a2020-07-23 02:37:12 +020074
Aaron Durbin76c37002012-10-30 09:03:43 -050075#ifndef __ASSEMBLER__
Aaron Durbin76c37002012-10-30 09:03:43 -050076
Aaron Durbin76c37002012-10-30 09:03:43 -050077void intel_northbridge_haswell_finalize_smm(void);
Kyösti Mälkkid7205be2019-09-27 07:24:17 +030078
Angel Pons73fa0352020-07-03 12:29:03 +020079void mb_late_romstage_setup(void); /* optional */
Angel Pons2e25ac62020-07-03 12:06:04 +020080
Angel Ponse8168292020-07-03 11:42:22 +020081void haswell_early_initialization(void);
Aaron Durbin76c37002012-10-30 09:03:43 -050082void haswell_late_initialization(void);
Ronald G. Minnich4c8465c2013-09-30 15:57:21 -070083void set_translation_table(int start, int end, u64 base, int inc);
Tristan Corrick334be322018-12-17 22:10:21 +130084void haswell_unhide_peg(void);
Aaron Durbin76c37002012-10-30 09:03:43 -050085
Aaron Durbin76c37002012-10-30 09:03:43 -050086void report_platform_info(void);
Aaron Durbin76c37002012-10-30 09:03:43 -050087
Angel Ponsf4fa1e12020-08-03 14:12:13 +020088int decode_pcie_bar(u32 *const base, u32 *const len);
89
Matt DeVillier85d98d92018-03-04 01:41:23 -060090#include <device/device.h>
91
92struct acpi_rsdp;
Furquan Shaikh0f007d82020-04-24 06:41:18 -070093unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start,
Angel Pons1db5bc72020-01-15 00:49:03 +010094 struct acpi_rsdp *rsdp);
Matt DeVillier85d98d92018-03-04 01:41:23 -060095
Angel Pons1db5bc72020-01-15 00:49:03 +010096#endif /* __ASSEMBLER__ */
97#endif /* __ACPI__ */
Edward O'Callaghan089a5102015-01-06 02:48:57 +110098#endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */