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Angel Pons4b429832020-04-02 23:48:50 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Martin Roth5474eb12018-05-26 19:22:33 -06002
Stefan Reinauerb15975b2011-10-21 12:57:59 -07003/* This was originally for the e7500, modified for e7501
4 * The primary differences are that 7501 apparently can
5 * support single channel RAM (i haven't tested),
6 * CAS1.5 is no longer supported, The ECC scrubber
7 * now supports a mode to zero RAM and init ECC in one step
8 * and the undocumented registers at 0x80 require new
9 * (undocumented) values determined by guesswork and
10 * comparison w/ OEM BIOS values.
11 * Steven James 02/06/2003
12 */
13
Kyösti Mälkki93b4ed92012-04-18 21:13:33 +030014#include <stdint.h>
15#include <device/pci_def.h>
16#include <arch/io.h>
Kyösti Mälkki13f66502019-03-03 08:01:05 +020017#include <device/mmio.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +020018#include <device/pci_ops.h>
Kyösti Mälkki1a1b04e2020-01-07 22:34:33 +020019#include <device/smbus_host.h>
Alexandru Gagniucaf4bd592014-01-12 15:42:58 -060020#include <lib.h>
Kyösti Mälkki717b6e32018-05-17 14:16:03 +030021#include <commonlib/helpers.h>
Kyösti Mälkki93b4ed92012-04-18 21:13:33 +030022#include <console/console.h>
Stefan Reinauerb15975b2011-10-21 12:57:59 -070023#include <assert.h>
24#include <spd.h>
25#include <sdram_mode.h>
Kyösti Mälkkiec558682019-01-09 13:33:39 +020026#include <timestamp.h>
Kyösti Mälkki93b4ed92012-04-18 21:13:33 +030027
28#include "raminit.h"
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +020029#include "e7505.h"
Stefan Reinauerb15975b2011-10-21 12:57:59 -070030
31/*-----------------------------------------------------------------------------
32Definitions:
33-----------------------------------------------------------------------------*/
34
Julius Wernercd49cce2019-03-05 16:53:33 -080035#if CONFIG(DEBUG_RAM_SETUP)
Stefan Reinauer65b72ab2015-01-05 12:59:54 -080036#define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x)
37#define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x)
38#define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x)
Stefan Reinauerb15975b2011-10-21 12:57:59 -070039#else
40#define RAM_DEBUG_MESSAGE(x)
41#define RAM_DEBUG_HEX32(x)
42#define RAM_DEBUG_HEX8(x)
Stefan Reinauerb15975b2011-10-21 12:57:59 -070043#endif
44
45#define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4)
46#define SPD_ERROR "Error reading SPD info\n"
47
Kyösti Mälkki4c0e2772018-05-17 14:16:03 +030048#define MCHDEV PCI_DEV(0, 0, 0)
49#define RASDEV PCI_DEV(0, 0, 1)
50#define AGPDEV PCI_DEV(0, 1, 0)
51#define D060DEV PCI_DEV(0, 6, 0)
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +030052
Stefan Reinauerb15975b2011-10-21 12:57:59 -070053// NOTE: This used to be 0x100000.
54// That doesn't work on systems where A20M# is asserted, because
55// attempts to access 0x1000NN end up accessing 0x0000NN.
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080056#define RCOMP_MMIO ((u8 *)0x200000)
Stefan Reinauerb15975b2011-10-21 12:57:59 -070057
58struct dimm_size {
59 unsigned long side1;
60 unsigned long side2;
61};
62
63static const uint32_t refresh_frequency[] = {
64 /* Relative frequency (array value) of each E7501 Refresh Mode Select
65 * (RMS) value (array index)
66 * 0 == least frequent refresh (longest interval between refreshes)
67 * [0] disabled -> 0
68 * [1] 15.6 usec -> 2
69 * [2] 7.8 usec -> 3
70 * [3] 64 usec -> 1
71 * [4] reserved -> 0
72 * [5] reserved -> 0
73 * [6] reserved -> 0
74 * [7] 64 clocks -> 4
75 */
76 0, 2, 3, 1, 0, 0, 0, 4
77};
78
79static const uint32_t refresh_rate_map[] = {
80 /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode
81 * Select values (array value)
82 * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0
83 * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and
84 * 64 clock (481 ns) (7) refresh.
85 * [0] == 15.625 us -> 15.6 us
86 * [1] == 3.9 us -> 481 ns
87 * [2] == 7.8 us -> 7.8 us
88 * [3] == 31.3 us -> 15.6 us
89 * [4] == 62.5 us -> 15.6 us
90 * [5] == 125 us -> 64 us
91 */
92 1, 7, 2, 1, 1, 3
93};
94
95#define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1)
96
97// SPD parameters that must match for dual-channel operation
98static const uint8_t dual_channel_parameters[] = {
99 SPD_MEMORY_TYPE,
100 SPD_MODULE_VOLTAGE,
101 SPD_NUM_COLUMNS,
102 SPD_NUM_ROWS,
103 SPD_NUM_DIMM_BANKS,
104 SPD_PRIMARY_SDRAM_WIDTH,
105 SPD_NUM_BANKS_PER_SDRAM
106};
107
Kyösti Mälkki77e4f7d2012-04-18 19:47:56 +0300108 /* Comments here are remains of e7501 or even 855PM.
109 * They might be partially (in)correct for e7505.
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700110 */
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700111
Kyösti Mälkki77e4f7d2012-04-18 19:47:56 +0300112 /* (DRAM Read Timing Control, if similar to 855PM?)
113 * 0x80 - 0x81 documented differently for e7505
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700114 * This register has something to do with CAS latencies,
Martin Roth128c1042016-11-18 09:29:03 -0700115 * possibly this is the real chipset control.
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700116 * At 0x00 CAS latency 1.5 works.
117 * At 0x06 CAS latency 2.5 works.
118 * At 0x01 CAS latency 2.0 works.
Kyösti Mälkki77e4f7d2012-04-18 19:47:56 +0300119 *
120 * This is still undocumented in e7501, but with different values
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700121 * CAS 2.0 values taken from Intel BIOS settings, others are a guess
122 * and may be terribly wrong. Old values preserved as comments until I
123 * figure this out for sure.
124 * e7501 docs claim that CAS1.5 is unsupported, so it may or may not
125 * work at all.
126 * Steven James 02/06/2003
Kyösti Mälkki77e4f7d2012-04-18 19:47:56 +0300127 *
128 * NOTE: values now configured in configure_e7501_cas_latency() based
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700129 * on SPD info and total number of DIMMs (per Intel)
130 */
131
Kyösti Mälkki77e4f7d2012-04-18 19:47:56 +0300132 /* FDHC - Fixed DRAM Hole Control ???
133 * 0x58 undocumented for e7505, memory hole in southbridge configuration?
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700134 * [7:7] Hole_Enable
135 * 0 == No memory Hole
136 * 1 == Memory Hole from 15MB to 16MB
137 * [6:0] Reserved
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700138 */
139
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700140 /* Another Intel undocumented register
141 * 0x88 - 0x8B
142 * [31:31] Purpose unknown
143 * [26:26] Master DLL Reset?
144 * 0 == Normal operation?
145 * 1 == Reset?
146 * [07:07] Periodic memory recalibration?
147 * 0 == Disabled?
148 * 1 == Enabled?
149 * [04:04] Receive FIFO RE-Sync?
150 * 0 == Normal operation?
151 * 1 == Reset?
152 */
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700153
Kyösti Mälkki77e4f7d2012-04-18 19:47:56 +0300154/* DDR RECOMP tables */
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700155// Slew table for 2x drive?
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +0300156static const uint32_t slew_2x[] = {
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700157 0x00000000, 0x76543210, 0xffffeca8, 0xffffffff,
158 0x21000000, 0xa8765432, 0xffffffec, 0xffffffff,
159};
160
161// Pull Up / Pull Down offset table, if analogous to IXP2800?
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +0300162static const uint32_t pull_updown_offset_table[] = {
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700163 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
164 0x88888888, 0x88888888, 0x88888888, 0x88888888,
165};
166
167/*-----------------------------------------------------------------------------
168Delay functions:
169-----------------------------------------------------------------------------*/
170
Kyösti Mälkki5c1ff922012-04-10 19:55:19 +0300171/* Estimate that SLOW_DOWN_IO takes about 1 us */
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700172#define SLOW_DOWN_IO inb(0x80)
Kyösti Mälkki77e4f7d2012-04-18 19:47:56 +0300173static void local_udelay(int i)
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700174{
Kyösti Mälkki5c1ff922012-04-10 19:55:19 +0300175 while (i--) {
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700176 SLOW_DOWN_IO;
177 }
178}
179
Kyösti Mälkki5c1ff922012-04-10 19:55:19 +0300180/* delay for 200us */
181#define DO_DELAY local_udelay(200)
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700182#define EXTRA_DELAY DO_DELAY
183
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +0200184/*-----------------------------------------------------------------------------
Kyösti Mälkki26c7b862012-04-12 22:46:23 +0300185Handle (undocumented) control bits MCHTST and PCI_DEV(0,6,0)
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +0200186-----------------------------------------------------------------------------*/
Kyösti Mälkki26c7b862012-04-12 22:46:23 +0300187typedef enum {
188 MCHTST_CMD_0,
189 D060_ENABLE,
190 D060_DISABLE,
191 RCOMP_BAR_ENABLE,
192 RCOMP_BAR_DISABLE,
193} mchtst_cc;
194
195typedef enum {
196 D060_CMD_0,
197 D060_CMD_1,
198} d060_cc;
199
200typedef enum {
201 RCOMP_HOLD,
202 RCOMP_RELEASE,
203 RCOMP_SMR_00,
204 RCOMP_SMR_01,
205} rcomp_smr_cc;
206
207/**
208 * MCHTST - 0xF4 - 0xF7 -- Based on similarity to 855PM
209 *
210 * [31:31] Purpose unknown
211 * [30:30] Purpose unknown
212 * [29:23] Unknown - not used?
213 * [22:22] System Memory MMR Enable
214 * 0 == Disable: mem space and BAR at 0x14 are not accessible
215 * 1 == Enable: mem space and BAR at 0x14 are accessible
216 * [21:20] Purpose unknown
217 * [19:02] Unknown - not used?
218 * [01:01] D6EN (Device #6 enable)
219 * 0 == Disable
220 * 1 == Enable
221 * [00:00] Unknown - not used?
222 */
Kyösti Mälkki77e4f7d2012-04-18 19:47:56 +0300223static void mchtest_control(mchtst_cc cmd)
Kyösti Mälkki26c7b862012-04-12 22:46:23 +0300224{
225 uint32_t dword = pci_read_config32(MCHDEV, MCHTST);
226 switch (cmd) {
227 case MCHTST_CMD_0:
228 dword &= ~(3 << 30);
229 break;
230 case RCOMP_BAR_ENABLE:
231 dword |= (1 << 22);
232 break;
233 case RCOMP_BAR_DISABLE:
234 dword &= ~(1 << 22);
235 break;
236 case D060_ENABLE:
237 dword |= (1 << 1);
238 break;
239 case D060_DISABLE:
240 dword &= ~(1 << 1);
241 break;
242 };
243 pci_write_config32(MCHDEV, MCHTST, dword);
244}
245
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +0200246/**
247 *
248 */
Kyösti Mälkki77e4f7d2012-04-18 19:47:56 +0300249static void d060_control(d060_cc cmd)
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700250{
Kyösti Mälkki26c7b862012-04-12 22:46:23 +0300251 mchtest_control(D060_ENABLE);
252 uint32_t dword = pci_read_config32(D060DEV, 0xf0);
253 switch (cmd) {
254 case D060_CMD_0:
255 dword |= (1 << 2);
256 break;
257 case D060_CMD_1:
258 dword |= (3 << 27);
259 break;
260 }
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +0300261 pci_write_config32(D060DEV, 0xf0, dword);
Kyösti Mälkki26c7b862012-04-12 22:46:23 +0300262 mchtest_control(D060_DISABLE);
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +0200263}
264
265/**
266 *
267 */
Kyösti Mälkki77e4f7d2012-04-18 19:47:56 +0300268static void rcomp_smr_control(rcomp_smr_cc cmd)
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +0200269{
Kyösti Mälkki26c7b862012-04-12 22:46:23 +0300270 uint32_t dword = read32(RCOMP_MMIO + SMRCTL);
271 switch (cmd) {
272 case RCOMP_HOLD:
273 dword |= (1 << 9);
274 break;
275 case RCOMP_RELEASE:
276 dword &= ~((1 << 9) | (3 << 0));
277 dword |= (1 << 10) | (1 << 0);
278 break;
279 case RCOMP_SMR_00:
280 dword &= ~(1 << 8);
281 break;
282 case RCOMP_SMR_01:
283 dword |= (1 << 10) | (1 << 8);
284 break;
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +0200285 }
Kyösti Mälkki26c7b862012-04-12 22:46:23 +0300286 write32(RCOMP_MMIO + SMRCTL, dword);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700287}
288
289/*-----------------------------------------------------------------------------
290Serial presence detect (SPD) functions:
291-----------------------------------------------------------------------------*/
292
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +0200293static void die_on_spd_error(int spd_return_value)
294{
295 if (spd_return_value < 0)
296 die("Error reading SPD info\n");
297}
298
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700299/**
300 * Calculate the page size for each physical bank of the DIMM:
301 * log2(page size) = (# columns) + log2(data width)
302 *
303 * NOTE: Page size is the total number of data bits in a row.
304 *
305 * @param dimm_socket_address SMBus address of DIMM socket to interrogate.
306 * @return log2(page size) for each side of the DIMM.
307 */
308static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address)
309{
310 uint16_t module_data_width;
311 int value;
312 struct dimm_size pgsz;
313
314 pgsz.side1 = 0;
315 pgsz.side2 = 0;
316
317 // Side 1
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +0200318 value = smbus_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700319 if (value < 0)
320 goto hw_err;
321 pgsz.side1 = value & 0xf; // # columns in bank 1
322
323 /* Get the module data width and convert it to a power of two */
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +0200324 value = smbus_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700325 if (value < 0)
326 goto hw_err;
327 module_data_width = (value & 0xff) << 8;
328
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +0200329 value = smbus_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700330 if (value < 0)
331 goto hw_err;
332 module_data_width |= (value & 0xff);
333
334 pgsz.side1 += log2(module_data_width);
335
336 /* side two */
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +0200337 value = smbus_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700338 if (value < 0)
339 goto hw_err;
340 if (value > 2)
341 die("Bad SPD value\n");
342 if (value == 2) {
343
344 pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +0200345 value = smbus_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700346 if (value < 0)
347 goto hw_err;
348 if ((value & 0xf0) != 0) {
349 // Asymmetric banks
350 pgsz.side2 -= value & 0xf; /* Subtract out columns on side 1 */
351 pgsz.side2 += (value >> 4) & 0xf; /* Add in columns on side 2 */
352 }
353 }
354
355 return pgsz;
356
357 hw_err:
358 die(SPD_ERROR);
359 return pgsz; // Never reached
360}
361
362/**
363 * Read the width in bits of each DIMM side's DRAMs via SPD (i.e. 4, 8, 16).
364 *
365 * @param dimm_socket_address SMBus address of DIMM socket to interrogate.
366 * @return Width in bits of each DIMM side's DRAMs.
367 */
368static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address)
369{
370 int value;
371 struct dimm_size width;
372
373 width.side1 = 0;
374 width.side2 = 0;
375
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +0200376 value = smbus_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700377 die_on_spd_error(value);
378
379 width.side1 = value & 0x7f; // Mask off bank 2 flag
380
381 if (value & 0x80) {
382 width.side2 = width.side1 << 1; // Bank 2 exists and is double-width
383 } else {
384 // If bank 2 exists, it's the same width as bank 1
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +0200385 value = smbus_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700386 die_on_spd_error(value);
387
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700388 if (value == 2)
389 width.side2 = width.side1;
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700390 }
391
392 return width;
393}
394
395/**
396 * Calculate the log base 2 size in bits of both DIMM sides.
397 *
398 * log2(# bits) = (# columns) + log2(data width) +
399 * (# rows) + log2(banks per SDRAM)
400 *
401 * Note that it might be easier to use SPD byte 31 here, it has the DIMM size
402 * as a multiple of 4MB. The way we do it now we can size both sides of an
403 * asymmetric DIMM.
404 *
405 * @param dimm_socket_address SMBus address of DIMM socket to interrogate.
406 * @return log2(number of bits) for each side of the DIMM.
407 */
Martin Roth468d02c2019-10-23 21:44:42 -0600408static struct dimm_size spd_get_dimm_size(unsigned int dimm_socket_address)
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700409{
410 int value;
411
412 // Start with log2(page size)
413 struct dimm_size sz = sdram_spd_get_page_size(dimm_socket_address);
414
415 if (sz.side1 > 0) {
416
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +0200417 value = smbus_read_byte(dimm_socket_address, SPD_NUM_ROWS);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700418 die_on_spd_error(value);
419
420 sz.side1 += value & 0xf;
421
422 if (sz.side2 > 0) {
423
424 // Double-sided DIMM
425 if (value & 0xF0)
426 sz.side2 += value >> 4; // Asymmetric
427 else
428 sz.side2 += value; // Symmetric
429 }
430
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +0200431 value = smbus_read_byte(dimm_socket_address,
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700432 SPD_NUM_BANKS_PER_SDRAM);
433 die_on_spd_error(value);
434
435 value = log2(value);
436 sz.side1 += value;
437 if (sz.side2 > 0)
438 sz.side2 += value;
439 }
440
441 return sz;
442}
443
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700444/**
445 * Determine whether two DIMMs have the same value for an SPD parameter.
446 *
447 * @param spd_byte_number The SPD byte number to compare in both DIMMs.
448 * @param dimm0_address SMBus address of the 1st DIMM socket to interrogate.
449 * @param dimm1_address SMBus address of the 2nd DIMM socket to interrogate.
450 * @return 1 if both DIMM sockets report the same value for the specified
451 * SPD parameter, 0 if the values differed or an error occurred.
452 */
453static uint8_t are_spd_values_equal(uint8_t spd_byte_number,
454 uint16_t dimm0_address,
455 uint16_t dimm1_address)
456{
457 uint8_t bEqual = 0;
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +0200458 int dimm0_value = smbus_read_byte(dimm0_address, spd_byte_number);
459 int dimm1_value = smbus_read_byte(dimm1_address, spd_byte_number);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700460
461 if ((dimm0_value >= 0) && (dimm1_value >= 0)
462 && (dimm0_value == dimm1_value))
463 bEqual = 1;
464
465 return bEqual;
466}
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700467
468/**
469 * Scan for compatible DIMMs.
470 *
471 * The code in this module only supports dual-channel operation, so we test
472 * that compatible DIMMs are paired.
473 *
474 * @param ctrl PCI addresses of memory controller functions, and SMBus
475 * addresses of DIMM slots on the mainboard.
476 * @return A bitmask indicating which of the possible sockets for each channel
477 * was found to contain a compatible DIMM.
478 * Bit 0 corresponds to the closest socket for channel 0
479 * Bit 1 to the next socket for channel 0
480 * ...
481 * Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0
482 * Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1
483 * ...
484 * Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1
485 */
486static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
487{
488 int i;
489 uint8_t dimm_mask = 0;
490
491 // Have to increase size of dimm_mask if this assertion is violated
492 ASSERT(MAX_DIMM_SOCKETS_PER_CHANNEL <= 4);
493
494 // Find DIMMs we can support on channel 0.
495 // Then see if the corresponding channel 1 DIMM has the same parameters,
496 // since we only support dual-channel.
497
498 for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
499
500 uint16_t channel0_dimm = ctrl->channel0[i];
501 uint16_t channel1_dimm = ctrl->channel1[i];
502 uint8_t bDualChannel = 1;
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700503 struct dimm_size page_size;
504 struct dimm_size sdram_width;
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700505 int spd_value;
506
507 if (channel0_dimm == 0)
508 continue; // No such socket on this mainboard
509
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +0200510 if (smbus_read_byte(channel0_dimm, SPD_MEMORY_TYPE) !=
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700511 SPD_MEMORY_TYPE_SDRAM_DDR)
512 continue;
513
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +0200514 if (smbus_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) !=
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700515 SPD_VOLTAGE_SSTL2)
516 continue; // Unsupported voltage
517
518 // E7501 does not support unregistered DIMMs
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +0200519 spd_value = smbus_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700520 if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0))
521 continue;
522
523 // Must support burst = 4 for dual-channel operation on E7501
524 // NOTE: for single-channel, burst = 8 is required
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +0200525 spd_value = smbus_read_byte(channel0_dimm,
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700526 SPD_SUPPORTED_BURST_LENGTHS);
527 if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
528 continue;
529
530 page_size = sdram_spd_get_page_size(channel0_dimm);
531 sdram_width = sdram_spd_get_width(channel0_dimm);
532
533 // Validate DIMM page size
534 // The E7501 only supports page sizes of 4, 8, 16, or 32 KB per channel
535 // NOTE: 4 KB = 32 Kb = 2^15
536 // 32 KB = 262 Kb = 2^18
537
538 if ((page_size.side1 < 15) || (page_size.side1 > 18))
539 continue;
540
541 // If DIMM is double-sided, verify side2 page size
542 if (page_size.side2 != 0) {
543 if ((page_size.side2 < 15)
544 || (page_size.side2 > 18))
545 continue;
546 }
547 // Validate SDRAM width
548 // The E7501 only supports x4 and x8 devices
549
550 if ((sdram_width.side1 != 4) && (sdram_width.side1 != 8))
551 continue;
552
553 // If DIMM is double-sided, verify side2 width
554 if (sdram_width.side2 != 0) {
555 if ((sdram_width.side2 != 4)
556 && (sdram_width.side2 != 8))
557 continue;
558 }
Kyösti Mälkkib71fb522020-01-07 11:16:35 +0200559
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700560 // Channel 0 DIMM looks compatible.
561 // Now see if it is paired with the proper DIMM on channel 1.
562
563 ASSERT(channel1_dimm != 0); // No such socket on this mainboard??
564
565 // NOTE: unpopulated DIMMs cause read to fail
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +0200566 spd_value = smbus_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700567 if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
568
Stefan Reinauer65b72ab2015-01-05 12:59:54 -0800569 printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700570 continue;
571 }
Kyösti Mälkkib71fb522020-01-07 11:16:35 +0200572
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +0200573 spd_value = smbus_read_byte(channel1_dimm,
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700574 SPD_SUPPORTED_BURST_LENGTHS);
575 if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
576 continue;
577
578 int j;
579 for (j = 0; j < sizeof(dual_channel_parameters); ++j) {
580 if (!are_spd_values_equal
581 (dual_channel_parameters[j], channel0_dimm,
582 channel1_dimm)) {
583
584 bDualChannel = 0;
585 break;
586 }
587 }
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700588
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700589 if (bDualChannel) {
Kyösti Mälkki58d6ff12018-06-02 18:38:04 +0300590 // This DIMM pair is usable
591 dimm_mask |= 1 << i;
592 dimm_mask |= 1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700593 } else
Stefan Reinauer65b72ab2015-01-05 12:59:54 -0800594 printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700595 }
596
597 return dimm_mask;
598}
599
600/*-----------------------------------------------------------------------------
601SDRAM configuration functions:
602-----------------------------------------------------------------------------*/
603
604/**
605 * Send the specified command to all DIMMs.
606 *
607 * @param command Specifies the command to be sent to the DIMMs.
608 * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the
609 * register value in JEDEC format.
610 */
611static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
612{
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +0200613 uint8_t dimm_start_64M_multiple;
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800614 uintptr_t dimm_start_address;
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700615 uint32_t dram_controller_mode;
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +0200616 uint8_t i;
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700617
618 // Configure the RAM command
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +0300619 dram_controller_mode = pci_read_config32(MCHDEV, DRC);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700620 dram_controller_mode &= 0xFFFFFF8F;
621 dram_controller_mode |= command;
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +0300622 pci_write_config32(MCHDEV, DRC, dram_controller_mode);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700623
624 // RAM_COMMAND_NORMAL is an exception.
625 // It affects only the memory controller and does not need to be "sent" to the DIMMs.
Kyösti Mälkki5c1ff922012-04-10 19:55:19 +0300626 if (command == RAM_COMMAND_NORMAL) {
627 EXTRA_DELAY;
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +0200628 return;
Kyösti Mälkki5c1ff922012-04-10 19:55:19 +0300629 }
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700630
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +0200631 // NOTE: for mode select commands, some of the location address bits are part of the command
632 // Map JEDEC mode bits to E7505
633 if (command == RAM_COMMAND_MRS) {
634 // Host address lines [25:18] map to DIMM address lines [7:0]
635 // Host address lines [17:16] map to DIMM address lines [9:8]
636 // Host address lines [15:4] map to DIMM address lines [11:0]
637 dimm_start_address = (jedec_mode_bits & 0x00ff) << 18;
638 dimm_start_address |= (jedec_mode_bits & 0x0300) << 8;
639 dimm_start_address |= (jedec_mode_bits & 0x0fff) << 4;
640 } else if (command == RAM_COMMAND_EMRS) {
641 // Host address lines [15:4] map to DIMM address lines [11:0]
642 dimm_start_address = (jedec_mode_bits << 4);
643 } else {
644 ASSERT(jedec_mode_bits == 0);
645 dimm_start_address = 0;
646 }
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700647
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +0200648 // Send the command to all DIMMs by accessing a memory location within each
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700649
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +0200650 dimm_start_64M_multiple = 0;
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700651
Kyösti Mälkki77e4f7d2012-04-18 19:47:56 +0300652 /* FIXME: Only address the number of rows present in the system?
653 * Seems like rows 4-7 overlap with 0-3.
654 */
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +0200655 for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) {
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700656
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +0300657 uint8_t dimm_end_64M_multiple = pci_read_config8(MCHDEV, DRB_ROW_0 + i);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700658
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +0200659 if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
660 dimm_start_address &= 0x3ffffff;
661 dimm_start_address |= dimm_start_64M_multiple << 26;
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800662 read32((void *)dimm_start_address);
Kyösti Mälkki77e4f7d2012-04-18 19:47:56 +0300663 // Set the start of the next DIMM
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +0200664 dimm_start_64M_multiple = dimm_end_64M_multiple;
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700665 }
666 }
Kyösti Mälkki5c1ff922012-04-10 19:55:19 +0300667 EXTRA_DELAY;
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700668}
669
670/**
671 * Set the mode register of all DIMMs.
672 *
673 * The proper CAS# latency setting is added to the mode bits specified
674 * by the caller.
675 *
676 * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the
677 * register value in JEDEC format.
678 */
679static void set_ram_mode(uint16_t jedec_mode_bits)
680{
681 ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK));
682
683 uint32_t dram_cas_latency =
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +0300684 pci_read_config32(MCHDEV, DRT) & DRT_CAS_MASK;
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700685
686 switch (dram_cas_latency) {
687 case DRT_CAS_2_5:
688 jedec_mode_bits |= SDRAM_CAS_2_5;
689 break;
690
691 case DRT_CAS_2_0:
692 jedec_mode_bits |= SDRAM_CAS_2_0;
693 break;
694
695 default:
696 BUG();
697 break;
698 }
699
700 do_ram_command(RAM_COMMAND_MRS, jedec_mode_bits);
701}
702
703/*-----------------------------------------------------------------------------
Martin Roth128c1042016-11-18 09:29:03 -0700704DIMM-independent configuration functions:
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700705-----------------------------------------------------------------------------*/
706
707/**
708 * Configure the E7501's DRAM Row Boundary (DRB) registers for the memory
709 * present in the specified DIMM.
710 *
711 * @param dimm_log2_num_bits Specifies log2(number of bits) for each side of
712 * the DIMM.
713 * @param total_dram_64M_multiple Total DRAM in the system (as a multiple of
714 * 64 MB) for DIMMs < dimm_index.
715 * @param dimm_index Which DIMM pair is being processed
716 * (0..MAX_DIMM_SOCKETS_PER_CHANNEL).
717 * @return New multiple of 64 MB total DRAM in the system.
718 */
Martin Roth468d02c2019-10-23 21:44:42 -0600719static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned int dimm_index)
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700720{
721 int i;
722
723 ASSERT(dimm_index < MAX_DIMM_SOCKETS_PER_CHANNEL);
724
725 // DIMM sides must be at least 32 MB
726 ASSERT(dimm_log2_num_bits.side1 >= 28);
727 ASSERT((dimm_log2_num_bits.side2 == 0)
728 || (dimm_log2_num_bits.side2 >= 28));
729
730 // In dual-channel mode, we are called only once for each pair of DIMMs.
731 // Each time we process twice the capacity of a single DIMM.
732
733 // Convert single DIMM capacity to paired DIMM capacity
734 // (multiply by two ==> add 1 to log2)
735 dimm_log2_num_bits.side1++;
736 if (dimm_log2_num_bits.side2 > 0)
737 dimm_log2_num_bits.side2++;
738
739 // Add the capacity of side 1 this DIMM pair (as a multiple of 64 MB)
740 // to the total capacity of the system
741 // NOTE: 64 MB == 512 Mb, and log2(512 Mb) == 29
742
743 total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side1 - 29));
744
745 // Configure the boundary address for the row on side 1
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +0300746 pci_write_config8(MCHDEV, DRB_ROW_0 + (dimm_index << 1),
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700747 total_dram_64M_multiple);
748
749 // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair
750 // (as a multiple of 64 MB) to the total capacity of the system
751 if (dimm_log2_num_bits.side2 >= 29)
752 total_dram_64M_multiple +=
753 (1 << (dimm_log2_num_bits.side2 - 29));
754
755 // Configure the boundary address for the row (if any) on side 2
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +0300756 pci_write_config8(MCHDEV, DRB_ROW_1 + (dimm_index << 1),
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700757 total_dram_64M_multiple);
758
759 // Update boundaries for rows subsequent to these.
760 // These settings will be overridden by a subsequent call if a populated physical slot exists
761
762 for (i = dimm_index + 1; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +0300763 pci_write_config8(MCHDEV, DRB_ROW_0 + (i << 1),
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700764 total_dram_64M_multiple);
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +0300765 pci_write_config8(MCHDEV, DRB_ROW_1 + (i << 1),
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700766 total_dram_64M_multiple);
767 }
768
769 return total_dram_64M_multiple;
770}
771
772/**
773 * Set the E7501's DRAM row boundary addresses & its Top Of Low Memory (TOLM).
774 *
775 * If necessary, set up a remap window so we don't waste DRAM that ordinarily
776 * would lie behind addresses reserved for memory-mapped I/O.
777 *
778 * @param ctrl PCI addresses of memory controller functions, and SMBus
779 * addresses of DIMM slots on the mainboard.
780 * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms().
781 */
782static void configure_e7501_ram_addresses(const struct mem_controller
783 *ctrl, uint8_t dimm_mask)
784{
785 int i;
786 uint8_t total_dram_64M_multiple = 0;
Kyösti Mälkki717b6e32018-05-17 14:16:03 +0300787 uint64_t tolm, tom;
788 uint16_t reg;
789
Kyösti Mälkki4c0e2772018-05-17 14:16:03 +0300790 /* FIXME: Is there standard presence detect bit somewhere. */
791 const int agp_slot_disabled = 1;
792
Kyösti Mälkki717b6e32018-05-17 14:16:03 +0300793 /* Start with disabled remap range. */
794 uint16_t remapbase_r = 0x3ff;
795 uint16_t remaplimit_r = 0;
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700796
797 // Configure the E7501's DRAM row boundaries
798 // Start by zeroing out the temporary initial configuration
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +0300799 pci_write_config32(MCHDEV, DRB_ROW_0, 0);
800 pci_write_config32(MCHDEV, DRB_ROW_4, 0);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700801
802 for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
803
804 uint16_t dimm_socket_address = ctrl->channel0[i];
805 struct dimm_size sz;
806
807 if (!(dimm_mask & (1 << i)))
808 continue; // This DIMM not present
809
810 sz = spd_get_dimm_size(dimm_socket_address);
811
812 RAM_DEBUG_MESSAGE("dimm size =");
813 RAM_DEBUG_HEX32((u32)sz.side1);
814 RAM_DEBUG_MESSAGE(" ");
815 RAM_DEBUG_HEX32((u32)sz.side2);
816 RAM_DEBUG_MESSAGE("\n");
817
818 if (sz.side1 == 0)
819 die("Bad SPD value\n");
820
821 total_dram_64M_multiple =
822 configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i);
823 }
824
Kyösti Mälkki717b6e32018-05-17 14:16:03 +0300825 tom = total_dram_64M_multiple * 64ULL * MiB;
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700826
Kyösti Mälkki717b6e32018-05-17 14:16:03 +0300827 /* Reserve MMIO space. */
Kyösti Mälkki4c0e2772018-05-17 14:16:03 +0300828 tolm = 4ULL * GiB - 512 * MiB;
829 if (agp_slot_disabled) {
830 /* Reduce apertures to 2 x 4 MiB. */
831 pci_write_config8(MCHDEV, APSIZE, 0x3F);
832 pci_write_config16(AGPDEV, APSIZE1, 0x3F);
833 } else {
834 /* Add MMIO reserve for 2 x 256 MiB apertures. */
835 tolm -= 512 * MiB;
836 }
Kyösti Mälkki717b6e32018-05-17 14:16:03 +0300837 tolm = MIN(tolm, tom);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700838
Kyösti Mälkki717b6e32018-05-17 14:16:03 +0300839 /* The PCI memory hole overlaps memory setup the remap window. */
840 if (tolm < tom) {
841 uint64_t remapbase = MAX(tom, 4ULL * GiB);
842 uint64_t remaplimit = remapbase + (4ULL * GiB - tolm);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700843
Kyösti Mälkki717b6e32018-05-17 14:16:03 +0300844 remapbase_r = remapbase / (64 * MiB);
845 remaplimit_r = remaplimit / (64 * MiB);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700846
Kyösti Mälkki717b6e32018-05-17 14:16:03 +0300847 /* Limit register is inclusive. */
848 remaplimit_r -= 1;
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700849 }
Kyösti Mälkki717b6e32018-05-17 14:16:03 +0300850
851 /* Write the RAM configuration registers,
852 preserving the reserved bits. */
853 reg = pci_read_config16(MCHDEV, TOLM) & 0x7ff;
854 reg |= (tolm / (128 * MiB)) << 11;
855 pci_write_config16(MCHDEV, TOLM, reg);
856
857 reg = pci_read_config16(MCHDEV, REMAPBASE) & 0xfc00;
858 reg |= remapbase_r;
859 pci_write_config16(MCHDEV, REMAPBASE, reg);
860
861 reg = pci_read_config16(MCHDEV, REMAPLIMIT) & 0xfc00;
862 reg |= remaplimit_r;
863 pci_write_config16(MCHDEV, REMAPLIMIT, reg);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700864}
865
866/**
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700867 * Program the DRAM Timing register (DRT) of the E7501 (except for CAS#
868 * latency, which is assumed to have been programmed already), based on the
869 * parameters of the various installed DIMMs.
870 *
871 * @param ctrl PCI addresses of memory controller functions, and SMBus
872 * addresses of DIMM slots on the mainboard.
873 * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms().
874 */
875static void configure_e7501_dram_timing(const struct mem_controller *ctrl,
876 uint8_t dimm_mask)
877{
878 int i;
879 uint32_t dram_timing;
880 int value;
881 uint8_t slowest_row_precharge = 0;
882 uint8_t slowest_ras_cas_delay = 0;
883 uint8_t slowest_active_to_precharge_delay = 0;
884 uint32_t current_cas_latency =
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +0300885 pci_read_config32(MCHDEV, DRT) & DRT_CAS_MASK;
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700886
887 // CAS# latency must be programmed beforehand
888 ASSERT((current_cas_latency == DRT_CAS_2_0)
889 || (current_cas_latency == DRT_CAS_2_5));
890
891 // Each timing parameter is determined by the slowest DIMM
892
893 for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
894 uint16_t dimm_socket_address;
895
896 if (!(dimm_mask & (1 << i)))
897 continue; // This DIMM not present
898
899 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
900 dimm_socket_address = ctrl->channel0[i];
901 else
902 dimm_socket_address =
903 ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
904
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +0200905 value = smbus_read_byte(dimm_socket_address,
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700906 SPD_MIN_ROW_PRECHARGE_TIME);
907 if (value < 0)
908 goto hw_err;
909 if (value > slowest_row_precharge)
910 slowest_row_precharge = value;
911
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +0200912 value = smbus_read_byte(dimm_socket_address,
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700913 SPD_MIN_RAS_TO_CAS_DELAY);
914 if (value < 0)
915 goto hw_err;
916 if (value > slowest_ras_cas_delay)
917 slowest_ras_cas_delay = value;
918
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +0200919 value = smbus_read_byte(dimm_socket_address,
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700920 SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
921 if (value < 0)
922 goto hw_err;
923 if (value > slowest_active_to_precharge_delay)
924 slowest_active_to_precharge_delay = value;
925 }
926
927 // NOTE for timing parameters:
928 // At 133 MHz, 1 clock == 7.52 ns
929
930 /* Read the initial state */
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +0300931 dram_timing = pci_read_config32(MCHDEV, DRT);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700932
933 /* Trp */
934
935 // E7501 supports only 2 or 3 clocks for tRP
936 if (slowest_row_precharge > ((22 << 2) | (2 << 0)))
937 die("unsupported DIMM tRP"); // > 22.5 ns: 4 or more clocks
938 else if (slowest_row_precharge > (15 << 2))
939 dram_timing &= ~(1 << 0); // > 15.0 ns: 3 clocks
940 else
941 dram_timing |= (1 << 0); // <= 15.0 ns: 2 clocks
942
943 /* Trcd */
944
945 // E7501 supports only 2 or 3 clocks for tRCD
946 // Use the same value for both read & write
947 dram_timing &= ~((1 << 3) | (3 << 1));
948 if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0)))
949 die("unsupported DIMM tRCD"); // > 22.5 ns: 4 or more clocks
950 else if (slowest_ras_cas_delay > (15 << 2))
951 dram_timing |= (2 << 1); // > 15.0 ns: 3 clocks
952 else
953 dram_timing |= ((1 << 3) | (3 << 1)); // <= 15.0 ns: 2 clocks
954
955 /* Tras */
956
957 // E7501 supports only 5, 6, or 7 clocks for tRAS
958 // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns
959 dram_timing &= ~(3 << 9);
960
961 if (slowest_active_to_precharge_delay > 52)
962 die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks
963 else if (slowest_active_to_precharge_delay > 45)
964 dram_timing |= (0 << 9); // 46-52 ns: 7 clocks
965 else if (slowest_active_to_precharge_delay > 37)
966 dram_timing |= (1 << 9); // 38-45 ns: 6 clocks
967 else
968 dram_timing |= (2 << 9); // < 38 ns: 5 clocks
969
970 /* Trd */
971
Elyes HAOUAS0f92f632014-07-27 19:37:31 +0200972 /* Set to a 7 clock read delay. This is for 133MHz
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700973 * with a CAS latency of 2.5 if 2.0 a 6 clock
974 * delay is good */
975
976 dram_timing &= ~(7 << 24); // 7 clocks
977 if (current_cas_latency == DRT_CAS_2_0)
978 dram_timing |= (1 << 24); // 6 clocks
979
980 /*
981 * Back to Back Read-Write Turn Around
982 */
983 /* Set to a 5 clock back to back read to write turn around.
984 * 4 is a good delay if the CAS latency is 2.0 */
985
986 dram_timing &= ~(1 << 28); // 5 clocks
987 if (current_cas_latency == DRT_CAS_2_0)
988 dram_timing |= (1 << 28); // 4 clocks
989
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +0300990 pci_write_config32(MCHDEV, DRT, dram_timing);
Stefan Reinauerb15975b2011-10-21 12:57:59 -0700991
992 return;
993
994 hw_err:
995 die(SPD_ERROR);
996}
997
998/**
999 * Determine the shortest CAS# latency that the E7501 and all DIMMs have in
1000 * common, and program the E7501 to use it.
1001 *
1002 * @param ctrl PCI addresses of memory controller functions, and SMBus
1003 * addresses of DIMM slots on the mainboard.
1004 * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms().
1005 */
1006static void configure_e7501_cas_latency(const struct mem_controller *ctrl,
1007 uint8_t dimm_mask)
1008{
1009 int i;
1010 int value;
1011 uint32_t dram_timing;
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001012 uint16_t dram_read_timing;
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001013 uint32_t dword;
1014
1015 // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format
1016 // NOTE: E7501 supports only 2.0 and 2.5
1017 uint32_t system_compatible_cas_latencies =
1018 SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5;
1019 uint32_t current_cas_latency;
1020 uint32_t dimm_compatible_cas_latencies;
1021
1022 for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1023
1024 uint16_t dimm_socket_address;
1025
1026 if (!(dimm_mask & (1 << i)))
1027 continue; // This DIMM not usable
1028
1029 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1030 dimm_socket_address = ctrl->channel0[i];
1031 else
1032 dimm_socket_address =
1033 ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
1034
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +02001035 value = smbus_read_byte(dimm_socket_address,
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001036 SPD_ACCEPTABLE_CAS_LATENCIES);
1037 if (value < 0)
1038 goto hw_err;
1039
1040 dimm_compatible_cas_latencies = value & 0x7f; // Start with all supported by DIMM
1041 current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM
1042
1043 // Can we support the highest CAS# latency?
1044
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +02001045 value = smbus_read_byte(dimm_socket_address,
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001046 SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
1047 if (value < 0)
1048 goto hw_err;
1049
1050 // NOTE: At 133 MHz, 1 clock == 7.52 ns
1051 if (value > 0x75) {
1052 // Our bus is too fast for this CAS# latency
1053 // Remove it from the bitmask of those supported by the DIMM that are compatible
1054 dimm_compatible_cas_latencies &= ~current_cas_latency;
1055 }
1056 // Can we support the next-highest CAS# latency (max - 0.5)?
1057
1058 current_cas_latency >>= 1;
1059 if (current_cas_latency != 0) {
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +02001060 value = smbus_read_byte(dimm_socket_address,
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001061 SPD_SDRAM_CYCLE_TIME_2ND);
1062 if (value < 0)
1063 goto hw_err;
1064 if (value > 0x75)
1065 dimm_compatible_cas_latencies &=
1066 ~current_cas_latency;
1067 }
1068 // Can we support the next-highest CAS# latency (max - 1.0)?
1069 current_cas_latency >>= 1;
1070 if (current_cas_latency != 0) {
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +02001071 value = smbus_read_byte(dimm_socket_address,
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001072 SPD_SDRAM_CYCLE_TIME_3RD);
1073 if (value < 0)
1074 goto hw_err;
1075 if (value > 0x75)
1076 dimm_compatible_cas_latencies &=
1077 ~current_cas_latency;
1078 }
1079 // Restrict the system to CAS# latencies compatible with this DIMM
1080 system_compatible_cas_latencies &=
1081 dimm_compatible_cas_latencies;
1082
1083 /* go to the next DIMM */
1084 }
1085
1086 /* After all of the arduous calculation setup with the fastest
1087 * cas latency I can use.
1088 */
1089
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001090 dram_timing = pci_read_config32(MCHDEV, DRT);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001091 dram_timing &= ~(DRT_CAS_MASK);
1092
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001093 dram_read_timing =
1094 pci_read_config16(MCHDEV, DRDCTL);
1095 dram_read_timing &= 0xF000;
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001096
1097 if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) {
1098 dram_timing |= DRT_CAS_2_0;
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001099 dram_read_timing |= 0x0222;
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001100 } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
1101
1102 uint32_t dram_row_attributes =
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001103 pci_read_config32(MCHDEV, DRA);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001104
1105 dram_timing |= DRT_CAS_2_5;
1106
1107 // At CAS# 2.5, DRAM Read Timing (if that's what it its) appears to need a slightly
1108 // different value if all DIMM slots are populated
1109
1110 if ((dram_row_attributes & 0xff)
1111 && (dram_row_attributes & 0xff00)
1112 && (dram_row_attributes & 0xff0000)
1113 && (dram_row_attributes & 0xff000000)) {
1114
1115 // All slots populated
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001116 dram_read_timing |= 0x0882;
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001117 } else {
1118 // Some unpopulated slots
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001119 dram_read_timing |= 0x0662;
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001120 }
1121 } else
1122 die("No CAS# latencies compatible with all DIMMs!!\n");
1123
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001124 pci_write_config32(MCHDEV, DRT, dram_timing);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001125
1126 /* set master DLL reset */
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001127 dword = pci_read_config32(MCHDEV, 0x88);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001128 dword |= (1 << 26);
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001129 pci_write_config32(MCHDEV, 0x88, dword);
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +02001130 /* patch try register 88 is undocumented tnz */
1131 dword &= 0x0ca17fff;
1132 dword |= 0xd14a5000;
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001133 pci_write_config32(MCHDEV, 0x88, dword);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001134
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001135 pci_write_config16(MCHDEV, DRDCTL,
1136 dram_read_timing);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001137
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +02001138 /* clear master DLL reset */
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001139 dword = pci_read_config32(MCHDEV, 0x88);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001140 dword &= ~(1 << 26);
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001141 pci_write_config32(MCHDEV, 0x88, dword);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001142
1143 return;
1144
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +02001145hw_err:
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001146 die(SPD_ERROR);
1147}
1148
1149/**
1150 * Configure the refresh interval so that we refresh no more often than
1151 * required by the "most needy" DIMM. Also disable ECC if any of the DIMMs
1152 * don't support it.
1153 *
1154 * @param ctrl PCI addresses of memory controller functions, and SMBus
1155 * addresses of DIMM slots on the mainboard.
1156 * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms().
1157 */
1158static void configure_e7501_dram_controller_mode(const struct
1159 mem_controller *ctrl,
1160 uint8_t dimm_mask)
1161{
1162 int i;
1163
1164 // Initial settings
1165 uint32_t controller_mode =
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001166 pci_read_config32(MCHDEV, DRC);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001167 uint32_t system_refresh_mode = (controller_mode >> 8) & 7;
1168
1169 // Code below assumes that most aggressive settings are in
1170 // force when we are called, either via E7501 reset defaults
1171 // or by sdram_set_registers():
1172 // - ECC enabled
1173 // - No refresh
1174
1175 ASSERT((controller_mode & (3 << 20)) == (2 << 20)); // ECC
1176 ASSERT(!(controller_mode & (7 << 8))); // Refresh
1177
1178 /* Walk through _all_ dimms and find the least-common denominator for:
1179 * - ECC support
1180 * - refresh rates
1181 */
1182
1183 for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1184
1185 uint32_t dimm_refresh_mode;
1186 int value;
1187 uint16_t dimm_socket_address;
1188
1189 if (!(dimm_mask & (1 << i))) {
1190 continue; // This DIMM not usable
1191 }
1192
1193 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1194 dimm_socket_address = ctrl->channel0[i];
1195 else
1196 dimm_socket_address =
1197 ctrl->channel1[i -
1198 MAX_DIMM_SOCKETS_PER_CHANNEL];
1199
1200 // Disable ECC mode if any one of the DIMMs does not support ECC
1201 // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported.
1202
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +02001203 value = smbus_read_byte(dimm_socket_address,
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001204 SPD_DIMM_CONFIG_TYPE);
1205 die_on_spd_error(value);
1206 if (value != ERROR_SCHEME_ECC) {
1207 controller_mode &= ~(3 << 20);
1208 }
1209
Kyösti Mälkki9e581ec2020-01-07 11:16:35 +02001210 value = smbus_read_byte(dimm_socket_address, SPD_REFRESH);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001211 die_on_spd_error(value);
1212 value &= 0x7f; // Mask off self-refresh bit
1213 if (value > MAX_SPD_REFRESH_RATE) {
Stefan Reinauer65b72ab2015-01-05 12:59:54 -08001214 printk(BIOS_ERR, "unsupported refresh rate\n");
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001215 continue;
1216 }
1217 // Get the appropriate E7501 refresh mode for this DIMM
1218 dimm_refresh_mode = refresh_rate_map[value];
1219 if (dimm_refresh_mode > 7) {
Stefan Reinauer65b72ab2015-01-05 12:59:54 -08001220 printk(BIOS_ERR, "unsupported refresh rate\n");
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001221 continue;
1222 }
1223 // If this DIMM requires more frequent refresh than others,
1224 // update the system setting
1225 if (refresh_frequency[dimm_refresh_mode] >
1226 refresh_frequency[system_refresh_mode])
1227 system_refresh_mode = dimm_refresh_mode;
1228
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001229 /* go to the next DIMM */
1230 }
1231
1232 controller_mode |= (system_refresh_mode << 8);
1233
1234 // Configure the E7501
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001235 pci_write_config32(MCHDEV, DRC, controller_mode);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001236}
1237
1238/**
1239 * Configure the E7501's DRAM Row Attributes (DRA) registers based on DIMM
1240 * parameters read via SPD. This tells the controller the width of the SDRAM
1241 * chips on each DIMM side (x4 or x8) and the page size of each DIMM side
1242 * (4, 8, 16, or 32 KB).
1243 *
1244 * @param ctrl PCI addresses of memory controller functions, and SMBus
1245 * addresses of DIMM slots on the mainboard.
1246 * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms().
1247 */
1248static void configure_e7501_row_attributes(const struct mem_controller
1249 *ctrl, uint8_t dimm_mask)
1250{
1251 int i;
1252 uint32_t row_attributes = 0;
1253
1254 for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1255
1256 uint16_t dimm_socket_address = ctrl->channel0[i];
1257 struct dimm_size page_size;
1258 struct dimm_size sdram_width;
1259
1260 if (!(dimm_mask & (1 << i)))
1261 continue; // This DIMM not usable
1262
1263 // Get the relevant parameters via SPD
1264 page_size = sdram_spd_get_page_size(dimm_socket_address);
1265 sdram_width = sdram_spd_get_width(dimm_socket_address);
1266
1267 // Update the DRAM Row Attributes.
1268 // Page size is encoded as log2(page size in bits) - log2(8 Kb)
1269 // NOTE: 8 Kb = 2^13
1270 row_attributes |= (page_size.side1 - 13) << (i << 3); // Side 1 of each DIMM is an EVEN row
1271
1272 if (sdram_width.side2 > 0)
1273 row_attributes |= (page_size.side2 - 13) << ((i << 3) + 4); // Side 2 is ODD
1274
1275 // Set x4 flags if appropriate
1276 if (sdram_width.side1 == 4) {
1277 row_attributes |= 0x08 << (i << 3);
1278 }
1279
1280 if (sdram_width.side2 == 4) {
1281 row_attributes |= 0x08 << ((i << 3) + 4);
1282 }
1283
1284 /* go to the next DIMM */
1285 }
1286
1287 /* Write the new row attributes register */
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001288 pci_write_config32(MCHDEV, DRA, row_attributes);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001289}
1290
1291/*
1292 * Enable clock signals for populated DIMM sockets and disable them for
1293 * unpopulated sockets (to reduce EMI).
1294 *
1295 * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms().
1296 */
1297static void enable_e7501_clocks(uint8_t dimm_mask)
1298{
1299 int i;
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001300 uint8_t clock_disable = pci_read_config8(MCHDEV, CKDIS);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001301
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001302 pci_write_config8(MCHDEV, 0x8e, 0xb0);
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +02001303
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001304 for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1305
1306 uint8_t socket_mask = 1 << i;
1307
1308 if (dimm_mask & socket_mask)
1309 clock_disable &= ~socket_mask; // DIMM present, enable clock
1310 else
1311 clock_disable |= socket_mask; // DIMM absent, disable clock
1312 }
1313
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001314 pci_write_config8(MCHDEV, CKDIS, clock_disable);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001315}
1316
Martin Roth128c1042016-11-18 09:29:03 -07001317/* DIMM-dependent configuration functions */
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001318
1319/**
1320 * DDR Receive FIFO RE-Sync (?)
1321 */
1322static void RAM_RESET_DDR_PTR(void)
1323{
1324 uint8_t byte;
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001325 byte = pci_read_config8(MCHDEV, 0x88);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001326 byte |= (1 << 4);
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001327 pci_write_config8(MCHDEV, 0x88, byte);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001328
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001329 byte = pci_read_config8(MCHDEV, 0x88);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001330 byte &= ~(1 << 4);
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001331 pci_write_config8(MCHDEV, 0x88, byte);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001332}
1333
1334/**
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001335 * Copy 64 bytes from one location to another.
1336 *
1337 * @param src_addr TODO
1338 * @param dst_addr TODO
1339 */
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -08001340static void write_8dwords(const uint32_t *src_addr, u8 *dst_addr)
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001341{
1342 int i;
1343 for (i = 0; i < 8; i++) {
1344 write32(dst_addr, *src_addr);
1345 src_addr++;
1346 dst_addr += sizeof(uint32_t);
1347 }
1348}
1349
1350/**
1351 * Set the E7501's (undocumented) RCOMP registers.
1352 *
1353 * Per the 855PM datasheet and IXP2800 HW Initialization Reference Manual,
1354 * RCOMP registers appear to affect drive strength, pullup/pulldown offset,
1355 * and slew rate of various signal groups.
1356 *
1357 * Comments below are conjecture based on apparent similarity between the
1358 * E7501 and these two chips.
1359 */
Kyösti Mälkki77e4f7d2012-04-18 19:47:56 +03001360static void rcomp_copy_registers(void)
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001361{
1362 uint32_t dword;
Kyösti Mälkki77e4f7d2012-04-18 19:47:56 +03001363 uint8_t strength_control;
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001364
1365 RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n");
1366
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001367 /* Begin to write the RCOMP registers */
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +02001368 write8(RCOMP_MMIO + 0x2c, 0x0);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001369
1370 // Set CMD and DQ/DQS strength to 2x (?)
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001371 strength_control = read8(RCOMP_MMIO + DQCMDSTR) & 0x88;
1372 strength_control |= 0x40;
1373 write8(RCOMP_MMIO + DQCMDSTR, strength_control);
1374 write_8dwords(slew_2x, RCOMP_MMIO + 0x80);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001375 write16(RCOMP_MMIO + 0x42, 0);
1376
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +02001377 // Set CMD and DQ/DQS strength to 2x (?)
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001378 strength_control = read8(RCOMP_MMIO + DQCMDSTR) & 0xF8;
1379 strength_control |= 0x04;
1380 write8(RCOMP_MMIO + DQCMDSTR, strength_control);
1381 write_8dwords(slew_2x, RCOMP_MMIO + 0x60);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001382 write16(RCOMP_MMIO + 0x40, 0);
1383
1384 // Set RCVEnOut# strength to 2x (?)
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001385 strength_control = read8(RCOMP_MMIO + RCVENSTR) & 0xF8;
1386 strength_control |= 0x04;
1387 write8(RCOMP_MMIO + RCVENSTR, strength_control);
1388 write_8dwords(slew_2x, RCOMP_MMIO + 0x1c0);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001389 write16(RCOMP_MMIO + 0x50, 0);
1390
1391 // Set CS# strength for x4 SDRAM to 2x (?)
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001392 strength_control = read8(RCOMP_MMIO + CSBSTR) & 0x88;
1393 strength_control |= 0x04;
1394 write8(RCOMP_MMIO + CSBSTR, strength_control);
1395 write_8dwords(slew_2x, RCOMP_MMIO + 0x140);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001396 write16(RCOMP_MMIO + 0x48, 0);
1397
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +02001398 // Set CS# strength for x4 SDRAM to 2x (?)
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001399 strength_control = read8(RCOMP_MMIO + CSBSTR) & 0x8F;
1400 strength_control |= 0x40;
1401 write8(RCOMP_MMIO + CSBSTR, strength_control);
1402 write_8dwords(slew_2x, RCOMP_MMIO + 0x160);
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +02001403 write16(RCOMP_MMIO + 0x4a, 0);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001404
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +02001405 // Set CKE strength for x4 SDRAM to 2x (?)
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001406 strength_control = read8(RCOMP_MMIO + CKESTR) & 0x88;
1407 strength_control |= 0x04;
1408 write8(RCOMP_MMIO + CKESTR, strength_control);
1409 write_8dwords(slew_2x, RCOMP_MMIO + 0xa0);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001410 write16(RCOMP_MMIO + 0x44, 0);
1411
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +02001412 // Set CKE strength for x4 SDRAM to 2x (?)
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001413 strength_control = read8(RCOMP_MMIO + CKESTR) & 0x8F;
1414 strength_control |= 0x40;
1415 write8(RCOMP_MMIO + CKESTR, strength_control);
1416 write_8dwords(slew_2x, RCOMP_MMIO + 0xc0);
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +02001417 write16(RCOMP_MMIO + 0x46, 0);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001418
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +02001419 // Set CK strength for x4 SDRAM to 1x (?)
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001420 strength_control = read8(RCOMP_MMIO + CKSTR) & 0x88;
1421 strength_control |= 0x01;
1422 write8(RCOMP_MMIO + CKSTR, strength_control);
1423 write_8dwords(pull_updown_offset_table, RCOMP_MMIO + 0x180);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001424 write16(RCOMP_MMIO + 0x4c, 0);
1425
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +02001426 // Set CK strength for x4 SDRAM to 1x (?)
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001427 strength_control = read8(RCOMP_MMIO + CKSTR) & 0x8F;
1428 strength_control |= 0x10;
1429 write8(RCOMP_MMIO + CKSTR, strength_control);
1430 write_8dwords(pull_updown_offset_table, RCOMP_MMIO + 0x1a0);
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +02001431 write16(RCOMP_MMIO + 0x4e, 0);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001432
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +02001433 dword = read32(RCOMP_MMIO + 0x400);
1434 dword &= 0x7f7fffff;
1435 write32(RCOMP_MMIO + 0x400, dword);
1436
1437 dword = read32(RCOMP_MMIO + 0x408);
1438 dword &= 0x7f7fffff;
1439 write32(RCOMP_MMIO + 0x408, dword);
Kyösti Mälkki77e4f7d2012-04-18 19:47:56 +03001440}
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +02001441
Kyösti Mälkki77e4f7d2012-04-18 19:47:56 +03001442static void ram_set_rcomp_regs(void)
1443{
1444 /* Set the RCOMP MMIO base address */
1445 mchtest_control(RCOMP_BAR_ENABLE);
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -08001446 pci_write_config32(MCHDEV, SMRBASE, (uintptr_t)RCOMP_MMIO);
Kyösti Mälkki77e4f7d2012-04-18 19:47:56 +03001447
1448 /* Block RCOMP updates while we configure the registers */
1449 rcomp_smr_control(RCOMP_HOLD);
1450 rcomp_copy_registers();
Kyösti Mälkki26c7b862012-04-12 22:46:23 +03001451 d060_control(D060_CMD_0);
1452 mchtest_control(MCHTST_CMD_0);
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +02001453
Kyösti Mälkki77e4f7d2012-04-18 19:47:56 +03001454 uint8_t revision = pci_read_config8(MCHDEV, 0x08);
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +02001455 if (revision >= 3) {
Kyösti Mälkki26c7b862012-04-12 22:46:23 +03001456 rcomp_smr_control(RCOMP_SMR_00);
1457 rcomp_smr_control(RCOMP_SMR_01);
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +02001458 }
Kyösti Mälkki26c7b862012-04-12 22:46:23 +03001459 rcomp_smr_control(RCOMP_RELEASE);
1460
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001461 /* Wait 40 usec */
1462 SLOW_DOWN_IO;
1463
Kyösti Mälkki26c7b862012-04-12 22:46:23 +03001464 /* Clear the RCOMP MMIO base address */
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001465 pci_write_config32(MCHDEV, SMRBASE, 0);
Kyösti Mälkki26c7b862012-04-12 22:46:23 +03001466 mchtest_control(RCOMP_BAR_DISABLE);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001467}
1468
1469/*-----------------------------------------------------------------------------
1470Public interface:
1471-----------------------------------------------------------------------------*/
1472
1473/**
1474 * Go through the JEDEC initialization sequence for all DIMMs, then enable
1475 * refresh and initialize ECC and memory to zero. Upon exit, SDRAM is up
1476 * and running.
1477 *
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001478 * @param ctrl PCI addresses of memory controller functions, and SMBus
1479 * addresses of DIMM slots on the mainboard.
1480 */
Kyösti Mälkki5c1ff922012-04-10 19:55:19 +03001481static void sdram_enable(const struct mem_controller *ctrl)
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001482{
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001483 uint8_t dimm_mask = pci_read_config16(MCHDEV, SKPD);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001484 uint32_t dram_controller_mode;
1485
1486 if (dimm_mask == 0)
1487 return;
1488
1489 /* 1 & 2 Power up and start clocks */
1490 RAM_DEBUG_MESSAGE("Ram Enable 1\n");
1491 RAM_DEBUG_MESSAGE("Ram Enable 2\n");
1492
1493 /* A 200us delay is needed */
1494 DO_DELAY; EXTRA_DELAY;
1495
1496 /* 3. Apply NOP */
1497 RAM_DEBUG_MESSAGE("Ram Enable 3\n");
1498 do_ram_command(RAM_COMMAND_NOP, 0);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001499
1500 /* 4 Precharge all */
1501 RAM_DEBUG_MESSAGE("Ram Enable 4\n");
1502 do_ram_command(RAM_COMMAND_PRECHARGE, 0);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001503 /* wait until the all banks idle state... */
1504
1505 /* 5. Issue EMRS to enable DLL */
1506 RAM_DEBUG_MESSAGE("Ram Enable 5\n");
1507 do_ram_command(RAM_COMMAND_EMRS,
1508 SDRAM_EXTMODE_DLL_ENABLE |
1509 SDRAM_EXTMODE_DRIVE_NORMAL);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001510
1511 /* 6. Reset DLL */
1512 RAM_DEBUG_MESSAGE("Ram Enable 6\n");
1513 set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET);
1514 EXTRA_DELAY;
1515 /* Ensure a 200us delay between the DLL reset in step 6 and the final
1516 * mode register set in step 9.
1517 * Infineon needs this before any other command is sent to the ram.
1518 */
1519 DO_DELAY; EXTRA_DELAY;
1520
1521 /* 7 Precharge all */
1522 RAM_DEBUG_MESSAGE("Ram Enable 7\n");
1523 do_ram_command(RAM_COMMAND_PRECHARGE, 0);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001524
1525 /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001526 /* And for good luck 6 more CBRs */
Kyösti Mälkki5c1ff922012-04-10 19:55:19 +03001527 RAM_DEBUG_MESSAGE("Ram Enable 8\n");
1528 int i;
Elyes HAOUAS93095522016-09-17 21:05:10 +02001529 for (i = 0; i < 8; i++)
Kyösti Mälkki5c1ff922012-04-10 19:55:19 +03001530 do_ram_command(RAM_COMMAND_CBR, 0);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001531
1532 /* 9 mode register set */
1533 RAM_DEBUG_MESSAGE("Ram Enable 9\n");
1534 set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001535
1536 /* 10 DDR Receive FIFO RE-Sync */
1537 RAM_DEBUG_MESSAGE("Ram Enable 10\n");
1538 RAM_RESET_DDR_PTR();
1539 EXTRA_DELAY;
1540
1541 /* 11 normal operation */
1542 RAM_DEBUG_MESSAGE("Ram Enable 11\n");
1543 do_ram_command(RAM_COMMAND_NORMAL, 0);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001544
1545 // Reconfigure the row boundaries and Top of Low Memory
1546 // to match the true size of the DIMMs
1547 configure_e7501_ram_addresses(ctrl, dimm_mask);
1548
1549 /* Finally enable refresh */
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001550 dram_controller_mode = pci_read_config32(MCHDEV, DRC);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001551 dram_controller_mode |= (1 << 29);
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001552 pci_write_config32(MCHDEV, DRC, dram_controller_mode);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001553 EXTRA_DELAY;
Kyösti Mälkki97c064f2012-04-18 20:33:35 +03001554}
Kyösti Mälkki5c1ff922012-04-10 19:55:19 +03001555
Kyösti Mälkki97c064f2012-04-18 20:33:35 +03001556/**
1557 * @param ctrl PCI addresses of memory controller functions, and SMBus
1558 * addresses of DIMM slots on the mainboard.
1559 */
1560static void sdram_post_ecc(const struct mem_controller *ctrl)
1561{
1562 /* Fast CS# Enable. */
1563 uint32_t dram_controller_mode = pci_read_config32(MCHDEV, DRC);
1564 dram_controller_mode = pci_read_config32(MCHDEV, DRC);
1565 dram_controller_mode |= (1 << 17);
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001566 pci_write_config32(MCHDEV, DRC, dram_controller_mode);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001567}
1568
1569/**
1570 * Configure SDRAM controller parameters that depend on characteristics of the
1571 * DIMMs installed in the system. These characteristics are read from the
1572 * DIMMs via the standard Serial Presence Detect (SPD) interface.
1573 *
1574 * @param ctrl PCI addresses of memory controller functions, and SMBus
1575 * addresses of DIMM slots on the mainboard.
1576 */
1577static void sdram_set_spd_registers(const struct mem_controller *ctrl)
1578{
1579 uint8_t dimm_mask;
1580
1581 RAM_DEBUG_MESSAGE("Reading SPD data...\n");
1582
1583 dimm_mask = spd_get_supported_dimms(ctrl);
1584
1585 if (dimm_mask == 0) {
Stefan Reinauer65b72ab2015-01-05 12:59:54 -08001586 printk(BIOS_DEBUG, "No usable memory for this controller\n");
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001587 } else {
1588 enable_e7501_clocks(dimm_mask);
1589
1590 RAM_DEBUG_MESSAGE("setting based on SPD data...\n");
1591
1592 configure_e7501_row_attributes(ctrl, dimm_mask);
1593 configure_e7501_dram_controller_mode(ctrl, dimm_mask);
1594 configure_e7501_cas_latency(ctrl, dimm_mask);
1595 RAM_RESET_DDR_PTR();
1596
1597 configure_e7501_dram_timing(ctrl, dimm_mask);
1598 DO_DELAY;
1599 RAM_DEBUG_MESSAGE("done\n");
1600 }
1601
1602 /* NOTE: configure_e7501_ram_addresses() is NOT called here.
1603 * We want to keep the default 64 MB/row mapping until sdram_enable() is called,
1604 * even though the default mapping is almost certainly incorrect.
1605 * The default mapping makes it easy to initialize all of the DIMMs
1606 * even if the total system memory is > 4 GB.
1607 *
1608 * Save the dimm_mask for when sdram_enable is called, so it can call
1609 * configure_e7501_ram_addresses() without having to regenerate the bitmask
1610 * of usable DIMMs.
1611 */
Kyösti Mälkki5bd271b2012-04-10 16:11:53 +03001612 pci_write_config16(MCHDEV, SKPD, dimm_mask);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001613}
1614
1615/**
1616 * Do basic RAM setup that does NOT depend on serial presence detect
1617 * information (i.e. independent of DIMM specifics).
1618 *
1619 * @param ctrl PCI addresses of memory controller functions, and SMBus
1620 * addresses of DIMM slots on the mainboard.
1621 */
1622static void sdram_set_registers(const struct mem_controller *ctrl)
1623{
Kyösti Mälkki77e4f7d2012-04-18 19:47:56 +03001624 uint32_t dword;
1625 uint16_t word;
1626 uint8_t byte;
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001627
1628 ram_set_rcomp_regs();
Kyösti Mälkki77e4f7d2012-04-18 19:47:56 +03001629
1630 /* Enable 0:0.1, 0:2.1 */
1631 word = pci_read_config16(MCHDEV, DVNP);
1632 word &= ~0x05;
1633 pci_write_config16(MCHDEV, DVNP, word);
1634
1635 /* Disable high-memory remap (power-on defaults, really) */
1636 pci_write_config16(MCHDEV, REMAPBASE, 0x03ff);
1637 pci_write_config16(MCHDEV, REMAPLIMIT, 0x0);
1638
1639 /* Disable legacy MMIO (0xC0000-0xEFFFF is DRAM) */
1640 int i;
1641 pci_write_config8(MCHDEV, PAM_0, 0x30);
Elyes HAOUAS93095522016-09-17 21:05:10 +02001642 for (i = 1; i <= 6; i++)
Kyösti Mälkki77e4f7d2012-04-18 19:47:56 +03001643 pci_write_config8(MCHDEV, PAM_0 + i, 0x33);
1644
1645 /* Conservatively say each row has 64MB of ram, we will fix this up later
1646 * Initial TOLM 8 rows 64MB each (1<<3 * 1<<26) >> 16 = 1<<13
1647 *
1648 * FIXME: Hard-coded limit to first four rows to prevent overlap!
1649 */
1650 pci_write_config32(MCHDEV, DRB_ROW_0, 0x04030201);
1651 pci_write_config32(MCHDEV, DRB_ROW_4, 0x04040404);
1652 //pci_write_config32(MCHDEV, DRB_ROW_4, 0x08070605);
1653 pci_write_config16(MCHDEV, TOLM, (1<<13));
1654
1655 /* DIMM clocks off */
1656 pci_write_config8(MCHDEV, CKDIS, 0xff);
1657
1658 /* reset row attributes */
1659 pci_write_config32(MCHDEV, DRA, 0x0);
1660
1661 // The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and
1662 // Back-to-Back Write-Read Turnaround. All others are configured based on SPD.
1663 dword = pci_read_config32(MCHDEV, DRT);
1664 dword &= 0xC7F8FFFF;
1665 dword |= (0x28<<24)|(0x03<<16);
1666 pci_write_config32(MCHDEV, DRT, dword);
1667
1668 dword = pci_read_config32(MCHDEV, DRC);
1669 dword &= 0xffcef8f7;
1670 dword |= 0x00210008;
1671 pci_write_config32(MCHDEV, DRC, dword);
1672
1673 /* Undocumented */
1674 pci_write_config8(MCHDEV, 0x88, 0x80);
1675
1676 /* Undocumented. Set much later in vendor BIOS. */
1677 byte = pci_read_config8(MCHDEV, 0xd9);
1678 byte &= ~0x60;
1679 pci_write_config8(MCHDEV, 0xd9, byte);
1680
Kyösti Mälkki26c7b862012-04-12 22:46:23 +03001681 uint8_t revision = pci_read_config8(MCHDEV, 0x08);
1682 if (revision >= 3)
1683 d060_control(D060_CMD_1);
Stefan Reinauerb15975b2011-10-21 12:57:59 -07001684}
Kyösti Mälkki0a0d5e82011-10-31 14:18:33 +02001685
Kyösti Mälkkid1141ab2020-01-07 11:16:35 +02001686static int e7505_mch_is_ready(void)
Kyösti Mälkki5c1ff922012-04-10 19:55:19 +03001687{
1688 uint32_t dword = pci_read_config32(MCHDEV, DRC);
1689 return !!(dword & DRC_DONE);
1690}
Kyösti Mälkkid1141ab2020-01-07 11:16:35 +02001691
1692void sdram_initialize(void)
1693{
1694 static const struct mem_controller memctrl[] = {
1695 {
1696 .d0 = PCI_DEV(0, 0, 0),
1697 .d0f1 = PCI_DEV(0, 0, 1),
1698 .channel0 = { 0x50, 0x52, 0, 0 },
1699 .channel1 = { 0x51, 0x53, 0, 0 },
1700 },
1701 };
1702
1703 /* If this is a warm boot, some initialisation can be skipped */
1704 if (!e7505_mch_is_ready()) {
1705
1706 /* The real MCH initialisation. */
1707 timestamp_add_now(TS_BEFORE_INITRAM);
1708
1709 sdram_set_registers(memctrl);
1710 sdram_set_spd_registers(memctrl);
1711 sdram_enable(memctrl);
1712
1713 /* Hook for post ECC scrub settings and debug. */
1714 sdram_post_ecc(memctrl);
1715
1716 timestamp_add_now(TS_AFTER_INITRAM);
1717 }
1718
1719 printk(BIOS_DEBUG, "SDRAM is up.\n");
1720}