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Sergej Ivanovd777c782015-04-03 18:10:27 +03001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 * Copyright (C) 2015 Sergej Ivanov <getinaks@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Sergej Ivanovd777c782015-04-03 18:10:27 +030015 */
16
Sergej Ivanovd777c782015-04-03 18:10:27 +030017#include <arch/io.h>
Sergej Ivanovd777c782015-04-03 18:10:27 +030018#include <device/pnp_def.h>
Sergej Ivanovd777c782015-04-03 18:10:27 +030019#include <console/console.h>
Aaron Durbindc9f5cd2015-09-08 13:34:43 -050020#include <commonlib/loglevel.h>
Kyösti Mälkkia7aa57a2017-03-05 14:23:14 +020021#include <northbridge/amd/agesa/state_machine.h>
Timothy Pearson7ad4dc5e2017-01-04 14:26:26 -060022#include <southbridge/amd/common/amd_defs.h>
Sergej Ivanovd777c782015-04-03 18:10:27 +030023#include <southbridge/amd/agesa/hudson/hudson.h>
Sergej Ivanovd777c782015-04-03 18:10:27 +030024#include <superio/ite/common/ite.h>
25#include <superio/ite/it8728f/it8728f.h>
26
27
28#define ITE_CONFIG_REG_CC 0x02
29#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1)
30#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO)
31#define ENVC_DEV PNP_DEV(0x2e, IT8728F_EC)
32
33#define MMIO_NON_POSTED_START 0xfed00000
34#define MMIO_NON_POSTED_END 0xfedfffff
Timothy Pearson7ad4dc5e2017-01-04 14:26:26 -060035#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
Sergej Ivanovd777c782015-04-03 18:10:27 +030036
37
38static void it_sio_write(pnp_devfn_t dev, u8 reg, u8 value)
39{
40 pnp_set_logical_device(dev);
41 pnp_write_config(dev, reg, value);
42}
43
44static void ite_enter_conf(pnp_devfn_t dev)
45{
46 u16 port = dev >> 8;
47
48 outb(0x87, port);
49 outb(0x01, port);
50 outb(0x55, port);
51 outb((port == 0x4e) ? 0xaa : 0x55, port);
52}
53
54static void ite_exit_conf(pnp_devfn_t dev)
55{
56 it_sio_write(dev, ITE_CONFIG_REG_CC, 0x02);
57}
58
59static void ite_evc_conf(pnp_devfn_t dev)
60{
61 ite_enter_conf(dev);
62 it_sio_write(dev, 0xf1 , 0x40 );
63 it_sio_write(dev, 0xf4 , 0x80 );
64 it_sio_write(dev, 0xf5 , 0x00 );
65 it_sio_write(dev, 0xf6 , 0xf0 );
66 it_sio_write(dev, 0xf9 , 0x48 );
67 it_sio_write(dev, 0xfa , 0x00 );
68 it_sio_write(dev, 0xfb , 0x00 );
69 ite_exit_conf(dev);
70}
71
72static void ite_gpio_conf(pnp_devfn_t dev)
73{
74 ite_enter_conf (dev);
75 it_sio_write (dev, 0x25 , 0x80 );
76 it_sio_write (dev, 0x26 , 0x07 );
77 it_sio_write (dev, 0x28 , 0x81 );
78 it_sio_write (dev, 0x2c , 0x06 );
79 it_sio_write (dev, 0x72 , 0x00 );
80 it_sio_write (dev, 0x73 , 0x00 );
81 it_sio_write (dev, 0xb3 , 0x01 );
82 it_sio_write (dev, 0xb8 , 0x00 );
83 it_sio_write (dev, 0xc0 , 0x00 );
84 it_sio_write (dev, 0xc3 , 0x00 );
85 it_sio_write (dev, 0xc8 , 0x00 );
86 it_sio_write (dev, 0xc9 , 0x07 );
87 it_sio_write (dev, 0xcb , 0x01 );
88 it_sio_write (dev, 0xf0 , 0x10 );
89 it_sio_write (dev, 0xf4 , 0x27 );
90 it_sio_write (dev, 0xf8 , 0x20 );
91 it_sio_write (dev, 0xf9 , 0x01 );
92 ite_exit_conf (dev);
93}
94
Kyösti Mälkkia7aa57a2017-03-05 14:23:14 +020095void board_BeforeAgesa(struct sysinfo *cb)
Sergej Ivanovd777c782015-04-03 18:10:27 +030096{
97 u32 val, t32;
98 u8 byte;
Antonello Dettori97c460a2016-09-02 09:12:20 +020099 pci_devfn_t dev;
Sergej Ivanovd777c782015-04-03 18:10:27 +0300100 u32 *addr32;
101
102 /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
103 * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
104 * even though the register is not documented in the Kabini BKDG.
105 * Otherwise the serial output is bad code.
106 */
107 outb(0xD2, 0xcd6);
108 outb(0x00, 0xcd7);
109
Sergej Ivanovd777c782015-04-03 18:10:27 +0300110 /* Set LPC decode enables. */
111 pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3);
112 pci_write_config32(dev2, 0x44, 0xff03ffd5);
113
114 hudson_lpc_port80();
115
116 /* Enable the AcpiMmio space */
117 outb(0x24, 0xcd6);
118 outb(0x1, 0xcd7);
119
120 /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
121 addr32 = (u32 *)0xfed80e28;
122 t32 = *addr32;
123 t32 &= 0xfff8ffff;
124 *addr32 = t32;
125
126 /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
127 addr32 = (u32 *)0xfed80e40;
128 t32 = *addr32;
129 t32 &= 0xffffbffb;
130 *addr32 = t32;
131
Kyösti Mälkkia7aa57a2017-03-05 14:23:14 +0200132 /* enable SIO LPC decode */
133 dev = PCI_DEV(0, 0x14, 3);
134 byte = pci_read_config8(dev, 0x48);
135 byte |= 3; /* 2e, 2f */
136 pci_write_config8(dev, 0x48, byte);
Sergej Ivanovd777c782015-04-03 18:10:27 +0300137
Kyösti Mälkkia7aa57a2017-03-05 14:23:14 +0200138 /* enable serial decode */
139 byte = pci_read_config8(dev, 0x44);
140 byte |= (1 << 6); /* 0x3f8 */
141 pci_write_config8(dev, 0x44, byte);
Sergej Ivanovd777c782015-04-03 18:10:27 +0300142
Sergej Ivanovd777c782015-04-03 18:10:27 +0300143 /* This functions configure SIO as it been done under vendor bios */
144 printk(BIOS_DEBUG, "ITE CONFIG ENVC\n");
145 ite_evc_conf(ENVC_DEV);
146 printk(BIOS_DEBUG, "ITE CONFIG GPIO\n");
147 ite_gpio_conf(GPIO_DEV);
148 printk(BIOS_DEBUG, "ITE CONFIG DONE\n");
149
Sergej Ivanovd777c782015-04-03 18:10:27 +0300150
Kyösti Mälkkia7aa57a2017-03-05 14:23:14 +0200151 ite_kill_watchdog(GPIO_DEV);
152 ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
153
154 /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
155 int i;
Elyes HAOUASdb8e8f32018-02-01 09:21:46 +0100156 for (i = 0; i < 200000; i++)
Kyösti Mälkkia7aa57a2017-03-05 14:23:14 +0200157 val = inb(0xcd6);
158
159 outb(0xEA, 0xCD6);
160 outb(0x1, 0xcd7);
161
162 post_code(0x50);
Sergej Ivanovd777c782015-04-03 18:10:27 +0300163}