Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 5 | * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <delay.h> |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 20 | #ifdef __SMM__ |
| 21 | #include <arch/io.h> |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 22 | #include <device/pci_def.h> |
| 23 | #else /* !__SMM__ */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 24 | #include <device/device.h> |
| 25 | #include <device/pci.h> |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 26 | #endif |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 27 | #include "pch.h" |
| 28 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 29 | |
| 30 | int pch_silicon_revision(void) |
| 31 | { |
Felix Held | 82bd0c3 | 2016-08-13 23:27:15 +0200 | [diff] [blame] | 32 | static int pch_revision_id = -1; |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 33 | device_t dev; |
| 34 | |
| 35 | #ifdef __SMM__ |
| 36 | dev = PCI_DEV(0, 0x1f, 0); |
| 37 | #else |
| 38 | dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); |
| 39 | #endif |
| 40 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 41 | if (pch_revision_id < 0) |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 42 | pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 43 | return pch_revision_id; |
| 44 | } |
| 45 | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 46 | int pch_silicon_type(void) |
| 47 | { |
Felix Held | 82bd0c3 | 2016-08-13 23:27:15 +0200 | [diff] [blame] | 48 | static int pch_type = -1; |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 49 | device_t dev; |
| 50 | |
| 51 | #ifdef __SMM__ |
| 52 | dev = PCI_DEV(0, 0x1f, 0); |
| 53 | #else |
| 54 | dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); |
| 55 | #endif |
| 56 | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 57 | if (pch_type < 0) |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 58 | pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1); |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 59 | return pch_type; |
| 60 | } |
| 61 | |
| 62 | int pch_silicon_supported(int type, int rev) |
| 63 | { |
| 64 | int cur_type = pch_silicon_type(); |
| 65 | int cur_rev = pch_silicon_revision(); |
| 66 | |
| 67 | switch (type) { |
| 68 | case PCH_TYPE_CPT: |
| 69 | /* CougarPoint minimum revision */ |
| 70 | if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) |
| 71 | return 1; |
| 72 | /* PantherPoint any revision */ |
| 73 | if (cur_type == PCH_TYPE_PPT) |
| 74 | return 1; |
| 75 | break; |
| 76 | |
| 77 | case PCH_TYPE_PPT: |
| 78 | /* PantherPoint minimum revision */ |
| 79 | if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) |
| 80 | return 1; |
| 81 | break; |
| 82 | } |
| 83 | |
| 84 | return 0; |
| 85 | } |
| 86 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 87 | #define IOBP_RETRY 1000 |
| 88 | static inline int iobp_poll(void) |
| 89 | { |
| 90 | unsigned try = IOBP_RETRY; |
| 91 | u32 data; |
| 92 | |
| 93 | while (try--) { |
| 94 | data = RCBA32(IOBPS); |
| 95 | if ((data & 1) == 0) |
| 96 | return 1; |
| 97 | udelay(10); |
| 98 | } |
| 99 | |
| 100 | printk(BIOS_ERR, "IOBP timeout\n"); |
| 101 | return 0; |
| 102 | } |
| 103 | |
| 104 | void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) |
| 105 | { |
| 106 | u32 data; |
| 107 | |
| 108 | /* Set the address */ |
| 109 | RCBA32(IOBPIRI) = address; |
| 110 | |
| 111 | /* READ OPCODE */ |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 112 | if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 113 | RCBA32(IOBPS) = IOBPS_RW_BX; |
| 114 | else |
| 115 | RCBA32(IOBPS) = IOBPS_READ_AX; |
| 116 | if (!iobp_poll()) |
| 117 | return; |
| 118 | |
| 119 | /* Read IOBP data */ |
| 120 | data = RCBA32(IOBPD); |
| 121 | if (!iobp_poll()) |
| 122 | return; |
| 123 | |
| 124 | /* Check for successful transaction */ |
| 125 | if ((RCBA32(IOBPS) & 0x6) != 0) { |
| 126 | printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address); |
| 127 | return; |
| 128 | } |
| 129 | |
| 130 | /* Update the data */ |
| 131 | data &= andvalue; |
| 132 | data |= orvalue; |
| 133 | |
| 134 | /* WRITE OPCODE */ |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 135 | if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 136 | RCBA32(IOBPS) = IOBPS_RW_BX; |
| 137 | else |
| 138 | RCBA32(IOBPS) = IOBPS_WRITE_AX; |
| 139 | if (!iobp_poll()) |
| 140 | return; |
| 141 | |
| 142 | /* Write IOBP data */ |
| 143 | RCBA32(IOBPD) = data; |
| 144 | if (!iobp_poll()) |
| 145 | return; |
| 146 | } |
| 147 | |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 148 | #ifndef __SMM__ |
| 149 | /* Set bit in Function Disble register to hide this device */ |
| 150 | static void pch_hide_devfn(unsigned devfn) |
| 151 | { |
| 152 | switch (devfn) { |
| 153 | case PCI_DEVFN(22, 0): /* MEI #1 */ |
| 154 | RCBA32_OR(FD2, PCH_DISABLE_MEI1); |
| 155 | break; |
| 156 | case PCI_DEVFN(22, 1): /* MEI #2 */ |
| 157 | RCBA32_OR(FD2, PCH_DISABLE_MEI2); |
| 158 | break; |
| 159 | case PCI_DEVFN(22, 2): /* IDE-R */ |
| 160 | RCBA32_OR(FD2, PCH_DISABLE_IDER); |
| 161 | break; |
| 162 | case PCI_DEVFN(22, 3): /* KT */ |
| 163 | RCBA32_OR(FD2, PCH_DISABLE_KT); |
| 164 | break; |
| 165 | case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ |
| 166 | RCBA32_OR(BUC, PCH_DISABLE_GBE); |
| 167 | break; |
| 168 | case PCI_DEVFN(26, 0): /* EHCI #2 */ |
| 169 | RCBA32_OR(FD, PCH_DISABLE_EHCI2); |
| 170 | break; |
| 171 | case PCI_DEVFN(27, 0): /* HD Audio Controller */ |
| 172 | RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO); |
| 173 | break; |
| 174 | case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */ |
| 175 | case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */ |
| 176 | case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */ |
| 177 | case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */ |
| 178 | case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */ |
| 179 | case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */ |
| 180 | case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */ |
| 181 | case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */ |
| 182 | RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(devfn))); |
| 183 | break; |
| 184 | case PCI_DEVFN(29, 0): /* EHCI #1 */ |
| 185 | RCBA32_OR(FD, PCH_DISABLE_EHCI1); |
| 186 | break; |
| 187 | case PCI_DEVFN(30, 0): /* PCI-to-PCI Bridge */ |
| 188 | RCBA32_OR(FD, PCH_DISABLE_P2P); |
| 189 | break; |
| 190 | case PCI_DEVFN(31, 0): /* LPC */ |
| 191 | RCBA32_OR(FD, PCH_DISABLE_LPC); |
| 192 | break; |
| 193 | case PCI_DEVFN(31, 2): /* SATA #1 */ |
| 194 | RCBA32_OR(FD, PCH_DISABLE_SATA1); |
| 195 | break; |
| 196 | case PCI_DEVFN(31, 3): /* SMBUS */ |
| 197 | RCBA32_OR(FD, PCH_DISABLE_SMBUS); |
| 198 | break; |
| 199 | case PCI_DEVFN(31, 5): /* SATA #22 */ |
| 200 | RCBA32_OR(FD, PCH_DISABLE_SATA2); |
| 201 | break; |
| 202 | case PCI_DEVFN(31, 6): /* Thermal Subsystem */ |
| 203 | RCBA32_OR(FD, PCH_DISABLE_THERMAL); |
| 204 | break; |
| 205 | } |
| 206 | } |
| 207 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 208 | /* Check if any port in set X to X+3 is enabled */ |
| 209 | static int pch_pcie_check_set_enabled(device_t dev) |
| 210 | { |
| 211 | device_t port; |
| 212 | int port_func; |
| 213 | int dev_func = PCI_FUNC(dev->path.pci.devfn); |
| 214 | |
| 215 | printk(BIOS_DEBUG, "%s: check set enabled\n", dev_path(dev)); |
| 216 | |
| 217 | /* Go through static device tree list of devices |
| 218 | * because enumeration is still in progress */ |
| 219 | for (port = all_devices; port; port = port->next) { |
| 220 | /* Only care about PCIe root ports */ |
| 221 | if (PCI_SLOT(port->path.pci.devfn) != |
| 222 | PCI_SLOT(dev->path.pci.devfn)) |
| 223 | continue; |
| 224 | |
| 225 | /* Check if port is in range and enabled */ |
| 226 | port_func = PCI_FUNC(port->path.pci.devfn); |
| 227 | if (port_func >= dev_func && |
| 228 | port_func < (dev_func + 4) && |
| 229 | port->enabled) |
| 230 | return 1; |
| 231 | } |
| 232 | |
| 233 | /* None of the ports in this set are enabled */ |
| 234 | return 0; |
| 235 | } |
| 236 | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 237 | /* RPFN is a write-once register so keep a copy until it is written */ |
| 238 | static u32 new_rpfn; |
| 239 | |
| 240 | /* Swap function numbers assigned to two PCIe Root Ports */ |
| 241 | static void pch_pcie_function_swap(u8 old_fn, u8 new_fn) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 242 | { |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 243 | u32 old_rpfn = new_rpfn; |
| 244 | |
| 245 | printk(BIOS_DEBUG, "PCH: Remap PCIe function %d to %d\n", |
| 246 | old_fn, new_fn); |
| 247 | |
| 248 | new_rpfn &= ~(RPFN_FNMASK(old_fn) | RPFN_FNMASK(new_fn)); |
| 249 | |
| 250 | /* Old function set to new function and disabled */ |
| 251 | new_rpfn |= RPFN_FNSET(old_fn, RPFN_FNGET(old_rpfn, new_fn)); |
| 252 | new_rpfn |= RPFN_FNSET(new_fn, RPFN_FNGET(old_rpfn, old_fn)); |
| 253 | } |
| 254 | |
| 255 | /* Update devicetree with new Root Port function number assignment */ |
| 256 | static void pch_pcie_devicetree_update(void) |
| 257 | { |
| 258 | device_t dev; |
| 259 | |
| 260 | /* Update the function numbers in the static devicetree */ |
| 261 | for (dev = all_devices; dev; dev = dev->next) { |
| 262 | u8 new_devfn; |
| 263 | |
| 264 | /* Only care about PCH PCIe root ports */ |
| 265 | if (PCI_SLOT(dev->path.pci.devfn) != |
| 266 | PCH_PCIE_DEV_SLOT) |
| 267 | continue; |
| 268 | |
| 269 | /* Determine the new devfn for this port */ |
| 270 | new_devfn = PCI_DEVFN(PCH_PCIE_DEV_SLOT, |
| 271 | RPFN_FNGET(new_rpfn, |
| 272 | PCI_FUNC(dev->path.pci.devfn))); |
| 273 | |
| 274 | if (dev->path.pci.devfn != new_devfn) { |
| 275 | printk(BIOS_DEBUG, |
| 276 | "PCH: PCIe map %02x.%1x -> %02x.%1x\n", |
| 277 | PCI_SLOT(dev->path.pci.devfn), |
| 278 | PCI_FUNC(dev->path.pci.devfn), |
| 279 | PCI_SLOT(new_devfn), PCI_FUNC(new_devfn)); |
| 280 | |
| 281 | dev->path.pci.devfn = new_devfn; |
| 282 | } |
| 283 | } |
| 284 | } |
| 285 | |
| 286 | /* Special handling for PCIe Root Port devices */ |
| 287 | static void pch_pcie_enable(device_t dev) |
| 288 | { |
| 289 | struct southbridge_intel_bd82x6x_config *config = dev->chip_info; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 290 | u32 reg32; |
| 291 | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 292 | /* |
| 293 | * Save a copy of the Root Port Function Number map when |
| 294 | * starting to walk the list of PCIe Root Ports so it can |
| 295 | * be updated locally and written out when the last port |
| 296 | * has been processed. |
| 297 | */ |
| 298 | if (PCI_FUNC(dev->path.pci.devfn) == 0) { |
| 299 | new_rpfn = RCBA32(RPFN); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 300 | |
| 301 | /* |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 302 | * Enable Root Port coalescing if the first port is disabled |
| 303 | * or the other devices will not be enumerated by the OS. |
| 304 | */ |
| 305 | if (!dev->enabled) |
| 306 | config->pcie_port_coalesce = 1; |
| 307 | |
| 308 | if (config->pcie_port_coalesce) |
| 309 | printk(BIOS_INFO, |
| 310 | "PCH: PCIe Root Port coalescing is enabled\n"); |
| 311 | } |
| 312 | |
| 313 | if (!dev->enabled) { |
Marc Jones | ef6b08c | 2012-06-15 23:03:15 -0600 | [diff] [blame] | 314 | printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); |
| 315 | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 316 | /* |
| 317 | * PCIE Power Savings for PantherPoint and CougarPoint/B1+ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 318 | * |
| 319 | * If PCIe 0-3 disabled set Function 0 0xE2[0] = 1 |
| 320 | * If PCIe 4-7 disabled set Function 4 0xE2[0] = 1 |
| 321 | * |
| 322 | * This check is done here instead of pcie driver |
| 323 | * because the pcie driver enable() handler is not |
| 324 | * called unless the device is enabled. |
| 325 | */ |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 326 | if ((PCI_FUNC(dev->path.pci.devfn) == 0 || |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 327 | PCI_FUNC(dev->path.pci.devfn) == 4)) { |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 328 | /* Handle workaround for PPT and CPT/B1+ */ |
| 329 | if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B1) && |
| 330 | !pch_pcie_check_set_enabled(dev)) { |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 331 | u8 reg8 = pci_read_config8(dev, 0xe2); |
| 332 | reg8 |= 1; |
| 333 | pci_write_config8(dev, 0xe2, reg8); |
| 334 | } |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 335 | |
| 336 | /* |
| 337 | * Enable Clock Gating for shared PCIe resources |
| 338 | * before disabling this particular port. |
| 339 | */ |
| 340 | pci_write_config8(dev, 0xe1, 0x3c); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 341 | } |
| 342 | |
| 343 | /* Ensure memory, io, and bus master are all disabled */ |
| 344 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 345 | reg32 &= ~(PCI_COMMAND_MASTER | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 346 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 347 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 348 | |
| 349 | /* Do not claim downstream transactions for PCIe ports */ |
| 350 | new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); |
| 351 | |
| 352 | /* Hide this device if possible */ |
| 353 | pch_hide_devfn(dev->path.pci.devfn); |
| 354 | } else { |
| 355 | int fn; |
| 356 | |
| 357 | /* |
| 358 | * Check if there is a lower disabled port to swap with this |
| 359 | * port in order to maintain linear order starting at zero. |
| 360 | */ |
| 361 | if (config->pcie_port_coalesce) { |
| 362 | for (fn=0; fn < PCI_FUNC(dev->path.pci.devfn); fn++) { |
| 363 | if (!(new_rpfn & RPFN_HIDE(fn))) |
| 364 | continue; |
| 365 | |
| 366 | /* Swap places with this function */ |
| 367 | pch_pcie_function_swap( |
| 368 | PCI_FUNC(dev->path.pci.devfn), fn); |
| 369 | break; |
| 370 | } |
| 371 | } |
| 372 | |
| 373 | /* Enable SERR */ |
| 374 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 375 | reg32 |= PCI_COMMAND_SERR; |
| 376 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 377 | } |
| 378 | |
| 379 | /* |
| 380 | * When processing the last PCIe root port we can now |
| 381 | * update the Root Port Function Number and Hide register. |
| 382 | */ |
| 383 | if (PCI_FUNC(dev->path.pci.devfn) == 7) { |
| 384 | printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", |
| 385 | RCBA32(RPFN), new_rpfn); |
| 386 | RCBA32(RPFN) = new_rpfn; |
| 387 | |
| 388 | /* Update static devictree with new function numbers */ |
| 389 | if (config->pcie_port_coalesce) |
| 390 | pch_pcie_devicetree_update(); |
| 391 | } |
| 392 | } |
| 393 | |
| 394 | void pch_enable(device_t dev) |
| 395 | { |
| 396 | u32 reg32; |
| 397 | |
| 398 | /* PCH PCIe Root Ports get special handling */ |
| 399 | if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT) |
| 400 | return pch_pcie_enable(dev); |
| 401 | |
| 402 | if (!dev->enabled) { |
| 403 | printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); |
| 404 | |
| 405 | /* Ensure memory, io, and bus master are all disabled */ |
| 406 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 407 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 408 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 409 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 410 | |
| 411 | /* Hide this device if possible */ |
| 412 | pch_hide_devfn(dev->path.pci.devfn); |
| 413 | } else { |
| 414 | /* Enable SERR */ |
| 415 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 416 | reg32 |= PCI_COMMAND_SERR; |
| 417 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 418 | } |
| 419 | } |
| 420 | |
| 421 | struct chip_operations southbridge_intel_bd82x6x_ops = { |
Stefan Reinauer | 9ca1c0a | 2012-07-25 16:10:36 -0700 | [diff] [blame] | 422 | CHIP_NAME("Intel Series 6/7 (Cougar Point/Panther Point) Southbridge") |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 423 | .enable_dev = pch_enable, |
| 424 | }; |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 425 | #endif |