| Seunghwan Kim | e5a9e60 | 2018-06-15 10:20:25 +0900 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2018 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <boardid.h> |
| 17 | #include <baseboard/variants.h> |
| 18 | #include <chip.h> |
| 19 | #include <device/device.h> |
| 20 | #include <variant/sku.h> |
| 21 | |
| 22 | uint32_t variant_board_sku(void) |
| 23 | { |
| 24 | static uint32_t sku_id = SKU_UNKNOWN; |
| 25 | |
| 26 | if (sku_id != SKU_UNKNOWN) |
| 27 | return sku_id; |
| 28 | |
| 29 | if (board_id() < 9) |
| 30 | sku_id = SKU_0_NAUTILUS; |
| 31 | else |
| 32 | sku_id = SKU_1_NAUTILUS_LTE; |
| 33 | |
| 34 | return sku_id; |
| 35 | } |
| 36 | |
| 37 | /* Override dev tree settings per board */ |
| 38 | void variant_devtree_update(void) |
| 39 | { |
| 40 | uint32_t sku_id = variant_board_sku(); |
| 41 | struct device *root = SA_DEV_ROOT; |
| 42 | config_t *cfg = root->chip_info; |
| 43 | |
| 44 | switch (sku_id) { |
| 45 | case SKU_0_NAUTILUS: |
| 46 | /* Disable LTE module */ |
| 47 | cfg->usb3_ports[3].enable = 0; |
| 48 | break; |
| 49 | |
| 50 | case SKU_1_NAUTILUS_LTE: |
| 51 | /* LTE board has different layout with Wifi sku, it need |
| 52 | new USB2 port strength settings */ |
| 53 | |
| 54 | /* Configure USB2 port 0 - USB2_PORT_TYPE_C(OC1) */ |
| 55 | cfg->usb2_ports[0].enable = 1; |
| 56 | cfg->usb2_ports[0].ocpin = OC1; |
| 57 | cfg->usb2_ports[0].tx_bias = USB2_BIAS_0MV; |
| 58 | cfg->usb2_ports[0].tx_emp_enable = USB2_PRE_EMP_ON; |
| 59 | cfg->usb2_ports[0].pre_emp_bias = USB2_BIAS_56MV; |
| 60 | cfg->usb2_ports[0].pre_emp_bit = USB2_HALF_BIT_PRE_EMP; |
| 61 | |
| 62 | /* Configure USB2 port 1 - USB2_PORT_LONG(OC2) */ |
| 63 | cfg->usb2_ports[1].enable = 1; |
| 64 | cfg->usb2_ports[1].ocpin = OC2; |
| 65 | cfg->usb2_ports[1].tx_bias = USB2_BIAS_39MV; |
| 66 | cfg->usb2_ports[1].tx_emp_enable = USB2_PRE_EMP_ON; |
| 67 | cfg->usb2_ports[1].pre_emp_bias = USB2_BIAS_56MV; |
| 68 | cfg->usb2_ports[1].pre_emp_bit = USB2_HALF_BIT_PRE_EMP; |
| 69 | |
| 70 | /* Configure USB2 port 4 - USB2_PORT_TYPE_C(OC0) */ |
| 71 | cfg->usb2_ports[4].enable = 1; |
| 72 | cfg->usb2_ports[4].ocpin = OC0; |
| 73 | cfg->usb2_ports[4].tx_bias = USB2_BIAS_0MV; |
| 74 | cfg->usb2_ports[4].tx_emp_enable = USB2_PRE_EMP_ON; |
| 75 | cfg->usb2_ports[4].pre_emp_bias = USB2_BIAS_56MV; |
| 76 | cfg->usb2_ports[4].pre_emp_bit = USB2_HALF_BIT_PRE_EMP; |
| 77 | break; |
| 78 | |
| 79 | default: |
| 80 | break; |
| 81 | } |
| 82 | } |