Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Subrata Banik | 01ae11b | 2017-03-04 23:32:41 +0530 | [diff] [blame] | 2 | |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 3 | #include <cbmem.h> |
Subrata Banik | b6df6b0 | 2020-01-03 15:29:02 +0530 | [diff] [blame] | 4 | #include <console/console.h> |
Furquan Shaikh | cc35f72 | 2020-05-12 16:25:31 -0700 | [diff] [blame] | 5 | #include <cpu/cpu.h> |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
| 8 | #include <device/pci_ids.h> |
Werner Zeh | d12530c | 2018-12-14 13:09:12 +0100 | [diff] [blame] | 9 | #include <intelblocks/acpi.h> |
Subrata Banik | b6df6b0 | 2020-01-03 15:29:02 +0530 | [diff] [blame] | 10 | #include <intelblocks/cfg.h> |
Subrata Banik | 01ae11b | 2017-03-04 23:32:41 +0530 | [diff] [blame] | 11 | #include <intelblocks/systemagent.h> |
Lijian Zhao | 357e552 | 2019-04-11 13:07:00 -0700 | [diff] [blame] | 12 | #include <smbios.h> |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 13 | #include <soc/iomap.h> |
Kyösti Mälkki | d6c5714 | 2020-12-21 15:17:01 +0200 | [diff] [blame] | 14 | #include <soc/nvs.h> |
Subrata Banik | 01ae11b | 2017-03-04 23:32:41 +0530 | [diff] [blame] | 15 | #include <soc/pci_devs.h> |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 16 | #include <soc/systemagent.h> |
Patrick Rudolph | 5e00780 | 2020-07-27 15:37:43 +0200 | [diff] [blame] | 17 | #include <types.h> |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 18 | #include "systemagent_def.h" |
Subrata Banik | 01ae11b | 2017-03-04 23:32:41 +0530 | [diff] [blame] | 19 | |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 20 | /* SoC override function */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 21 | __weak void soc_systemagent_init(struct device *dev) |
Subrata Banik | 01ae11b | 2017-03-04 23:32:41 +0530 | [diff] [blame] | 22 | { |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 23 | /* no-op */ |
Subrata Banik | 01ae11b | 2017-03-04 23:32:41 +0530 | [diff] [blame] | 24 | } |
| 25 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 26 | __weak void soc_add_fixed_mmio_resources(struct device *dev, |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 27 | int *resource_cnt) |
| 28 | { |
| 29 | /* no-op */ |
| 30 | } |
| 31 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 32 | __weak int soc_get_uncore_prmmr_base_and_mask(uint64_t *base, |
Pratik Prajapati | 82cdfa7 | 2017-08-28 14:48:55 -0700 | [diff] [blame] | 33 | uint64_t *mask) |
| 34 | { |
| 35 | /* return failure for this dummy API */ |
| 36 | return -1; |
| 37 | } |
| 38 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 39 | __weak unsigned long sa_write_acpi_tables(const struct device *dev, |
Werner Zeh | d12530c | 2018-12-14 13:09:12 +0100 | [diff] [blame] | 40 | unsigned long current, |
| 41 | struct acpi_rsdp *rsdp) |
| 42 | { |
| 43 | return current; |
| 44 | } |
| 45 | |
Patrick Rudolph | bf72dcb | 2020-05-12 16:04:47 +0200 | [diff] [blame] | 46 | __weak uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) |
| 47 | { |
| 48 | return 32768; /* 32 GiB per channel */ |
| 49 | } |
| 50 | |
Angel Pons | 6724ba4 | 2021-01-31 15:06:59 +0100 | [diff] [blame] | 51 | static uint8_t sa_get_ecc_type(const uint32_t capid0_a) |
Patrick Rudolph | 5e00780 | 2020-07-27 15:37:43 +0200 | [diff] [blame] | 52 | { |
Angel Pons | 6724ba4 | 2021-01-31 15:06:59 +0100 | [diff] [blame] | 53 | return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT; |
Patrick Rudolph | 5e00780 | 2020-07-27 15:37:43 +0200 | [diff] [blame] | 54 | } |
| 55 | |
| 56 | static size_t sa_slots_per_channel(const uint32_t capid0_a) |
| 57 | { |
| 58 | return !(capid0_a & CAPID_DDPCD) + 1; |
| 59 | } |
| 60 | |
| 61 | static size_t sa_number_of_channels(const uint32_t capid0_a) |
| 62 | { |
| 63 | return !(capid0_a & CAPID_PDCD) + 1; |
| 64 | } |
| 65 | |
| 66 | static void sa_soc_systemagent_init(struct device *dev) |
| 67 | { |
| 68 | soc_systemagent_init(dev); |
| 69 | |
| 70 | struct memory_info *m = cbmem_find(CBMEM_ID_MEMINFO); |
| 71 | if (m == NULL) |
| 72 | return; |
| 73 | |
| 74 | const uint32_t capid0_a = pci_read_config32(dev, CAPID0_A); |
| 75 | |
Angel Pons | 6724ba4 | 2021-01-31 15:06:59 +0100 | [diff] [blame] | 76 | m->ecc_type = sa_get_ecc_type(capid0_a); |
Patrick Rudolph | 5e00780 | 2020-07-27 15:37:43 +0200 | [diff] [blame] | 77 | m->max_capacity_mib = soc_systemagent_max_chan_capacity_mib(CAPID_DDRSZ(capid0_a)) * |
| 78 | sa_number_of_channels(capid0_a); |
| 79 | m->number_of_devices = sa_slots_per_channel(capid0_a) * |
| 80 | sa_number_of_channels(capid0_a); |
| 81 | } |
| 82 | |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 83 | /* |
| 84 | * Add all known fixed MMIO ranges that hang off the host bridge/memory |
| 85 | * controller device. |
| 86 | */ |
| 87 | void sa_add_fixed_mmio_resources(struct device *dev, int *resource_cnt, |
| 88 | const struct sa_mmio_descriptor *sa_fixed_resources, size_t count) |
| 89 | { |
| 90 | int i; |
| 91 | int index = *resource_cnt; |
| 92 | |
| 93 | for (i = 0; i < count; i++) { |
| 94 | uintptr_t base; |
| 95 | size_t size; |
| 96 | |
| 97 | size = sa_fixed_resources[i].size; |
| 98 | base = sa_fixed_resources[i].base; |
| 99 | |
| 100 | mmio_resource(dev, index++, base / KiB, size / KiB); |
| 101 | } |
| 102 | |
| 103 | *resource_cnt = index; |
| 104 | } |
| 105 | |
| 106 | /* |
| 107 | * DRAM memory mapped register |
| 108 | * |
| 109 | * TOUUD: This 64 bit register defines the Top of Upper Usable DRAM |
| 110 | * TOLUD: This 32 bit register defines the Top of Low Usable DRAM |
| 111 | * BGSM: This register contains the base address of stolen DRAM memory for GTT |
| 112 | * TSEG: This register contains the base address of TSEG DRAM memory |
| 113 | */ |
| 114 | static const struct sa_mem_map_descriptor sa_memory_map[MAX_MAP_ENTRIES] = { |
| 115 | { TOUUD, true, "TOUUD" }, |
| 116 | { TOLUD, false, "TOLUD" }, |
| 117 | { BGSM, false, "BGSM" }, |
| 118 | { TSEG, false, "TSEG" }, |
| 119 | }; |
| 120 | |
| 121 | /* Read DRAM memory map register value through PCI configuration space */ |
Elyes HAOUAS | 4a13126 | 2018-09-16 17:35:48 +0200 | [diff] [blame] | 122 | static void sa_read_map_entry(struct device *dev, |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 123 | const struct sa_mem_map_descriptor *entry, uint64_t *result) |
| 124 | { |
| 125 | uint64_t value = 0; |
| 126 | |
| 127 | if (entry->is_64_bit) { |
| 128 | value = pci_read_config32(dev, entry->reg + 4); |
| 129 | value <<= 32; |
| 130 | } |
| 131 | |
| 132 | value |= pci_read_config32(dev, entry->reg); |
| 133 | /* All registers are on a 1MiB granularity. */ |
| 134 | value = ALIGN_DOWN(value, 1 * MiB); |
| 135 | |
| 136 | *result = value; |
| 137 | } |
| 138 | |
Furquan Shaikh | 1085fee | 2020-05-07 16:04:16 -0700 | [diff] [blame] | 139 | /* Fill MMIO resource above 4GB into GNVS */ |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 140 | void sa_fill_gnvs(struct global_nvs *gnvs) |
Furquan Shaikh | 1085fee | 2020-05-07 16:04:16 -0700 | [diff] [blame] | 141 | { |
Furquan Shaikh | 1085fee | 2020-05-07 16:04:16 -0700 | [diff] [blame] | 142 | struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
| 143 | |
Furquan Shaikh | 1085fee | 2020-05-07 16:04:16 -0700 | [diff] [blame] | 144 | sa_read_map_entry(sa_dev, &sa_memory_map[SA_TOUUD_REG], &gnvs->a4gb); |
Furquan Shaikh | cc35f72 | 2020-05-12 16:25:31 -0700 | [diff] [blame] | 145 | gnvs->a4gs = POWER_OF_2(cpu_phys_address_size()) - gnvs->a4gb; |
| 146 | printk(BIOS_DEBUG, "PCI space above 4GB MMIO is at 0x%llx, len = 0x%llx\n", |
Furquan Shaikh | 1085fee | 2020-05-07 16:04:16 -0700 | [diff] [blame] | 147 | gnvs->a4gb, gnvs->a4gs); |
| 148 | } |
| 149 | |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 150 | static void sa_get_mem_map(struct device *dev, uint64_t *values) |
| 151 | { |
| 152 | int i; |
| 153 | for (i = 0; i < MAX_MAP_ENTRIES; i++) |
| 154 | sa_read_map_entry(dev, &sa_memory_map[i], &values[i]); |
| 155 | } |
| 156 | |
| 157 | /* |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 158 | * These are the host memory ranges that should be added: |
| 159 | * - 0 -> 0xa0000: cacheable |
| 160 | * - 0xc0000 -> top_of_ram : cacheable |
Subrata Banik | 239272e | 2020-07-29 11:01:26 +0530 | [diff] [blame] | 161 | * - top_of_ram -> TOLUD: not cacheable with standard MTRRs and reserved |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 162 | * - 4GiB -> TOUUD: cacheable |
| 163 | * |
| 164 | * The default SMRAM space is reserved so that the range doesn't |
| 165 | * have to be saved during S3 Resume. Once marked reserved the OS |
| 166 | * cannot use the memory. This is a bit of an odd place to reserve |
| 167 | * the region, but the CPU devices don't have dev_ops->read_resources() |
| 168 | * called on them. |
| 169 | * |
| 170 | * The range 0xa0000 -> 0xc0000 does not have any resources |
| 171 | * associated with it to handle legacy VGA memory. If this range |
| 172 | * is not omitted the mtrr code will setup the area as cacheable |
| 173 | * causing VGA access to not work. |
| 174 | * |
Subrata Banik | 239272e | 2020-07-29 11:01:26 +0530 | [diff] [blame] | 175 | * Don't need to mark the entire top_of_ram till TOLUD range (used |
| 176 | * for stolen memory like GFX and ME, PTT, DPR, PRMRR, TSEG etc) as |
| 177 | * cacheable for OS usage as coreboot already done with mpinit w/ smm |
| 178 | * relocation early. |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 179 | * |
| 180 | * It should be noted that cacheable entry types need to be added in |
| 181 | * order. The reason is that the current MTRR code assumes this and |
| 182 | * falls over itself if it isn't. |
| 183 | * |
| 184 | * The resource index starts low and should not meet or exceed |
| 185 | * PCI_BASE_ADDRESS_0. |
| 186 | */ |
| 187 | static void sa_add_dram_resources(struct device *dev, int *resource_count) |
| 188 | { |
| 189 | uintptr_t base_k, touud_k; |
Michael Niewöhner | 40f893e | 2019-10-21 18:58:04 +0200 | [diff] [blame] | 190 | size_t size_k; |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 191 | uint64_t sa_map_values[MAX_MAP_ENTRIES]; |
| 192 | uintptr_t top_of_ram; |
| 193 | int index = *resource_count; |
| 194 | |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 195 | top_of_ram = (uintptr_t)cbmem_top(); |
| 196 | |
| 197 | /* 0 - > 0xa0000 */ |
| 198 | base_k = 0; |
| 199 | size_k = (0xa0000 / KiB) - base_k; |
| 200 | ram_resource(dev, index++, base_k, size_k); |
| 201 | |
| 202 | /* 0xc0000 -> top_of_ram */ |
| 203 | base_k = 0xc0000 / KiB; |
| 204 | size_k = (top_of_ram / KiB) - base_k; |
| 205 | ram_resource(dev, index++, base_k, size_k); |
| 206 | |
| 207 | sa_get_mem_map(dev, &sa_map_values[0]); |
| 208 | |
Subrata Banik | 239272e | 2020-07-29 11:01:26 +0530 | [diff] [blame] | 209 | /* top_of_ram -> TOLUD */ |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 210 | base_k = top_of_ram; |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 211 | size_k = sa_map_values[SA_TOLUD_REG] - base_k; |
| 212 | mmio_resource(dev, index++, base_k / KiB, size_k / KiB); |
| 213 | |
| 214 | /* 4GiB -> TOUUD */ |
| 215 | base_k = 4 * (GiB / KiB); /* 4GiB */ |
| 216 | touud_k = sa_map_values[SA_TOUUD_REG] / KiB; |
| 217 | size_k = touud_k - base_k; |
| 218 | if (touud_k > base_k) |
| 219 | ram_resource(dev, index++, base_k, size_k); |
| 220 | |
| 221 | /* |
| 222 | * Reserve everything between A segment and 1MB: |
| 223 | * |
| 224 | * 0xa0000 - 0xbffff: legacy VGA |
| 225 | * 0xc0000 - 0xfffff: RAM |
| 226 | */ |
| 227 | mmio_resource(dev, index++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB); |
| 228 | reserved_ram_resource(dev, index++, 0xc0000 / KiB, |
| 229 | (1*MiB - 0xc0000) / KiB); |
| 230 | |
| 231 | *resource_count = index; |
| 232 | } |
| 233 | |
| 234 | static bool is_imr_enabled(uint32_t imr_base_reg) |
| 235 | { |
| 236 | return !!(imr_base_reg & (1 << 31)); |
| 237 | } |
| 238 | |
Elyes HAOUAS | 4a13126 | 2018-09-16 17:35:48 +0200 | [diff] [blame] | 239 | static void imr_resource(struct device *dev, int idx, uint32_t base, |
| 240 | uint32_t mask) |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 241 | { |
| 242 | uint32_t base_k, size_k; |
| 243 | /* Bits 28:0 encode the base address bits 38:10, hence the KiB unit. */ |
| 244 | base_k = (base & 0x0fffffff); |
| 245 | /* Bits 28:0 encode the AND mask used for comparison, in KiB. */ |
| 246 | size_k = ((~mask & 0x0fffffff) + 1); |
| 247 | /* |
| 248 | * IMRs sit in lower DRAM. Mark them cacheable, otherwise we run |
| 249 | * out of MTRRs. Memory reserved by IMRs is not usable for host |
| 250 | * so mark it reserved. |
| 251 | */ |
| 252 | reserved_ram_resource(dev, idx, base_k, size_k); |
| 253 | } |
| 254 | |
| 255 | /* |
| 256 | * Add IMR ranges that hang off the host bridge/memory |
Martin Roth | f48acbd | 2020-07-24 12:24:27 -0600 | [diff] [blame] | 257 | * controller device in case CONFIG(SA_ENABLE_IMR) is selected by SoC. |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 258 | */ |
| 259 | static void sa_add_imr_resources(struct device *dev, int *resource_cnt) |
| 260 | { |
| 261 | size_t i, imr_offset; |
| 262 | uint32_t base, mask; |
| 263 | int index = *resource_cnt; |
| 264 | |
| 265 | for (i = 0; i < MCH_NUM_IMRS; i++) { |
| 266 | imr_offset = i * MCH_IMR_PITCH; |
| 267 | base = MCHBAR32(imr_offset + MCH_IMR0_BASE); |
| 268 | mask = MCHBAR32(imr_offset + MCH_IMR0_MASK); |
| 269 | |
| 270 | if (is_imr_enabled(base)) |
| 271 | imr_resource(dev, index++, base, mask); |
| 272 | } |
| 273 | |
| 274 | *resource_cnt = index; |
| 275 | } |
| 276 | |
| 277 | static void systemagent_read_resources(struct device *dev) |
| 278 | { |
| 279 | int index = 0; |
| 280 | |
| 281 | /* Read standard PCI resources. */ |
| 282 | pci_dev_read_resources(dev); |
| 283 | |
| 284 | /* Add all fixed MMIO resources. */ |
| 285 | soc_add_fixed_mmio_resources(dev, &index); |
| 286 | /* Calculate and add DRAM resources. */ |
| 287 | sa_add_dram_resources(dev, &index); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 288 | if (CONFIG(SA_ENABLE_IMR)) |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 289 | /* Add the isolated memory ranges (IMRs). */ |
| 290 | sa_add_imr_resources(dev, &index); |
Furquan Shaikh | b53280a | 2020-11-25 14:30:15 -0800 | [diff] [blame] | 291 | |
| 292 | /* Reserve the window used for extended BIOS decoding. */ |
| 293 | if (CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW)) |
| 294 | mmio_resource(dev, index++, CONFIG_EXT_BIOS_WIN_BASE / KiB, |
| 295 | CONFIG_EXT_BIOS_WIN_SIZE / KiB); |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 296 | } |
| 297 | |
| 298 | void enable_power_aware_intr(void) |
| 299 | { |
| 300 | uint8_t pair; |
| 301 | |
| 302 | /* Enable Power Aware Interrupt Routing */ |
| 303 | pair = MCHBAR8(MCH_PAIR); |
| 304 | pair &= ~0x7; /* Clear 2:0 */ |
| 305 | pair |= 0x4; /* Fixed Priority */ |
| 306 | MCHBAR8(MCH_PAIR) = pair; |
| 307 | } |
| 308 | |
| 309 | static struct device_operations systemagent_ops = { |
Elyes HAOUAS | 1d19127 | 2018-11-27 12:23:48 +0100 | [diff] [blame] | 310 | .read_resources = systemagent_read_resources, |
| 311 | .set_resources = pci_dev_set_resources, |
| 312 | .enable_resources = pci_dev_enable_resources, |
Patrick Rudolph | 5e00780 | 2020-07-27 15:37:43 +0200 | [diff] [blame] | 313 | .init = sa_soc_systemagent_init, |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame] | 314 | .ops_pci = &pci_dev_ops_pci, |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 315 | #if CONFIG(HAVE_ACPI_TABLES) |
Werner Zeh | d12530c | 2018-12-14 13:09:12 +0100 | [diff] [blame] | 316 | .write_acpi_tables = sa_write_acpi_tables, |
| 317 | #endif |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 318 | }; |
| 319 | |
| 320 | static const unsigned short systemagent_ids[] = { |
| 321 | PCI_DEVICE_ID_INTEL_GLK_NB, |
| 322 | PCI_DEVICE_ID_INTEL_APL_NB, |
Lijian Zhao | bbedef9 | 2017-07-29 16:38:38 -0700 | [diff] [blame] | 323 | PCI_DEVICE_ID_INTEL_CNL_ID_U, |
| 324 | PCI_DEVICE_ID_INTEL_CNL_ID_Y, |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 325 | PCI_DEVICE_ID_INTEL_SKL_ID_U, |
| 326 | PCI_DEVICE_ID_INTEL_SKL_ID_Y, |
| 327 | PCI_DEVICE_ID_INTEL_SKL_ID_ULX, |
Maxim Polyakov | dde937c | 2019-09-09 15:50:03 +0300 | [diff] [blame] | 328 | PCI_DEVICE_ID_INTEL_SKL_ID_H_4, |
Keno Fischer | 1044eba | 2019-06-07 01:55:56 -0400 | [diff] [blame] | 329 | PCI_DEVICE_ID_INTEL_SKL_ID_H_2, |
| 330 | PCI_DEVICE_ID_INTEL_SKL_ID_S_2, |
| 331 | PCI_DEVICE_ID_INTEL_SKL_ID_S_4, |
Lean Sheng Tan | 38c3ff7 | 2019-05-27 13:06:35 +0800 | [diff] [blame] | 332 | PCI_DEVICE_ID_INTEL_WHL_ID_W_2, |
| 333 | PCI_DEVICE_ID_INTEL_WHL_ID_W_4, |
Gaggery Tsai | e415a4c | 2018-03-21 22:36:18 +0800 | [diff] [blame] | 334 | PCI_DEVICE_ID_INTEL_KBL_ID_S, |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 335 | PCI_DEVICE_ID_INTEL_SKL_ID_H_EM, |
| 336 | PCI_DEVICE_ID_INTEL_KBL_ID_U, |
| 337 | PCI_DEVICE_ID_INTEL_KBL_ID_Y, |
| 338 | PCI_DEVICE_ID_INTEL_KBL_ID_H, |
| 339 | PCI_DEVICE_ID_INTEL_KBL_U_R, |
V Sowmya | acc2a48 | 2018-01-23 15:27:23 +0530 | [diff] [blame] | 340 | PCI_DEVICE_ID_INTEL_KBL_ID_DT, |
Christian Walter | 3d84038 | 2019-05-17 19:37:16 +0200 | [diff] [blame] | 341 | PCI_DEVICE_ID_INTEL_KBL_ID_DT_2, |
Maulik | fc19ab5 | 2018-01-05 22:40:35 +0530 | [diff] [blame] | 342 | PCI_DEVICE_ID_INTEL_CFL_ID_U, |
Christian Walter | ccac15a | 2019-08-13 09:55:37 +0200 | [diff] [blame] | 343 | PCI_DEVICE_ID_INTEL_CFL_ID_U_2, |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 344 | PCI_DEVICE_ID_INTEL_CFL_ID_H, |
Christian Walter | ccac15a | 2019-08-13 09:55:37 +0200 | [diff] [blame] | 345 | PCI_DEVICE_ID_INTEL_CFL_ID_H_4, |
Lean Sheng Tan | 38c3ff7 | 2019-05-27 13:06:35 +0800 | [diff] [blame] | 346 | PCI_DEVICE_ID_INTEL_CFL_ID_H_8, |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 347 | PCI_DEVICE_ID_INTEL_CFL_ID_S, |
Christian Walter | ccac15a | 2019-08-13 09:55:37 +0200 | [diff] [blame] | 348 | PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2, |
Felix Singer | d298ffe | 2019-07-28 13:27:11 +0200 | [diff] [blame] | 349 | PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4, |
Lean Sheng Tan | 38c3ff7 | 2019-05-27 13:06:35 +0800 | [diff] [blame] | 350 | PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8, |
Christian Walter | ccac15a | 2019-08-13 09:55:37 +0200 | [diff] [blame] | 351 | PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4, |
| 352 | PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6, |
Lean Sheng Tan | 38c3ff7 | 2019-05-27 13:06:35 +0800 | [diff] [blame] | 353 | PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8, |
Christian Walter | ccac15a | 2019-08-13 09:55:37 +0200 | [diff] [blame] | 354 | PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4, |
| 355 | PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6, |
| 356 | PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8, |
Aamir Bohra | 9eac039 | 2018-06-30 12:07:04 +0530 | [diff] [blame] | 357 | PCI_DEVICE_ID_INTEL_ICL_ID_U, |
| 358 | PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2, |
| 359 | PCI_DEVICE_ID_INTEL_ICL_ID_Y, |
| 360 | PCI_DEVICE_ID_INTEL_ICL_ID_Y_2, |
Ronak Kanabar | f606a2f | 2019-02-04 16:06:50 +0530 | [diff] [blame] | 361 | PCI_DEVICE_ID_INTEL_CML_ULT, |
Subrata Banik | ba8af58 | 2019-02-27 15:00:55 +0530 | [diff] [blame] | 362 | PCI_DEVICE_ID_INTEL_CML_ULT_2_2, |
Ronak Kanabar | f606a2f | 2019-02-04 16:06:50 +0530 | [diff] [blame] | 363 | PCI_DEVICE_ID_INTEL_CML_ULT_6_2, |
| 364 | PCI_DEVICE_ID_INTEL_CML_ULX, |
| 365 | PCI_DEVICE_ID_INTEL_CML_S, |
Gaggery Tsai | fdcc9ab | 2019-11-04 20:49:10 -0800 | [diff] [blame] | 366 | PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2, |
| 367 | PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2, |
| 368 | PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2, |
Gaggery Tsai | 39e1f44 | 2020-01-08 15:22:13 -0800 | [diff] [blame] | 369 | PCI_DEVICE_ID_INTEL_CML_S_G0G1_4, |
| 370 | PCI_DEVICE_ID_INTEL_CML_S_G0G1_2, |
Ronak Kanabar | f606a2f | 2019-02-04 16:06:50 +0530 | [diff] [blame] | 371 | PCI_DEVICE_ID_INTEL_CML_H, |
Jamie Chen | 6bb9aaf | 2019-12-20 19:30:33 +0800 | [diff] [blame] | 372 | PCI_DEVICE_ID_INTEL_CML_H_4_2, |
Ronak Kanabar | f606a2f | 2019-02-04 16:06:50 +0530 | [diff] [blame] | 373 | PCI_DEVICE_ID_INTEL_CML_H_8_2, |
Srinidhi N Kaushik | 1d812e8 | 2020-02-07 15:51:09 -0800 | [diff] [blame] | 374 | PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, |
Derek Huang | 60f178d | 2020-07-03 15:33:13 +0800 | [diff] [blame] | 375 | PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2, |
| 376 | PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2, |
| 377 | PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2, |
Jeremy Soller | 191a8d7 | 2021-08-10 14:06:51 -0600 | [diff] [blame] | 378 | PCI_DEVICE_ID_INTEL_TGL_ID_H_6_1, |
| 379 | PCI_DEVICE_ID_INTEL_TGL_ID_H_8_1, |
Tan, Lean Sheng | 8d2177b | 2021-05-23 23:06:43 -0700 | [diff] [blame] | 380 | PCI_DEVICE_ID_INTEL_EHL_ID_0, |
Tan, Lean Sheng | 2613609 | 2020-01-20 19:13:56 -0800 | [diff] [blame] | 381 | PCI_DEVICE_ID_INTEL_EHL_ID_1, |
Tan, Lean Sheng | 8d2177b | 2021-05-23 23:06:43 -0700 | [diff] [blame] | 382 | PCI_DEVICE_ID_INTEL_EHL_ID_1A, |
Tan, Lean Sheng | 21910f00 | 2020-04-29 03:03:27 -0700 | [diff] [blame] | 383 | PCI_DEVICE_ID_INTEL_EHL_ID_2, |
Tan, Lean Sheng | 8d2177b | 2021-05-23 23:06:43 -0700 | [diff] [blame] | 384 | PCI_DEVICE_ID_INTEL_EHL_ID_2_1, |
Tan, Lean Sheng | 21910f00 | 2020-04-29 03:03:27 -0700 | [diff] [blame] | 385 | PCI_DEVICE_ID_INTEL_EHL_ID_3, |
Tan, Lean Sheng | 8d2177b | 2021-05-23 23:06:43 -0700 | [diff] [blame] | 386 | PCI_DEVICE_ID_INTEL_EHL_ID_3A, |
Tan, Lean Sheng | 21910f00 | 2020-04-29 03:03:27 -0700 | [diff] [blame] | 387 | PCI_DEVICE_ID_INTEL_EHL_ID_4, |
| 388 | PCI_DEVICE_ID_INTEL_EHL_ID_5, |
| 389 | PCI_DEVICE_ID_INTEL_EHL_ID_6, |
| 390 | PCI_DEVICE_ID_INTEL_EHL_ID_7, |
| 391 | PCI_DEVICE_ID_INTEL_EHL_ID_8, |
| 392 | PCI_DEVICE_ID_INTEL_EHL_ID_9, |
| 393 | PCI_DEVICE_ID_INTEL_EHL_ID_10, |
| 394 | PCI_DEVICE_ID_INTEL_EHL_ID_11, |
| 395 | PCI_DEVICE_ID_INTEL_EHL_ID_12, |
Tan, Lean Sheng | 8d2177b | 2021-05-23 23:06:43 -0700 | [diff] [blame] | 396 | PCI_DEVICE_ID_INTEL_EHL_ID_13, |
Meera Ravindranath | 3f4af0d | 2020-02-12 16:01:22 +0530 | [diff] [blame] | 397 | PCI_DEVICE_ID_INTEL_JSL_ID_1, |
Maulik V Vaghela | 8745a27 | 2020-04-22 12:13:40 +0530 | [diff] [blame] | 398 | PCI_DEVICE_ID_INTEL_JSL_ID_2, |
| 399 | PCI_DEVICE_ID_INTEL_JSL_ID_3, |
| 400 | PCI_DEVICE_ID_INTEL_JSL_ID_4, |
Krishna Prasad Bhat | 20f580b | 2020-09-17 19:42:39 +0530 | [diff] [blame] | 401 | PCI_DEVICE_ID_INTEL_JSL_ID_5, |
Subrata Banik | f672f7f | 2020-08-03 14:29:25 +0530 | [diff] [blame] | 402 | PCI_DEVICE_ID_INTEL_ADL_S_ID_1, |
| 403 | PCI_DEVICE_ID_INTEL_ADL_S_ID_2, |
| 404 | PCI_DEVICE_ID_INTEL_ADL_S_ID_3, |
| 405 | PCI_DEVICE_ID_INTEL_ADL_S_ID_4, |
| 406 | PCI_DEVICE_ID_INTEL_ADL_S_ID_5, |
| 407 | PCI_DEVICE_ID_INTEL_ADL_S_ID_6, |
| 408 | PCI_DEVICE_ID_INTEL_ADL_S_ID_7, |
| 409 | PCI_DEVICE_ID_INTEL_ADL_S_ID_8, |
| 410 | PCI_DEVICE_ID_INTEL_ADL_S_ID_9, |
| 411 | PCI_DEVICE_ID_INTEL_ADL_S_ID_10, |
| 412 | PCI_DEVICE_ID_INTEL_ADL_S_ID_11, |
| 413 | PCI_DEVICE_ID_INTEL_ADL_S_ID_12, |
| 414 | PCI_DEVICE_ID_INTEL_ADL_S_ID_13, |
| 415 | PCI_DEVICE_ID_INTEL_ADL_S_ID_14, |
| 416 | PCI_DEVICE_ID_INTEL_ADL_S_ID_15, |
| 417 | PCI_DEVICE_ID_INTEL_ADL_P_ID_1, |
Subrata Banik | f672f7f | 2020-08-03 14:29:25 +0530 | [diff] [blame] | 418 | PCI_DEVICE_ID_INTEL_ADL_P_ID_3, |
| 419 | PCI_DEVICE_ID_INTEL_ADL_P_ID_4, |
| 420 | PCI_DEVICE_ID_INTEL_ADL_P_ID_5, |
| 421 | PCI_DEVICE_ID_INTEL_ADL_P_ID_6, |
| 422 | PCI_DEVICE_ID_INTEL_ADL_P_ID_7, |
| 423 | PCI_DEVICE_ID_INTEL_ADL_P_ID_8, |
| 424 | PCI_DEVICE_ID_INTEL_ADL_P_ID_9, |
Sumeet R Pawnikar | dd4861a | 2021-05-19 15:59:55 +0530 | [diff] [blame] | 425 | PCI_DEVICE_ID_INTEL_ADL_M_ID_1, |
Sumeet Pawnikar | 3888292 | 2021-07-29 22:09:14 +0530 | [diff] [blame] | 426 | PCI_DEVICE_ID_INTEL_ADL_M_ID_2, |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 427 | 0 |
| 428 | }; |
| 429 | |
| 430 | static const struct pci_driver systemagent_driver __pci_driver = { |
| 431 | .ops = &systemagent_ops, |
| 432 | .vendor = PCI_VENDOR_ID_INTEL, |
| 433 | .devices = systemagent_ids |
| 434 | }; |