blob: 089a8a99ea85a19175dcfaf431d2e3687f2d1ded [file] [log] [blame]
Ronald G. Minniche0e784a2014-11-26 19:25:47 +00001// See LICENSE for license details.
2
3#ifndef RISCV_CSR_ENCODING_H
4#define RISCV_CSR_ENCODING_H
5
6#define SR_S 0x00000001
7#define SR_PS 0x00000002
8#define SR_EI 0x00000004
9#define SR_PEI 0x00000008
10#define SR_EF 0x00000010
11#define SR_U64 0x00000020
12#define SR_S64 0x00000040
13#define SR_VM 0x00000080
14#define SR_EA 0x00000100
15#define SR_IM 0x00FF0000
16#define SR_IP 0xFF000000
17#define SR_ZERO ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EA|SR_IM|SR_IP)
18#define SR_IM_SHIFT 16
19#define SR_IP_SHIFT 24
20
21#define IRQ_COP 2
22#define IRQ_IPI 5
23#define IRQ_HOST 6
24#define IRQ_TIMER 7
25
26#define IMPL_SPIKE 1
27#define IMPL_ROCKET 2
28
29// page table entry (PTE) fields
30#define PTE_V 0x001 // Entry is a page Table descriptor
31#define PTE_T 0x002 // Entry is a page Table, not a terminal node
32#define PTE_G 0x004 // Global
33#define PTE_UR 0x008 // User Write permission
34#define PTE_UW 0x010 // User Read permission
35#define PTE_UX 0x020 // User eXecute permission
36#define PTE_SR 0x040 // Supervisor Read permission
37#define PTE_SW 0x080 // Supervisor Write permission
38#define PTE_SX 0x100 // Supervisor eXecute permission
39#define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX)
40
41#ifdef __riscv
42
43#ifdef __riscv64
44# define RISCV_PGLEVELS 3
45# define RISCV_PGSHIFT 13
46#else
47# define RISCV_PGLEVELS 2
48# define RISCV_PGSHIFT 12
49#endif
50#define RISCV_PGLEVEL_BITS 10
51#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
52
53#ifndef __ASSEMBLER__
54
55#define read_csr(reg) ({ long __tmp; \
56 asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
57 __tmp; })
58
59#define write_csr(reg, val) \
60 asm volatile ("csrw " #reg ", %0" :: "r"(val))
61
62#define swap_csr(reg, val) ({ long __tmp; \
63 asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
64 __tmp; })
65
66#define set_csr(reg, bit) ({ long __tmp; \
67 if (__builtin_constant_p(bit) && (bit) < 32) \
68 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
69 else \
70 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
71 __tmp; })
72
73#define clear_csr(reg, bit) ({ long __tmp; \
74 if (__builtin_constant_p(bit) && (bit) < 32) \
75 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
76 else \
77 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
78 __tmp; })
79
80#define rdtime() ({ unsigned long __tmp; \
81 asm volatile ("rdtime %0" : "=r"(__tmp)); \
82 __tmp; })
83
84#define rdcycle() ({ unsigned long __tmp; \
85 asm volatile ("rdcycle %0" : "=r"(__tmp)); \
86 __tmp; })
87
88#define rdinstret() ({ unsigned long __tmp; \
89 asm volatile ("rdinstret %0" : "=r"(__tmp)); \
90 __tmp; })
91
92#endif
93
94#endif
95
96#endif
97/* Automatically generated by parse-opcodes */
98#ifndef RISCV_ENCODING_H
99#define RISCV_ENCODING_H
100#define MATCH_FMV_S_X 0xf0000053
101#define MASK_FMV_S_X 0xfff0707f
102#define MATCH_AMOXOR_W 0x2000202f
103#define MASK_AMOXOR_W 0xf800707f
104#define MATCH_REMUW 0x200703b
105#define MASK_REMUW 0xfe00707f
106#define MATCH_FMIN_D 0x2a000053
107#define MASK_FMIN_D 0xfe00707f
108#define MATCH_AMOMAX_D 0xa000302f
109#define MASK_AMOMAX_D 0xf800707f
110#define MATCH_BLTU 0x6063
111#define MASK_BLTU 0x707f
112#define MATCH_FSGNJN_D 0x22001053
113#define MASK_FSGNJN_D 0xfe00707f
114#define MATCH_FMIN_S 0x28000053
115#define MASK_FMIN_S 0xfe00707f
116#define MATCH_CSRRW 0x1073
117#define MASK_CSRRW 0x707f
118#define MATCH_SLLIW 0x101b
119#define MASK_SLLIW 0xfe00707f
120#define MATCH_LB 0x3
121#define MASK_LB 0x707f
122#define MATCH_FMAX_S 0x28001053
123#define MASK_FMAX_S 0xfe00707f
124#define MATCH_LH 0x1003
125#define MASK_LH 0x707f
126#define MATCH_FCVT_D_W 0xd2000053
127#define MASK_FCVT_D_W 0xfff0007f
128#define MATCH_LW 0x2003
129#define MASK_LW 0x707f
130#define MATCH_ADD 0x33
131#define MASK_ADD 0xfe00707f
132#define MATCH_CSRRC 0x3073
133#define MASK_CSRRC 0x707f
134#define MATCH_FMAX_D 0x2a001053
135#define MASK_FMAX_D 0xfe00707f
136#define MATCH_BNE 0x1063
137#define MASK_BNE 0x707f
138#define MATCH_FCVT_S_D 0x40100053
139#define MASK_FCVT_S_D 0xfff0007f
140#define MATCH_BGEU 0x7063
141#define MASK_BGEU 0x707f
142#define MATCH_FADD_D 0x2000053
143#define MASK_FADD_D 0xfe00007f
144#define MATCH_SLTIU 0x3013
145#define MASK_SLTIU 0x707f
146#define MATCH_FADD_S 0x53
147#define MASK_FADD_S 0xfe00007f
148#define MATCH_FCLASS_D 0xe2001053
149#define MASK_FCLASS_D 0xfff0707f
150#define MATCH_FCVT_S_W 0xd0000053
151#define MASK_FCVT_S_W 0xfff0007f
152#define MATCH_MUL 0x2000033
153#define MASK_MUL 0xfe00707f
154#define MATCH_AMOMINU_D 0xc000302f
155#define MASK_AMOMINU_D 0xf800707f
156#define MATCH_FCVT_S_LU 0xd0300053
157#define MASK_FCVT_S_LU 0xfff0007f
158#define MATCH_SRLI 0x5013
159#define MASK_SRLI 0xfc00707f
160#define MATCH_AMOMINU_W 0xc000202f
161#define MASK_AMOMINU_W 0xf800707f
162#define MATCH_DIVUW 0x200503b
163#define MASK_DIVUW 0xfe00707f
164#define MATCH_MULW 0x200003b
165#define MASK_MULW 0xfe00707f
166#define MATCH_SRLW 0x503b
167#define MASK_SRLW 0xfe00707f
168#define MATCH_DIV 0x2004033
169#define MASK_DIV 0xfe00707f
170#define MATCH_FDIV_D 0x1a000053
171#define MASK_FDIV_D 0xfe00007f
172#define MATCH_FENCE 0xf
173#define MASK_FENCE 0x707f
174#define MATCH_FNMSUB_S 0x4b
175#define MASK_FNMSUB_S 0x600007f
176#define MATCH_FCVT_L_S 0xc0200053
177#define MASK_FCVT_L_S 0xfff0007f
178#define MATCH_SBREAK 0x100073
179#define MASK_SBREAK 0xffffffff
180#define MATCH_FLE_S 0xa0000053
181#define MASK_FLE_S 0xfe00707f
182#define MATCH_FDIV_S 0x18000053
183#define MASK_FDIV_S 0xfe00007f
184#define MATCH_FLE_D 0xa2000053
185#define MASK_FLE_D 0xfe00707f
186#define MATCH_FENCE_I 0x100f
187#define MASK_FENCE_I 0x707f
188#define MATCH_FNMSUB_D 0x200004b
189#define MASK_FNMSUB_D 0x600007f
190#define MATCH_ADDW 0x3b
191#define MASK_ADDW 0xfe00707f
192#define MATCH_SLL 0x1033
193#define MASK_SLL 0xfe00707f
194#define MATCH_XOR 0x4033
195#define MASK_XOR 0xfe00707f
196#define MATCH_SUB 0x40000033
197#define MASK_SUB 0xfe00707f
198#define MATCH_BLT 0x4063
199#define MASK_BLT 0x707f
200#define MATCH_SCALL 0x73
201#define MASK_SCALL 0xffffffff
202#define MATCH_FCLASS_S 0xe0001053
203#define MASK_FCLASS_S 0xfff0707f
204#define MATCH_SC_W 0x1800202f
205#define MASK_SC_W 0xf800707f
206#define MATCH_REM 0x2006033
207#define MASK_REM 0xfe00707f
208#define MATCH_SRLIW 0x501b
209#define MASK_SRLIW 0xfe00707f
210#define MATCH_LUI 0x37
211#define MASK_LUI 0x7f
212#define MATCH_CSRRCI 0x7073
213#define MASK_CSRRCI 0x707f
214#define MATCH_ADDI 0x13
215#define MASK_ADDI 0x707f
216#define MATCH_MULH 0x2001033
217#define MASK_MULH 0xfe00707f
218#define MATCH_FMUL_S 0x10000053
219#define MASK_FMUL_S 0xfe00007f
220#define MATCH_CSRRSI 0x6073
221#define MASK_CSRRSI 0x707f
222#define MATCH_SRAI 0x40005013
223#define MASK_SRAI 0xfc00707f
224#define MATCH_AMOAND_D 0x6000302f
225#define MASK_AMOAND_D 0xf800707f
226#define MATCH_FLT_D 0xa2001053
227#define MASK_FLT_D 0xfe00707f
228#define MATCH_SRAW 0x4000503b
229#define MASK_SRAW 0xfe00707f
230#define MATCH_FMUL_D 0x12000053
231#define MASK_FMUL_D 0xfe00007f
232#define MATCH_LD 0x3003
233#define MASK_LD 0x707f
234#define MATCH_ORI 0x6013
235#define MASK_ORI 0x707f
236#define MATCH_CSRRS 0x2073
237#define MASK_CSRRS 0x707f
238#define MATCH_FLT_S 0xa0001053
239#define MASK_FLT_S 0xfe00707f
240#define MATCH_ADDIW 0x1b
241#define MASK_ADDIW 0x707f
242#define MATCH_AMOAND_W 0x6000202f
243#define MASK_AMOAND_W 0xf800707f
244#define MATCH_FEQ_S 0xa0002053
245#define MASK_FEQ_S 0xfe00707f
246#define MATCH_FSGNJX_D 0x22002053
247#define MASK_FSGNJX_D 0xfe00707f
248#define MATCH_SRA 0x40005033
249#define MASK_SRA 0xfe00707f
250#define MATCH_BGE 0x5063
251#define MASK_BGE 0x707f
252#define MATCH_SRAIW 0x4000501b
253#define MASK_SRAIW 0xfe00707f
254#define MATCH_SRL 0x5033
255#define MASK_SRL 0xfe00707f
256#define MATCH_FSUB_D 0xa000053
257#define MASK_FSUB_D 0xfe00007f
258#define MATCH_FSGNJX_S 0x20002053
259#define MASK_FSGNJX_S 0xfe00707f
260#define MATCH_FEQ_D 0xa2002053
261#define MASK_FEQ_D 0xfe00707f
262#define MATCH_FCVT_D_WU 0xd2100053
263#define MASK_FCVT_D_WU 0xfff0007f
264#define MATCH_OR 0x6033
265#define MASK_OR 0xfe00707f
266#define MATCH_FCVT_WU_D 0xc2100053
267#define MASK_FCVT_WU_D 0xfff0007f
268#define MATCH_SUBW 0x4000003b
269#define MASK_SUBW 0xfe00707f
270#define MATCH_FCVT_D_L 0xd2200053
271#define MASK_FCVT_D_L 0xfff0007f
272#define MATCH_AMOMAXU_D 0xe000302f
273#define MASK_AMOMAXU_D 0xf800707f
274#define MATCH_XORI 0x4013
275#define MASK_XORI 0x707f
276#define MATCH_AMOXOR_D 0x2000302f
277#define MASK_AMOXOR_D 0xf800707f
278#define MATCH_AMOMAXU_W 0xe000202f
279#define MASK_AMOMAXU_W 0xf800707f
280#define MATCH_FCVT_WU_S 0xc0100053
281#define MASK_FCVT_WU_S 0xfff0007f
282#define MATCH_ANDI 0x7013
283#define MASK_ANDI 0x707f
284#define MATCH_FMV_X_S 0xe0000053
285#define MASK_FMV_X_S 0xfff0707f
286#define MATCH_SRET 0x80000073
287#define MASK_SRET 0xffffffff
288#define MATCH_FNMADD_S 0x4f
289#define MASK_FNMADD_S 0x600007f
290#define MATCH_JAL 0x6f
291#define MASK_JAL 0x7f
292#define MATCH_LWU 0x6003
293#define MASK_LWU 0x707f
294#define MATCH_FMV_X_D 0xe2000053
295#define MASK_FMV_X_D 0xfff0707f
296#define MATCH_FCVT_D_S 0x42000053
297#define MASK_FCVT_D_S 0xfff0007f
298#define MATCH_FNMADD_D 0x200004f
299#define MASK_FNMADD_D 0x600007f
300#define MATCH_AMOADD_D 0x302f
301#define MASK_AMOADD_D 0xf800707f
302#define MATCH_LR_D 0x1000302f
303#define MASK_LR_D 0xf9f0707f
304#define MATCH_FCVT_W_S 0xc0000053
305#define MASK_FCVT_W_S 0xfff0007f
306#define MATCH_MULHSU 0x2002033
307#define MASK_MULHSU 0xfe00707f
308#define MATCH_AMOADD_W 0x202f
309#define MASK_AMOADD_W 0xf800707f
310#define MATCH_FCVT_D_LU 0xd2300053
311#define MASK_FCVT_D_LU 0xfff0007f
312#define MATCH_LR_W 0x1000202f
313#define MASK_LR_W 0xf9f0707f
314#define MATCH_FCVT_W_D 0xc2000053
315#define MASK_FCVT_W_D 0xfff0007f
316#define MATCH_SLT 0x2033
317#define MASK_SLT 0xfe00707f
318#define MATCH_SLLW 0x103b
319#define MASK_SLLW 0xfe00707f
320#define MATCH_AMOOR_D 0x4000302f
321#define MASK_AMOOR_D 0xf800707f
322#define MATCH_SLTI 0x2013
323#define MASK_SLTI 0x707f
324#define MATCH_REMU 0x2007033
325#define MASK_REMU 0xfe00707f
326#define MATCH_FLW 0x2007
327#define MASK_FLW 0x707f
328#define MATCH_REMW 0x200603b
329#define MASK_REMW 0xfe00707f
330#define MATCH_SLTU 0x3033
331#define MASK_SLTU 0xfe00707f
332#define MATCH_SLLI 0x1013
333#define MASK_SLLI 0xfc00707f
334#define MATCH_AMOOR_W 0x4000202f
335#define MASK_AMOOR_W 0xf800707f
336#define MATCH_BEQ 0x63
337#define MASK_BEQ 0x707f
338#define MATCH_FLD 0x3007
339#define MASK_FLD 0x707f
340#define MATCH_FSUB_S 0x8000053
341#define MASK_FSUB_S 0xfe00007f
342#define MATCH_AND 0x7033
343#define MASK_AND 0xfe00707f
344#define MATCH_FMV_D_X 0xf2000053
345#define MASK_FMV_D_X 0xfff0707f
346#define MATCH_LBU 0x4003
347#define MASK_LBU 0x707f
348#define MATCH_FSGNJ_S 0x20000053
349#define MASK_FSGNJ_S 0xfe00707f
350#define MATCH_AMOMAX_W 0xa000202f
351#define MASK_AMOMAX_W 0xf800707f
352#define MATCH_FSGNJ_D 0x22000053
353#define MASK_FSGNJ_D 0xfe00707f
354#define MATCH_MULHU 0x2003033
355#define MASK_MULHU 0xfe00707f
356#define MATCH_FCVT_L_D 0xc2200053
357#define MASK_FCVT_L_D 0xfff0007f
358#define MATCH_FCVT_S_WU 0xd0100053
359#define MASK_FCVT_S_WU 0xfff0007f
360#define MATCH_FCVT_LU_S 0xc0300053
361#define MASK_FCVT_LU_S 0xfff0007f
362#define MATCH_FCVT_S_L 0xd0200053
363#define MASK_FCVT_S_L 0xfff0007f
364#define MATCH_AUIPC 0x17
365#define MASK_AUIPC 0x7f
366#define MATCH_FCVT_LU_D 0xc2300053
367#define MASK_FCVT_LU_D 0xfff0007f
368#define MATCH_CSRRWI 0x5073
369#define MASK_CSRRWI 0x707f
370#define MATCH_SC_D 0x1800302f
371#define MASK_SC_D 0xf800707f
372#define MATCH_FMADD_S 0x43
373#define MASK_FMADD_S 0x600007f
374#define MATCH_FSQRT_S 0x58000053
375#define MASK_FSQRT_S 0xfff0007f
376#define MATCH_AMOMIN_W 0x8000202f
377#define MASK_AMOMIN_W 0xf800707f
378#define MATCH_FSGNJN_S 0x20001053
379#define MASK_FSGNJN_S 0xfe00707f
380#define MATCH_AMOSWAP_D 0x800302f
381#define MASK_AMOSWAP_D 0xf800707f
382#define MATCH_FSQRT_D 0x5a000053
383#define MASK_FSQRT_D 0xfff0007f
384#define MATCH_FMADD_D 0x2000043
385#define MASK_FMADD_D 0x600007f
386#define MATCH_DIVW 0x200403b
387#define MASK_DIVW 0xfe00707f
388#define MATCH_AMOMIN_D 0x8000302f
389#define MASK_AMOMIN_D 0xf800707f
390#define MATCH_DIVU 0x2005033
391#define MASK_DIVU 0xfe00707f
392#define MATCH_AMOSWAP_W 0x800202f
393#define MASK_AMOSWAP_W 0xf800707f
394#define MATCH_JALR 0x67
395#define MASK_JALR 0x707f
396#define MATCH_FSD 0x3027
397#define MASK_FSD 0x707f
398#define MATCH_SW 0x2023
399#define MASK_SW 0x707f
400#define MATCH_FMSUB_S 0x47
401#define MASK_FMSUB_S 0x600007f
402#define MATCH_LHU 0x5003
403#define MASK_LHU 0x707f
404#define MATCH_SH 0x1023
405#define MASK_SH 0x707f
406#define MATCH_FSW 0x2027
407#define MASK_FSW 0x707f
408#define MATCH_SB 0x23
409#define MASK_SB 0x707f
410#define MATCH_FMSUB_D 0x2000047
411#define MASK_FMSUB_D 0x600007f
412#define MATCH_SD 0x3023
413#define MASK_SD 0x707f
414#define CSR_FFLAGS 0x1
415#define CSR_FRM 0x2
416#define CSR_FCSR 0x3
417#define CSR_STATS 0xc0
418#define CSR_SUP0 0x500
419#define CSR_SUP1 0x501
420#define CSR_EPC 0x502
421#define CSR_BADVADDR 0x503
422#define CSR_PTBR 0x504
423#define CSR_ASID 0x505
424#define CSR_COUNT 0x506
425#define CSR_COMPARE 0x507
426#define CSR_EVEC 0x508
427#define CSR_CAUSE 0x509
428#define CSR_STATUS 0x50a
429#define CSR_HARTID 0x50b
430#define CSR_IMPL 0x50c
431#define CSR_FATC 0x50d
432#define CSR_SEND_IPI 0x50e
433#define CSR_CLEAR_IPI 0x50f
434#define CSR_RESET 0x51d
435#define CSR_TOHOST 0x51e
436#define CSR_FROMHOST 0x51f
437#define CSR_CYCLE 0xc00
438#define CSR_TIME 0xc01
439#define CSR_INSTRET 0xc02
440#define CSR_UARCH0 0xcc0
441#define CSR_UARCH1 0xcc1
442#define CSR_UARCH2 0xcc2
443#define CSR_UARCH3 0xcc3
444#define CSR_UARCH4 0xcc4
445#define CSR_UARCH5 0xcc5
446#define CSR_UARCH6 0xcc6
447#define CSR_UARCH7 0xcc7
448#define CSR_UARCH8 0xcc8
449#define CSR_UARCH9 0xcc9
450#define CSR_UARCH10 0xcca
451#define CSR_UARCH11 0xccb
452#define CSR_UARCH12 0xccc
453#define CSR_UARCH13 0xccd
454#define CSR_UARCH14 0xcce
455#define CSR_UARCH15 0xccf
456#define CSR_COUNTH 0x586
457#define CSR_CYCLEH 0xc80
458#define CSR_TIMEH 0xc81
459#define CSR_INSTRETH 0xc82
460#define CAUSE_MISALIGNED_FETCH 0x0
461#define CAUSE_FAULT_FETCH 0x1
462#define CAUSE_ILLEGAL_INSTRUCTION 0x2
463#define CAUSE_PRIVILEGED_INSTRUCTION 0x3
464#define CAUSE_FP_DISABLED 0x4
465#define CAUSE_SYSCALL 0x6
466#define CAUSE_BREAKPOINT 0x7
467#define CAUSE_MISALIGNED_LOAD 0x8
468#define CAUSE_MISALIGNED_STORE 0x9
469#define CAUSE_FAULT_LOAD 0xa
470#define CAUSE_FAULT_STORE 0xb
471#define CAUSE_ACCELERATOR_DISABLED 0xc
472#endif
473#ifdef DECLARE_INSN
474DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
475DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
476DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
477DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
478DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
479DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
480DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
481DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
482DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
483DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
484DECLARE_INSN(lb, MATCH_LB, MASK_LB)
485DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
486DECLARE_INSN(lh, MATCH_LH, MASK_LH)
487DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
488DECLARE_INSN(lw, MATCH_LW, MASK_LW)
489DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
490DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
491DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
492DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
493DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
494DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
495DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
496DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
497DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
498DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
499DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
500DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
501DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
502DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
503DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
504DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
505DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
506DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
507DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
508DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
509DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
510DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
511DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
512DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
513DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
514DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
515DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
516DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
517DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
518DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
519DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
520DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
521DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
522DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
523DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
524DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
525DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
526DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
527DECLARE_INSN(rem, MATCH_REM, MASK_REM)
528DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
529DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
530DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
531DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
532DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
533DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
534DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
535DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
536DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
537DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
538DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
539DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
540DECLARE_INSN(ld, MATCH_LD, MASK_LD)
541DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
542DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
543DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
544DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
545DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
546DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
547DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
548DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
549DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
550DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
551DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
552DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
553DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
554DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
555DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
556DECLARE_INSN(or, MATCH_OR, MASK_OR)
557DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
558DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
559DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
560DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
561DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
562DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
563DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
564DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
565DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
566DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
567DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
568DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
569DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
570DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
571DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
572DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
573DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
574DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
575DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
576DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
577DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
578DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
579DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
580DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
581DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
582DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
583DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
584DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
585DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
586DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
587DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
588DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
589DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
590DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
591DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
592DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
593DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
594DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
595DECLARE_INSN(and, MATCH_AND, MASK_AND)
596DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
597DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
598DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
599DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
600DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
601DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
602DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
603DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
604DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
605DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
606DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
607DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
608DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
609DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
610DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
611DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
612DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
613DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
614DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
615DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
616DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
617DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
618DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
619DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
620DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
621DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
622DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
623DECLARE_INSN(sw, MATCH_SW, MASK_SW)
624DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
625DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
626DECLARE_INSN(sh, MATCH_SH, MASK_SH)
627DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
628DECLARE_INSN(sb, MATCH_SB, MASK_SB)
629DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
630DECLARE_INSN(sd, MATCH_SD, MASK_SD)
631#endif
632#ifdef DECLARE_CSR
633DECLARE_CSR(fflags, CSR_FFLAGS)
634DECLARE_CSR(frm, CSR_FRM)
635DECLARE_CSR(fcsr, CSR_FCSR)
636DECLARE_CSR(stats, CSR_STATS)
637DECLARE_CSR(sup0, CSR_SUP0)
638DECLARE_CSR(sup1, CSR_SUP1)
639DECLARE_CSR(epc, CSR_EPC)
640DECLARE_CSR(badvaddr, CSR_BADVADDR)
641DECLARE_CSR(ptbr, CSR_PTBR)
642DECLARE_CSR(asid, CSR_ASID)
643DECLARE_CSR(count, CSR_COUNT)
644DECLARE_CSR(compare, CSR_COMPARE)
645DECLARE_CSR(evec, CSR_EVEC)
646DECLARE_CSR(cause, CSR_CAUSE)
647DECLARE_CSR(status, CSR_STATUS)
648DECLARE_CSR(hartid, CSR_HARTID)
649DECLARE_CSR(impl, CSR_IMPL)
650DECLARE_CSR(fatc, CSR_FATC)
651DECLARE_CSR(send_ipi, CSR_SEND_IPI)
652DECLARE_CSR(clear_ipi, CSR_CLEAR_IPI)
653DECLARE_CSR(reset, CSR_RESET)
654DECLARE_CSR(tohost, CSR_TOHOST)
655DECLARE_CSR(fromhost, CSR_FROMHOST)
656DECLARE_CSR(cycle, CSR_CYCLE)
657DECLARE_CSR(time, CSR_TIME)
658DECLARE_CSR(instret, CSR_INSTRET)
659DECLARE_CSR(uarch0, CSR_UARCH0)
660DECLARE_CSR(uarch1, CSR_UARCH1)
661DECLARE_CSR(uarch2, CSR_UARCH2)
662DECLARE_CSR(uarch3, CSR_UARCH3)
663DECLARE_CSR(uarch4, CSR_UARCH4)
664DECLARE_CSR(uarch5, CSR_UARCH5)
665DECLARE_CSR(uarch6, CSR_UARCH6)
666DECLARE_CSR(uarch7, CSR_UARCH7)
667DECLARE_CSR(uarch8, CSR_UARCH8)
668DECLARE_CSR(uarch9, CSR_UARCH9)
669DECLARE_CSR(uarch10, CSR_UARCH10)
670DECLARE_CSR(uarch11, CSR_UARCH11)
671DECLARE_CSR(uarch12, CSR_UARCH12)
672DECLARE_CSR(uarch13, CSR_UARCH13)
673DECLARE_CSR(uarch14, CSR_UARCH14)
674DECLARE_CSR(uarch15, CSR_UARCH15)
675DECLARE_CSR(counth, CSR_COUNTH)
676DECLARE_CSR(cycleh, CSR_CYCLEH)
677DECLARE_CSR(timeh, CSR_TIMEH)
678DECLARE_CSR(instreth, CSR_INSTRETH)
679#endif
680#ifdef DECLARE_CAUSE
681DECLARE_CAUSE("fflags", CAUSE_FFLAGS)
682DECLARE_CAUSE("frm", CAUSE_FRM)
683DECLARE_CAUSE("fcsr", CAUSE_FCSR)
684DECLARE_CAUSE("stats", CAUSE_STATS)
685DECLARE_CAUSE("sup0", CAUSE_SUP0)
686DECLARE_CAUSE("sup1", CAUSE_SUP1)
687DECLARE_CAUSE("epc", CAUSE_EPC)
688DECLARE_CAUSE("badvaddr", CAUSE_BADVADDR)
689DECLARE_CAUSE("ptbr", CAUSE_PTBR)
690DECLARE_CAUSE("asid", CAUSE_ASID)
691DECLARE_CAUSE("count", CAUSE_COUNT)
692DECLARE_CAUSE("compare", CAUSE_COMPARE)
693DECLARE_CAUSE("evec", CAUSE_EVEC)
694DECLARE_CAUSE("cause", CAUSE_CAUSE)
695DECLARE_CAUSE("status", CAUSE_STATUS)
696DECLARE_CAUSE("hartid", CAUSE_HARTID)
697DECLARE_CAUSE("impl", CAUSE_IMPL)
698DECLARE_CAUSE("fatc", CAUSE_FATC)
699DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI)
700DECLARE_CAUSE("clear_ipi", CAUSE_CLEAR_IPI)
701DECLARE_CAUSE("reset", CAUSE_RESET)
702DECLARE_CAUSE("tohost", CAUSE_TOHOST)
703DECLARE_CAUSE("fromhost", CAUSE_FROMHOST)
704DECLARE_CAUSE("cycle", CAUSE_CYCLE)
705DECLARE_CAUSE("time", CAUSE_TIME)
706DECLARE_CAUSE("instret", CAUSE_INSTRET)
707DECLARE_CAUSE("uarch0", CAUSE_UARCH0)
708DECLARE_CAUSE("uarch1", CAUSE_UARCH1)
709DECLARE_CAUSE("uarch2", CAUSE_UARCH2)
710DECLARE_CAUSE("uarch3", CAUSE_UARCH3)
711DECLARE_CAUSE("uarch4", CAUSE_UARCH4)
712DECLARE_CAUSE("uarch5", CAUSE_UARCH5)
713DECLARE_CAUSE("uarch6", CAUSE_UARCH6)
714DECLARE_CAUSE("uarch7", CAUSE_UARCH7)
715DECLARE_CAUSE("uarch8", CAUSE_UARCH8)
716DECLARE_CAUSE("uarch9", CAUSE_UARCH9)
717DECLARE_CAUSE("uarch10", CAUSE_UARCH10)
718DECLARE_CAUSE("uarch11", CAUSE_UARCH11)
719DECLARE_CAUSE("uarch12", CAUSE_UARCH12)
720DECLARE_CAUSE("uarch13", CAUSE_UARCH13)
721DECLARE_CAUSE("uarch14", CAUSE_UARCH14)
722DECLARE_CAUSE("uarch15", CAUSE_UARCH15)
723DECLARE_CAUSE("counth", CAUSE_COUNTH)
724DECLARE_CAUSE("cycleh", CAUSE_CYCLEH)
725DECLARE_CAUSE("timeh", CAUSE_TIMEH)
726DECLARE_CAUSE("instreth", CAUSE_INSTRETH)
727#endif