Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2013 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <stdint.h> |
| 22 | #include <arch/io.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <romstage_handoff.h> |
| 27 | |
| 28 | #include <baytrail/iomap.h> |
| 29 | #include <baytrail/lpc.h> |
| 30 | #include <baytrail/nvs.h> |
| 31 | #include <baytrail/pci_devs.h> |
| 32 | #include <baytrail/ramstage.h> |
| 33 | |
| 34 | static inline void |
| 35 | add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) |
| 36 | { |
| 37 | mmio_resource(dev, i, addr >> 10, size >> 10); |
| 38 | } |
| 39 | |
| 40 | static void sc_add_mmio_resources(device_t dev) |
| 41 | { |
| 42 | add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, 1024); |
| 43 | add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, 16 * 1024); |
| 44 | add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, 1024); |
| 45 | add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, 1024); |
| 46 | add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, 1024 * 1024); |
| 47 | add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, 2048); |
| 48 | add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, 1024); |
| 49 | } |
| 50 | |
| 51 | /* Default IO range claimed by the LPC device. The upper bound is exclusive. */ |
| 52 | #define LPC_DEFAULT_IO_RANGE_LOWER 0 |
| 53 | #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 |
| 54 | |
| 55 | static inline int io_range_in_default(int base, int size) |
| 56 | { |
| 57 | /* Does it start above the range? */ |
| 58 | if (base >= LPC_DEFAULT_IO_RANGE_UPPER) |
| 59 | return 0; |
| 60 | |
| 61 | /* Is it entirely contained? */ |
| 62 | if (base >= LPC_DEFAULT_IO_RANGE_LOWER && |
| 63 | (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) |
| 64 | return 1; |
| 65 | |
| 66 | /* This will return not in range for partial overlaps. */ |
| 67 | return 0; |
| 68 | } |
| 69 | |
| 70 | /* |
| 71 | * Note: this function assumes there is no overlap with the default LPC device's |
| 72 | * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. |
| 73 | */ |
| 74 | static void sc_add_io_resource(device_t dev, int base, int size, int index) |
| 75 | { |
| 76 | struct resource *res; |
| 77 | |
| 78 | if (io_range_in_default(base, size)) |
| 79 | return; |
| 80 | |
| 81 | res = new_resource(dev, index); |
| 82 | res->base = base; |
| 83 | res->size = size; |
| 84 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 85 | } |
| 86 | |
| 87 | static void sc_add_io_resources(device_t dev) |
| 88 | { |
| 89 | struct resource *res; |
| 90 | |
| 91 | /* Add the default claimed IO range for the LPC device. */ |
| 92 | res = new_resource(dev, 0); |
| 93 | res->base = LPC_DEFAULT_IO_RANGE_LOWER; |
| 94 | res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; |
| 95 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 96 | |
| 97 | /* GPIO */ |
| 98 | sc_add_io_resource(dev, GPIO_BASE_ADDRESS, 256, GBASE); |
| 99 | |
| 100 | /* ACPI */ |
| 101 | sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE); |
| 102 | } |
| 103 | |
| 104 | static void sc_read_resources(device_t dev) |
| 105 | { |
| 106 | /* Get the normal PCI resources of this device. */ |
| 107 | pci_dev_read_resources(dev); |
| 108 | |
| 109 | /* Add non-standard MMIO resources. */ |
| 110 | sc_add_mmio_resources(dev); |
| 111 | |
| 112 | /* Add IO resources. */ |
| 113 | sc_add_io_resources(dev); |
| 114 | } |
| 115 | |
| 116 | static struct device_operations device_ops = { |
| 117 | .read_resources = sc_read_resources, |
| 118 | .set_resources = pci_dev_set_resources, |
| 119 | .enable_resources = NULL, |
| 120 | .init = NULL, |
| 121 | .enable = NULL, |
| 122 | .scan_bus = NULL, |
| 123 | .ops_pci = &soc_pci_ops, |
| 124 | }; |
| 125 | |
| 126 | static const struct pci_driver southcluster __pci_driver = { |
| 127 | .ops = &device_ops, |
| 128 | .vendor = PCI_VENDOR_ID_INTEL, |
| 129 | .device = LPC_DEVID, |
| 130 | }; |