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Alexandru Gagniuc23211b02013-06-09 16:06:07 -05001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "vx900.h"
21#include "chip.h"
22
23#include <console/console.h>
24#include <device/device.h>
25#include <device/pci.h>
26#include <device/pci_ids.h>
27#include <cpu/cpu.h>
28#include <cbmem.h>
29#include <lib.h>
30#include <reset.h>
31#include <string.h>
32
33#define RAM_4GB (((u64)1) << 32)
34
Kyösti Mälkki5cf88242013-10-18 11:02:56 +030035static uint64_t uma_memory_base = 0;
36static uint64_t uma_memory_size = 0;
37
Alexandru Gagniuc23211b02013-06-09 16:06:07 -050038/**
39 * @file northbridge.c
40 *
41 * STATUS: Pretty good
42 * One thing that needs to be thoroughly tested is the remap above 4G logic.
43 * Unfortunately, while we cannot initialize odd ranks, our testing
44 * possibilities are somewhat limited. A point of failure that is not covered is
45 * when the amount of RAM and PCI config space added up exceeds 8GB. The
46 * remapping mechanism will overflow, the effects of which are unknown.
47 */
48
49void hard_reset(void)
50{
51 outb((1 << 2) | (1 << 1), 0xcf9);
52}
53
Kyösti Mälkki5cf88242013-10-18 11:02:56 +030054uint64_t get_uma_memory_base(void)
55{
56 printk(BIOS_DEBUG, "UMA base 0x%.8llx (%lluMB)\n", uma_memory_base,
57 uma_memory_base >> 20);
58 printk(BIOS_DEBUG, "UMA size 0x%.8llx (%lluMB)\n", uma_memory_size,
59 uma_memory_size >> 20);
60 return uma_memory_base;
61}
62
Alexandru Gagniuc23211b02013-06-09 16:06:07 -050063static u64 vx900_get_top_of_ram(device_t mcu)
64{
65 u16 reg16;
66 /* The last valid DRAM address is computed by the MCU
67 * One issue might be if we have a hole in the rank mappings, so that
68 * virtual ranks are not mapped successively in the linear address space
69 * (Ex: rank 0 mapped 0-1G, rank 1 mapped 2G-3G)
70 * We don't do this awkward mapping in RAM init, so we don't worry about
71 * it here, but it is something to keep in mind if having RAM issues */
72 reg16 = pci_read_config16(mcu, 0x88) & 0x07ff;
73 return (u64) reg16 << 24;
74}
75
76/*
77 * This guy is meant to go away, but for now, leave it in so that we can see
78 * if the logic to remap RAM above 4G has errors.
79 */
80static void killme_debug_4g_remap_reg(u32 reg32)
81{
82 if (reg32 & (1 << 0))
Stefan Reinauer65b72ab2015-01-05 12:59:54 -080083 printk(BIOS_DEBUG, "Mem remapping enabled\n");
Alexandru Gagniuc23211b02013-06-09 16:06:07 -050084 u64 remapstart = (reg32 >> 2) & 0x3ff;
85 u64 remapend = (reg32 >> 14) & 0x3ff;
86 remapstart <<= 26;
87 remapend <<= 26;
88 printk(BIOS_DEBUG, "Remapstart %lld(MB) \n", remapstart >> 20);
89 printk(BIOS_DEBUG, "Remapend %lld(MB) \n", remapend >> 20);
90}
91
92/**
93 * \brief Remap low memory colliding with PCI MMIO space, above 4G
94 *
95 * @param mcu The memory controller
96 * @param tolm Top of low memory.
97 *
98 * @return The new top of memory.
99 */
100static u64 vx900_remap_above_4g(device_t mcu, u32 tolm)
101{
102 size_t i;
103 u8 reg8, start8, end8, start, end;
104 u16 reg16;
105 u32 reg32;
106 u64 tor, newtor, chunk;
107
108 /*
109 * The remapping mechanism works like this:
110 *
111 * - Choose the top of low memory.
112 * This becomes the "remap from"
113 * - Choose a chunk above 4G where to remap.
114 * This becomes "remap to"
115 * - Choose a chunk above 4G where to end the remapping.
116 * This becomes "remap until"
117 *
118 * This remaps a "chunk" of memory where we want to.
119 * sizeof(chunk) = until - to;
120 *
121 * Therefore the memory region from "from" to " from + sizeof(chunk)"
122 * becomes accessible at "to" to "until"
123 */
124 if (tolm >= vx900_get_top_of_ram(mcu)) {
Stefan Reinauer65b72ab2015-01-05 12:59:54 -0800125 printk(BIOS_DEBUG, "Nothing to remap\n");
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500126 }
127
128 /* This is how the Vendor BIOS. Keep it for comparison for now */
129 killme_debug_4g_remap_reg(0x00180141);
130 /* We can remap with a granularity of 64MB, so align tolm */
131 tolm &= ~((64 * MiB) - 1);
132
133 /* The "start remapping from where ?" register */
134 reg16 = ((tolm >> 20) & 0xfff) << 4;
135 pci_mod_config16(mcu, 0x84, 0xfff0, reg16);
136
137 /* Find the chunk size */
138 tor = vx900_get_top_of_ram(mcu);
139 printk(BIOS_DEBUG, "Top of RAM %lldMB\n", tor >> 20);
140
141 if (tor < RAM_4GB) {
142 chunk = tor - tolm;
143 newtor = RAM_4GB + chunk;
144 } else {
145 chunk = (RAM_4GB - tolm);
146 newtor = tor + chunk;
147 }
148 printk(BIOS_DEBUG, "New top of RAM %lldMB\n", newtor >> 20);
149
150 reg8 = tolm >> 26;
151 /* Which rank does the PCI TOLM fall on? */
152 for (i = 0; i < VX900_MAX_MEM_RANKS; i++) {
153 end8 = pci_read_config8(mcu, 0x40 + i);
154 if (reg8 > end8)
155 continue;
156 start8 = pci_read_config8(mcu, 0x48 + i);
157 if (reg8 <= start8)
158 continue;
Patrick Georgi6f7e4b22014-05-19 09:18:11 +0200159 printk(BIOS_DEBUG, "Address %x falls on rank %zu\n", tolm, i);
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500160 break;
161 }
162
163 for (; i < VX900_MAX_MEM_RANKS; i++) {
164 start = pci_read_config8(mcu, 0x48 + i);
165 end = pci_read_config8(mcu, 0x40 + i);
166
167 if (end == 0) {
Patrick Georgi6f7e4b22014-05-19 09:18:11 +0200168 printk(BIOS_DEBUG, "Huh? rank %zu empty?\n", i);
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500169 continue;
170 }
171
172 if (end < (tolm >> 26)) {
Patrick Georgi6f7e4b22014-05-19 09:18:11 +0200173 printk(BIOS_DEBUG, "Huh? rank %zu don't need remap?\n",
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500174 i);
175 continue;
176 }
177
178 printk(BIOS_DEBUG, "Physical rank %u is mapped to\n"
179 " Start address: 0x%.10llx (%dMB)\n"
180 " End address: 0x%.10llx (%dMB)\n",
181 (int)i,
182 ((u64) start << 26), (start << (26 - 20)),
183 ((u64) end << 26), (end << (26 - 20)));
184
185 if (end < (RAM_4GB >> 26))
186 end = (RAM_4GB >> 26);
187
188 if (end >= (tolm >> 26))
189 end += chunk >> 26;
190
191 if (start > (tolm >> 26))
192 start += chunk >> 26;
193
194 pci_write_config8(mcu, 0x48 + i, start);
195 pci_write_config8(mcu, 0x40 + i, end);
196
197 printk(BIOS_DEBUG, "ReMapped Physical rank %u, to\n"
198 " Start address: 0x%.10llx (%dMB)\n"
199 " End address: 0x%.10llx (%dMB)\n",
200 (int)i,
201 ((u64) start << 26), (start << (26 - 20)),
202 ((u64) end << 26), (end << (26 - 20)));
203 }
204
205 /* The "remap to where?" register */
Alexandru Gagniuc560433b2013-06-10 15:47:25 -0500206 reg32 = ((MAX(tor, RAM_4GB) >> 26) & 0x3ff) << 2;
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500207 /* The "remap until where?" register */
208 reg32 |= ((newtor >> 26) & 0x3ff) << 14;
209 /* Now enable the goodies */
210 reg32 |= (1 << 0);
211 pci_write_config32(mcu, 0xf8, reg32);
212 printk(BIOS_DEBUG, "Wrote remap map %x\n", reg32);
213 killme_debug_4g_remap_reg(reg32);
214
215 printk(BIOS_DEBUG, "New top of memory is at %lldMB\n", newtor >> 20);
216 return newtor;
217}
218
219static void vx900_set_resources(device_t dev)
220{
221 u32 pci_tolm, tomk, vx900_tolm, full_tolmk, fbufk, tolmk;
222
Stefan Reinauer65b72ab2015-01-05 12:59:54 -0800223 printk(BIOS_DEBUG, "========================================"
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500224 "========================================\n");
Stefan Reinauer65b72ab2015-01-05 12:59:54 -0800225 printk(BIOS_DEBUG, "============= VX900 memory sizing & Co. "
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500226 "========================================\n");
Stefan Reinauer65b72ab2015-01-05 12:59:54 -0800227 printk(BIOS_DEBUG, "========================================"
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500228 "========================================\n");
229
230 int idx = 10;
231 const device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
232 PCI_DEVICE_ID_VIA_VX900_MEMCTRL,
233 0);
234 if (!mcu) {
235 die("Something is terribly wrong.\n"
236 " We tried locating the MCU on the PCI bus, "
237 "but couldn't find it. Halting.\n");
238 }
239
240 /* How much low adrress space do we have? */
241 pci_tolm = find_pci_tolm(dev->link_list);
242 printk(BIOS_SPEW, "Found PCI tolm at %.8x\n", pci_tolm);
243 printk(BIOS_SPEW, "Found PCI tolm at %dMB\n", pci_tolm >> 20);
244
245 /* Figure out the total amount of RAM */
246 tomk = vx900_get_top_of_ram(mcu) >> 10;
247 printk(BIOS_SPEW, "Found top of memory at %dMB\n", tomk >> 10);
248
249 /* Do the same for top of low RAM */
250 vx900_tolm = (pci_read_config16(mcu, 0x84) & 0xfff0) >> 4;
251 full_tolmk = vx900_tolm << (20 - 10);
252 /* Remap above 4G if needed */
Alexandru Gagniuc560433b2013-06-10 15:47:25 -0500253 full_tolmk = MIN(full_tolmk, pci_tolm >> 10);
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500254 printk(BIOS_SPEW, "Found top of low memory at %dMB\n",
255 full_tolmk >> 10);
256
257 /* What about the framebuffer for the integrated GPU? */
258 fbufk = chrome9hd_fb_size() >> 10;
259 printk(BIOS_SPEW, "Integrated graphics buffer: %dMB\n", fbufk >> 10);
260
261 /* Can't use the framebuffer as system RAM, sorry */
Alexandru Gagniuc560433b2013-06-10 15:47:25 -0500262 tolmk = MIN(full_tolmk, tomk);
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500263 tolmk -= fbufk;
264 ram_resource(dev, idx++, 0, 640);
265 printk(BIOS_SPEW, "System ram left: %dMB\n", tolmk >> 10);
266 /* FIXME: how can we avoid leaving this hole?
267 * Leave a hole for VGA, 0xa0000 - 0xc0000 ?? */
268 /* TODO: VGA Memory hole can be disabled in SNMIC. Upper 64k of ROM seem
269 * to be always mapped to the top of 1M, but this can be overcome with
270 * some smart positive/subtractive resource decoding */
271 ram_resource(dev, idx++, 768, (tolmk - 768));
272 uma_memory_size = fbufk << 10;
273 uma_memory_base = tolmk << 10;
274
Kyösti Mälkki5cf88242013-10-18 11:02:56 +0300275 //uma_resource(dev, idx++, uma_memory_base>>10, uma_memory_size>>10);
276
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500277 printk(BIOS_DEBUG, "UMA @ %lldMB + %lldMB\n", uma_memory_base >> 20,
278 uma_memory_size >> 20);
279 /* FIXME: How do we handle remapping above 4G? */
280 u64 tor = vx900_remap_above_4g(mcu, pci_tolm);
281 ram_resource(dev, idx++, RAM_4GB >> 10, (tor - RAM_4GB) >> 10);
282
Kyösti Mälkki42f46512013-06-27 08:20:09 +0300283 set_top_of_ram(tolmk << 10);
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500284
Stefan Reinauer65b72ab2015-01-05 12:59:54 -0800285 printk(BIOS_DEBUG, "======================================================\n");
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500286 assign_resources(dev->link_list);
287}
288
289static void vx900_read_resources(device_t dev)
290{
291 /* Our fixed resources start at 0 */
292 int idx = 0;
293 /* Reserve our ROM mapped space */
294 struct resource *res;
295 res = new_resource(dev, idx++);
296 res->size = CONFIG_ROM_SIZE;
297 res->base = 0xffffffff - (res->size - 1);
298 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
299
300 /* Now do the same for our MMCONF
301 * We always run with MMCONF enabled. We need to access the extended
302 * config space when configuring PCI-Express links */
303 res = new_resource(dev, idx++);
304 res->size = 256 * MiB;
305 res->base = CONFIG_MMCONF_BASE_ADDRESS;
306 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
307
308 pci_domain_read_resources(dev);
309}
310
311static struct device_operations pci_domain_ops = {
312 .read_resources = vx900_read_resources,
313 .set_resources = vx900_set_resources,
314 .enable_resources = NULL,
315 .init = NULL,
316 .scan_bus = pci_domain_scan_bus,
Kyösti Mälkki872c9222013-07-03 09:44:28 +0300317 .ops_pci_bus = pci_bus_default_ops,
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500318};
319
320static void cpu_bus_init(device_t dev)
321{
322 initialize_cpus(dev->link_list);
323}
324
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500325static struct device_operations cpu_bus_ops = {
Edward O'Callaghand2040732014-10-31 08:26:21 +1100326 .read_resources = DEVICE_NOOP,
327 .set_resources = DEVICE_NOOP,
328 .enable_resources = DEVICE_NOOP,
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500329 .init = cpu_bus_init,
330 .scan_bus = 0,
331};
332
333static void enable_dev(device_t dev)
334{
335 /* Set the operations if it is a special bus type */
336 if (dev->path.type == DEVICE_PATH_DOMAIN) {
337 dev->ops = &pci_domain_ops;
338 } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
339 dev->ops = &cpu_bus_ops;
340 }
341}
342
343struct chip_operations northbridge_via_vx900_ops = {
344 CHIP_NAME("VIA VX900 Chipset")
345 .enable_dev = enable_dev,
346};