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Alexandru Gagniuc23211b02013-06-09 16:06:07 -05001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <arch/io.h>
21#include <config.h>
22#include <console/console.h>
23#include <device/pci.h>
24#include <device/pci_ids.h>
25#include <pc80/vga_io.h>
Alexandru Gagniuc560433b2013-06-10 15:47:25 -050026#include <stdlib.h>
Alexandru Gagniuc23211b02013-06-09 16:06:07 -050027
28#include "vx900.h"
29
30#define CHROME_9_HD_MIN_FB_SIZE 8
31#define CHROME_9_HD_MAX_FB_SIZE 512
32
33/**
34 * @file chrome9hd.c
35 *
36 * \brief Initialization for Chrome9HD integrated graphics adapters
37 *
38 * This takes care of the initialization we need to do before calling the VGA
39 * BIOS. The device is not documented in the VX900 datasheet.
40 *
41 * The device is documented in:
42 * Open Graphics Programming Manual
43 * Chrome9GraphicsHD Processor
44 * VX900 Series System Processor
45 * Part I: Graphics Core / 2D
46 *
47 * This document was released by VIA to the Xorg project, and is available at:
48 * <http://www.x.org/docs/via/OGPM_Chrome9%20HD%20DX9%20_R100_PartI_Core_2D.pdf>
49 *
50 * STATUS:
51 * We do the minimal initialization described in VIA documents. Running the VGA
52 * option ROM does not get us a usable display. We configure the framebuffer and
53 * the IGP is able to use it. GRUB2 and linux are capable of getting a usable
54 * text console, which uses the monitor's native resolution (even 1920x1080).
55 * The graphical console (linux) does not work properly.
56 * @TODO
57 * 1. Figure out what sequence we need to do to get the VGA BIOS running
58 * properly. Use the code provided by VIA and compare their sequence to ours,
59 * fill in any missing steps, etc.
60 * 2. Make BAR2 and the framebuffer use the same memory space. This is a feature
61 * called "Direct framebuffer access" which allows us to save memory space by
62 * setting BAR2 of the VGA to the location in memory of the framebuffer. This
63 * reduces the amount of PCI MMIO space we need below 4G, and is especially
64 * useful considering we only have 8GB (33 bits) of memory-mapped space.
65 */
66
67/* Helper to determine the framebuffer size */
68u32 chrome9hd_fb_size(void)
69{
70 static u32 fb_size = 0;
71 u8 reg8, ranksize;
72 u32 size_mb, tom_mb, max_size_mb;
73 int i;
74 /* We do some PCI and CMOS IO to find our value, so if we've already
75 * found it, save some time */
76 if (fb_size != 0)
77 return fb_size;
78 /* FIXME: read fb_size from CMOS, but until that is implemented, start
79 * from 512MB */
80 size_mb = 512;
81
82 /* The minimum framebuffer size is 8MB. */
Alexandru Gagniuc560433b2013-06-10 15:47:25 -050083 size_mb = MAX(size_mb, CHROME_9_HD_MIN_FB_SIZE);
Alexandru Gagniuc23211b02013-06-09 16:06:07 -050084
85 const device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
86 PCI_DEVICE_ID_VIA_VX900_MEMCTRL,
87 0);
88 /*
89 * We have two limitations on the maximum framebuffer size:
90 * 1) (Sanity) No more that 1/4 of system RAM
91 * 2) (Hardware limitation) No larger than DRAM in last rank
92 * Check both of these limitations and apply them to our framebuffer */
93 tom_mb = (pci_read_config16(mcu, 0x88) & 0x07ff) << (24 - 20);
94 max_size_mb = tom_mb >> 2;
95 if (size_mb > max_size_mb) {
96 printk(BIOS_ALERT, "The framebuffer size of of %dMB is larger"
97 " than 1/4 of available memory.\n"
98 " Limiting framebuffer to %dMB\n", size_mb, max_size_mb);
99 size_mb = max_size_mb;
100 }
101
102 /* Now handle limitation #2
103 * Look at the ending address of the memory ranks, from last to first,
104 * until we find one that is not zero. That is our last rank, and its
105 * size is the limit of our framebuffer. */
106 /* FIXME: This has a bug. If we remap memory above 4G, we consider the
107 * memory hole as part of our RAM. Thus if we install 3G, with a TOLM of
108 * 2.5G, our TOM will be at 5G and we'll assume we have 5G RAM instead
109 * of the actual 3.5G */
110 for (i = VX900_MAX_MEM_RANKS - 1; i > -1; i--) {
111 reg8 = pci_read_config8(mcu, 0x40 + i);
112 if (reg8 == 0)
113 continue;
114 /* We've reached the last populated rank */
115 ranksize = reg8 - pci_read_config8(mcu, 0x48 + i);
116 max_size_mb = ranksize << 6;
117 /* That's it. We got what we needed. */
118 break;
119 };
120 if (size_mb > max_size_mb) {
121 printk(BIOS_ALERT, "The framebuffer size of %dMB is larger"
122 " than size of the last DRAM rank.\n"
123 " Limiting framebuffer to %dMB\n", size_mb, max_size_mb);
124 size_mb = max_size_mb;
125 }
126
127 /* Now round the framebuffer size to the closest power of 2 */
128 u8 fb_pow = 0;
129 while (size_mb >> fb_pow)
130 fb_pow++;
131 fb_pow--;
132 size_mb = (1 << fb_pow);
133 /* We store the framebuffer size in bytes, for simplicity */
134 fb_size = size_mb << 20;
135 return fb_size;
136}
137
138/**
Martin Roth6e222252014-12-29 14:44:38 -0700139 * vx900_int15
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500140 *
141 * \brief INT15 helpers for Chrome9HD IGP
142 *
143 * The following are helpers for INT15 handlers for the VGA BIOS. The full set
144 * of INT15 callbacks is described in
145 *
146 * VIA/S3Graphics
147 * Video BIOS External Interface Specification for Chrome9 Series IGP
148 * VX900 Series
149 *
150 * This document is only available under NDA, however, the callbacks are very
151 * similar to other VIA/Intel IGP callbacks.
152 *
153 * Callback 0x5f18 is the most important one. It informs the VGA BIOS of the
154 * RAM speed and framebuffer size. The other callbacks seem to be optional.
155 * @{
156 */
157
158/**
159 * \brief Get X86_BL value for VGA INT15 function 5f18
160 *
161 * Int15 5f18 lets the VGA BIOS know the framebuffer size and the memory speed.
162 * This handler is very important. If it is not implemented, the VGA BIOS will
163 * not work correctly.
164 *
165 * To use, just call this from the 15f18 handler, and place the return value in
166 * X86_BL
167 *
168 * @code{.c}
169 * case 0x5f18:
170 * X86_BX = vx900_int15_get_5f18_bl();
171 * res = 0;
172 * break;
173 * @endcode
174 *
175 */
176u8 vx900_int15_get_5f18_bl(void)
177{
178 u8 reg8, ret;
179 device_t dev;
180 /*
181 * BL Bit[7:4]
182 * Memory Data Rate (not to be confused with fCLK)
183 * 0000: 66MHz
184 * 0001: 100MHz
185 * 0010: 133MHz
186 * 0011: 200MHz ( DDR200 )
187 * 0100: 266MHz ( DDR266 )
188 * 0101: 333MHz ( DDR333 )
189 * 0110: 400MHz ( DDR400 )
190 * 0111: 533MHz ( DDR I/II 533)
191 * 1000: 667MHz ( DDR I/II 667)
192 * 1001: 800MHz ( DDR3 800)
193 * 1010: 1066MHz ( DDR3 1066)
194 * 1011: 1333MHz ( DDR3 1333)
195 * Bit[3:0]
196 * N: Frame Buffer Size 2^N MB
197 */
198 dev = dev_find_slot(0, PCI_DEVFN(0, 3));
199 reg8 = pci_read_config8(dev, 0xa1);
200 ret = (u32) ((reg8 & 0x70) >> 4) + 2;
201 reg8 = pci_read_config8(dev, 0x90);
202 reg8 = ((reg8 & 0x07) + 3) << 4;
203 ret |= (u32) reg8;
204
205 return ret;
206}
Alexandru Gagniuc560433b2013-06-10 15:47:25 -0500207
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500208/** @} */
209
210static void chrome9hd_set_sid_vid(u16 vendor, u16 device)
211{
212 vga_sr_write(0x36, vendor >> 8); /* SVID high byte */
213 vga_sr_write(0x35, vendor & 0xff); /* SVID low byte */
214 vga_sr_write(0x38, device >> 8); /* SID high byte */
215 vga_sr_write(0x37, device & 0xff); /* SID low byte */
216}
217
218static void chrome9hd_handle_uma(device_t dev)
219{
220 /* Mirror mirror, shiny glass, tell me that is not my ass */
221 u32 fb_size = chrome9hd_fb_size() >> 20;
222
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500223 u8 fb_pow = 0;
224 while (fb_size >> fb_pow)
225 fb_pow++;
226 fb_pow--;
227
228 /* Step 6 - Let MCU know the framebuffer size */
229 device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
230 PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);
231 pci_mod_config8(mcu, 0xa1, 7 << 4, (fb_pow - 2) << 4);
232
233 /* Step 7 - Let GFX know the framebuffer size (through PCI and IOCTL)
234 * The size we set here affects the behavior of BAR2, and the amount of
235 * MMIO space it requests. The default is 512MB, so if we don't set this
236 * before reading the resources, we could waste space below 4G */
237 pci_write_config8(dev, 0xb2, ((0xff << (fb_pow - 2)) & ~(1 << 7)));
238 vga_sr_write(0x68, (0xff << (fb_pow - 1)));
239 /* And also that the framebuffer is in the system, RAM */
240 pci_mod_config8(dev, 0xb0, 0, 1 << 0);
241}
242
243/**
244 * \brief Initialization sequence before running the VGA BIOS
245 *
246 * This is the initialization sequence described in:
247 *
248 * BIOS Porting Guide
249 * VX900 Series
250 * All-in-One System Processor
251 *
252 * This document is only available under NDA.
253 */
254static void chrome9hd_biosguide_init_seq(device_t dev)
255{
256 device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
257 PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);
258 device_t host = dev_find_device(PCI_VENDOR_ID_VIA,
259 PCI_DEVICE_ID_VIA_VX900_HOST_BR, 0);
260
261 /* Step 1 - Enable VGA controller */
262 /* FIXME: This is the VGA hole @ 640k-768k, and the vga port io
263 * We need the port IO, but can we disable the memory hole? */
264 pci_mod_config8(mcu, 0xa4, 0, (1 << 7)); /* VGA memory hole */
265
266 /* Step 2 - Forward MDA cycles to GFX */
267 pci_mod_config8(host, 0x4e, 0, (1 << 1));
268
269 /* Step 3 - Enable GFX I/O space */
270 pci_mod_config8(dev, PCI_COMMAND, 0, PCI_COMMAND_IO);
271
272 /* Step 4 - Enable video subsystem */
273 vga_enable_mask((1 << 0), (1 << 0));
274
275 /* FIXME: VGA IO Address Select. 3B5 or 3D5? */
276 vga_misc_mask((1 << 0), (1 << 0));
277
278 /* Step 5 - Unlock accessing of IO space */
279 vga_sr_write(0x10, 0x01);
280
281 chrome9hd_handle_uma(dev);
282
Kyösti Mälkki5cf88242013-10-18 11:02:56 +0300283 uint64_t gfx_base = get_uma_memory_base();
284 if (gfx_base == 0)
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500285 die("uma_memory_base not set. Abandon ship!\n");
Kyösti Mälkki5cf88242013-10-18 11:02:56 +0300286
287 /* Step 8 - Enable memory base register on the GFX */
288 vga_sr_write(0x6d, (gfx_base >> 21) & 0xff); /* base 28:21 */
289 vga_sr_write(0x6e, (gfx_base >> 29) & 0xff); /* base 36:29 */
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500290 vga_sr_write(0x6f, 0x00); /* base 43:37 */
291
292 /* Step 9 - Set SID/VID */
293 chrome9hd_set_sid_vid(0x1106, 0x7122);
294
295}
296
297static void chrome9hd_init(device_t dev)
298{
Stefan Reinauer65b72ab2015-01-05 12:59:54 -0800299 printk(BIOS_DEBUG, "======================================================\n");
300 printk(BIOS_DEBUG, "== Chrome9 HD INIT\n");
301 printk(BIOS_DEBUG, "======================================================\n");
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500302
303 chrome9hd_biosguide_init_seq(dev);
304
305 /* Prime PLL FIXME: bad comment */
306 vga_sr_mask(0x3c, 1 << 2, 1 << 2);
307
308 /* FIXME: recheck; VGA IO Address Select. 3B5 or 3D5? */
309 vga_misc_mask(1 << 0, 1 << 0);
310
311 /* FIXME: recheck; Enable Base VGA 16 Bits Decode */
312 ////pci_mod_config8(host, 0x4e, 0, 1<<4);
313
314 u32 fb_address = pci_read_config32(dev, PCI_BASE_ADDRESS_2);
315 fb_address &= ~0x0F;
316 if (!fb_address) {
317 printk(BIOS_WARNING, "Chrome9HD: No FB BAR assigned!\n");
318 return;
319 }
320
321 printk(BIOS_INFO, "Chrome: Using %dMB Framebuffer at 0x%08X.\n",
322 256, fb_address);
323
324 printk(BIOS_DEBUG, "Initializing VGA...\n");
325
326 pci_dev_init(dev);
327
328 printk(BIOS_DEBUG, "Enable VGA console\n");
329
330 dump_pci_device(dev);
331}
332
333static void chrome9hd_enable(device_t dev)
334{
335 device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
336 PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);
Elyes HAOUAS0f92f632014-07-27 19:37:31 +0200337 /* FIXME: here? -=- ACLK 250MHz */
Alexandru Gagniuc23211b02013-06-09 16:06:07 -0500338 pci_mod_config8(mcu, 0xbb, 0, 0x01);
339}
340
341static void chrome9hd_disable(device_t dev)
342{
343 device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
344 PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);
345 /* Disable GFX - This step effectively renders the GFX inert
346 * It won't even show up as a PCI device during enumeration */
347 pci_mod_config8(mcu, 0xa1, 1 << 7, 0);
348}
349
350static struct device_operations chrome9hd_operations = {
351 .read_resources = pci_dev_read_resources,
352 .set_resources = pci_dev_set_resources,
353 .enable_resources = pci_dev_enable_resources,
354 .init = chrome9hd_init,
355 .disable = chrome9hd_disable,
356 .enable = chrome9hd_enable,
357 .ops_pci = 0,
358};
359
360static const struct pci_driver chrome9hd_driver __pci_driver = {
361 .ops = &chrome9hd_operations,
362 .vendor = PCI_VENDOR_ID_VIA,
363 .device = PCI_DEVICE_ID_VIA_VX900_VGA,
364};