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Yinghai Lu93a5a192006-10-04 21:05:23 +00001/*
2 * Memory map:
3 *
4 * DCACHE_RAM_BASE
5 * : data segment
6 * : bss segment
7 * : heap
8 * : stack
9 */
10/*
11 * Bootstrap code for the STPC Consumer
12 * Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
13 */
14
15/*
16 * Written by Johan Rydberg, based on work by Daniel Kahlin.
17 * Rewritten by Eric Biederman
Stefan Reinauerf8ee1802008-01-18 15:08:58 +000018 * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling
Yinghai Lu93a5a192006-10-04 21:05:23 +000019 * 2006.05 yhlu tailed it to use it for AP code in cache
20 */
21/*
22 * We use ELF as output format. So that we can
23 * debug the code in some form.
24 */
25INCLUDE ldoptions
26
27ENTRY(_start)
28
29SECTIONS
30{
31 . = DCACHE_RAM_BASE;
32 /*
33 * First we place the code and read only data (typically const declared).
34 * This get placed in rom.
35 */
36 .text : {
37 _text = .;
38 *(.text);
39 *(.text.*);
40 . = ALIGN(16);
41 _etext = .;
42 }
43 .rodata : {
44 _rodata = .;
45 . = ALIGN(4);
46 *(.rodata)
47 *(.rodata.*)
48 . = ALIGN(4);
49 _erodata = .;
50 }
51 /*
52 * After the code we place initialized data (typically initialized
53 * global variables). This gets copied into ram by startup code.
54 * __data_start and __data_end shows where in ram this should be placed,
55 * whereas __data_loadstart and __data_loadend shows where in rom to
56 * copy from.
57 */
58 .data : {
59 _data = .;
60 *(.data)
61 _edata = .;
62 }
63 /*
64 * bss does not contain data, it is just a space that should be zero
65 * initialized on startup. (typically uninitialized global variables)
66 * crt0.S fills between _bss and _ebss with zeroes.
67 */
68 _bss = .;
69 .bss . : {
70 *(.bss)
71 *(.sbss)
72 *(COMMON)
73 }
74 _ebss = .;
75 _end = .;
76 . = ALIGN(0x1000);
77 _stack = .;
78 .stack . : {
79 . = 0x4000;
80 }
81 _estack = .;
82 _heap = .;
83 .heap . : {
84 . = ALIGN(4);
85 }
86 _eheap = .;
87 /* The ram segment
Stefan Reinauerf8ee1802008-01-18 15:08:58 +000088 * This is all address of the memory resident copy of coreboot.
Yinghai Lu93a5a192006-10-04 21:05:23 +000089 */
90 _ram_seg = _text;
91 _eram_seg = _eheap;
92
Stefan Reinauerf8ee1802008-01-18 15:08:58 +000093 _bogus = ASSERT( ( _eram_seg <= ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE))) , "coreboot_apc is too big");
Yinghai Lu93a5a192006-10-04 21:05:23 +000094
95 /DISCARD/ : {
96 *(.comment)
97 *(.note)
98 *(.note.*)
99 }
100}