blob: 6da8006040dd0747b2c1a3c4c2ee70d818cc5523 [file] [log] [blame]
Greg Watson4890a662003-06-23 01:01:17 +00001#######################################################
2#
Stefan Reinauerf8ee1802008-01-18 15:08:58 +00003# Main options file for coreboot
Greg Watson4890a662003-06-23 01:01:17 +00004#
5# Each option used by a part must be defined in
6# this file. The format for options is:
7#
8# define <name>
9# default <expr> | {<expr>} | "<string>" | none
10# format "<string>"
11# export always | used | never
12# comment "<string>"
13# end
14#
15# where
16#
17# <name> is the name of the option
18# <expr> is a numeric expression
19# <string> is a string
20#
21# Either a default value or 'default none' must
22# be specified for every option. An option
23# specified as 'default none' will not be exported
24# (i.e. will remain undefined) unless it has
25# been assigned a value.
26#
27# Option values can be an immediate expression that
28# evaluates to a numeric value, a delayed expression
29# (surrounded by curley braces), or a string
30# (surrounded by double quotes.)
31#
32# Immediate expressions are evaluated at the time an
33# option is defined or set and the numeric result
34# becomes the value of the option.
35#
36# Delayed expression are evaluated at the time the
37# option is used, either in another expression or
38# when being exported.
39#
40# String values will have the double quotes removed
41# automatically.
42#
43# Format strings determine the print format that is
44# used when exporting options. The default format
45# is "%s" for strings and "%d" for numbers.
46#
47# Exported options generate entries in the
48# Makefile.settings file. Options can be always
49# exported, exported only if used, or never exported.
50#
51# A comment string must be supplied for every option.
52#
53#######################################################
54
55###############################################
56# Architecture options
57###############################################
58
59define ARCH
60 default "i386"
61 export always
62 comment "Default architecture is i386, options are alpha and ppc"
63end
Eric Biedermanf8a2ddd2004-10-30 08:05:41 +000064define HAVE_MOVNTI
65 default 0
66 export always
67 comment "This cpu supports the MOVNTI directive"
Greg Watson4890a662003-06-23 01:01:17 +000068end
69
70###############################################
71# Build options
72###############################################
73
74define CROSS_COMPILE
75 default ""
76 export always
77 comment "Cross compiler prefix"
78end
79define CC
80 default "$(CROSS_COMPILE)gcc"
81 export always
82 comment "Target C Compiler"
83end
84define HOSTCC
Greg Watson109959d2003-07-14 18:00:10 +000085 default "gcc"
Greg Watson4890a662003-06-23 01:01:17 +000086 export always
87 comment "Host C Compiler"
88end
Greg Watson499b3042003-07-28 21:15:13 +000089define CPU_OPT
90 default none
91 export used
92 comment "Additional per-cpu CFLAGS"
93end
Greg Watson4890a662003-06-23 01:01:17 +000094define OBJCOPY
arch import user (historical)577f1852005-07-06 17:11:02 +000095 default "$(CROSS_COMPILE)objcopy --gap-fill 0xff"
Greg Watson4890a662003-06-23 01:01:17 +000096 export always
97 comment "Objcopy command"
98end
Stefan Reinauerf8ee1802008-01-18 15:08:58 +000099define COREBOOT_VERSION
Stefan Reinauer3e03d032006-09-08 16:34:51 +0000100 default "2.0.0"
Greg Watson4890a662003-06-23 01:01:17 +0000101 export always
Eric Biedermanb78c1972004-10-14 20:54:17 +0000102 format "\"%s\""
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000103 comment "coreboot version"
Greg Watson4890a662003-06-23 01:01:17 +0000104end
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000105define COREBOOT_EXTRA_VERSION
Ronald G. Minnich57ffeb02003-07-30 03:05:20 +0000106 default ""
107 export used
Eric Biedermanb78c1972004-10-14 20:54:17 +0000108 format "\"%s\""
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000109 comment "coreboot extra version"
Ronald G. Minnich57ffeb02003-07-30 03:05:20 +0000110end
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000111define COREBOOT_BUILD
Greg Watson4890a662003-06-23 01:01:17 +0000112 default "$(shell date)"
113 export always
Eric Biedermanb78c1972004-10-14 20:54:17 +0000114 format "\"%s\""
Greg Watson4890a662003-06-23 01:01:17 +0000115 comment "Build date"
116end
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000117define COREBOOT_COMPILE_TIME
Greg Watson4890a662003-06-23 01:01:17 +0000118 default "$(shell date +%T)"
119 export always
Eric Biedermanb78c1972004-10-14 20:54:17 +0000120 format "\"%s\""
Greg Watson4890a662003-06-23 01:01:17 +0000121 comment "Build time"
122end
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000123define COREBOOT_COMPILE_BY
Greg Watson4890a662003-06-23 01:01:17 +0000124 default "$(shell whoami)"
125 export always
Eric Biedermanb78c1972004-10-14 20:54:17 +0000126 format "\"%s\""
Greg Watson4890a662003-06-23 01:01:17 +0000127 comment "Who build this image"
128end
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000129define COREBOOT_COMPILE_HOST
Greg Watson4890a662003-06-23 01:01:17 +0000130 default "$(shell hostname)"
131 export always
Eric Biedermanb78c1972004-10-14 20:54:17 +0000132 format "\"%s\""
Greg Watson4890a662003-06-23 01:01:17 +0000133 comment "Build host"
134end
135
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000136define COREBOOT_COMPILE_DOMAIN
Eric Biederman9bdb4602003-09-01 23:17:58 +0000137 default "$(shell dnsdomainname)"
Greg Watson4890a662003-06-23 01:01:17 +0000138 export always
Eric Biedermanb78c1972004-10-14 20:54:17 +0000139 format "\"%s\""
Greg Watson4890a662003-06-23 01:01:17 +0000140 comment "Build domain name"
141end
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000142define COREBOOT_COMPILER
Greg Watson4890a662003-06-23 01:01:17 +0000143 default "$(shell $(CC) $(CFLAGS) -v 2>&1 | tail -n 1)"
144 export always
Eric Biedermanb78c1972004-10-14 20:54:17 +0000145 format "\"%s\""
Greg Watson4890a662003-06-23 01:01:17 +0000146 comment "Build compiler"
147end
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000148define COREBOOT_LINKER
Stefan Reinauer7db27ee2006-02-19 14:43:48 +0000149 default "$(shell $(CC) -Wl,--version 2>&1 | grep version | tail -n 1)"
Greg Watson4890a662003-06-23 01:01:17 +0000150 export always
Eric Biedermanb78c1972004-10-14 20:54:17 +0000151 format "\"%s\""
Greg Watson4890a662003-06-23 01:01:17 +0000152 comment "Build linker"
153end
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000154define COREBOOT_ASSEMBLER
Greg Watson4890a662003-06-23 01:01:17 +0000155 default "$(shell touch dummy.s ; $(CC) -c -Wa,-v dummy.s 2>&1; rm -f dummy.s dummy.o )"
156 export always
Eric Biedermanb78c1972004-10-14 20:54:17 +0000157 format "\"%s\""
Greg Watson4890a662003-06-23 01:01:17 +0000158 comment "Build assembler"
159end
Greg Watson2b02b632003-07-21 14:00:53 +0000160define CONFIG_CHIP_CONFIGURE
161 default 0
162 export used
163 comment "Use new chip_configure method for configuring (non-pci) devices"
164end
Greg Watsone3da4d32003-11-09 23:29:42 +0000165define CONFIG_USE_INIT
166 default 0
arch import user (historical)6ca76362005-07-06 17:17:25 +0000167 export always
Greg Watsone3da4d32003-11-09 23:29:42 +0000168 comment "Use stage 1 initialization code"
169end
Greg Watson4890a662003-06-23 01:01:17 +0000170
171###############################################
172# ROM image options
173###############################################
174
175define HAVE_FALLBACK_BOOT
Ronald G. Minnich848d3362003-10-01 16:09:23 +0000176 format "%d"
Greg Watson4890a662003-06-23 01:01:17 +0000177 default 0
178 export always
179 comment "Set if fallback booting required"
180end
Yinghai Lud4b278c2006-10-04 20:46:15 +0000181define HAVE_FAILOVER_BOOT
182 format "%d"
183 default 0
184 export always
185 comment "Set if failover booting required"
186end
Greg Watson4890a662003-06-23 01:01:17 +0000187define USE_FALLBACK_IMAGE
Ronald G. Minnich848d3362003-10-01 16:09:23 +0000188 format "%d"
189 default 0
Greg Watson4890a662003-06-23 01:01:17 +0000190 export used
191 comment "Set to build a fallback image"
192end
Yinghai Lud4b278c2006-10-04 20:46:15 +0000193define USE_FAILOVER_IMAGE
194 format "%d"
195 default 0
196 export used
197 comment "Set to build a failover image"
198end
Greg Watson4890a662003-06-23 01:01:17 +0000199define FALLBACK_SIZE
200 default 65536
201 format "0x%x"
202 export used
Stefan Reinauerf5183cf2005-12-01 11:01:01 +0000203 comment "Default fallback image size"
Greg Watson4890a662003-06-23 01:01:17 +0000204end
Yinghai Lud4b278c2006-10-04 20:46:15 +0000205define FAILOVER_SIZE
206 default 0
207 format "0x%x"
208 export used
209 comment "Default failover image size"
210end
Greg Watson4890a662003-06-23 01:01:17 +0000211define ROM_SIZE
Ronald G. Minnichca34c042003-09-25 17:34:56 +0000212 default none
Greg Watson4890a662003-06-23 01:01:17 +0000213 format "0x%x"
214 export used
Stefan Reinauerf5183cf2005-12-01 11:01:01 +0000215 comment "Size of your ROM"
Greg Watson4890a662003-06-23 01:01:17 +0000216end
217define ROM_IMAGE_SIZE
218 default 65535
219 format "0x%x"
220 export always
Stefan Reinauerf5183cf2005-12-01 11:01:01 +0000221 comment "Default image size"
Greg Watson4890a662003-06-23 01:01:17 +0000222end
223define ROM_SECTION_SIZE
Greg Watson375505f2003-07-17 22:10:11 +0000224 default {FALLBACK_SIZE}
Greg Watson4890a662003-06-23 01:01:17 +0000225 format "0x%x"
226 export used
Stefan Reinauerf5183cf2005-12-01 11:01:01 +0000227 comment "Default rom section size"
Greg Watson4890a662003-06-23 01:01:17 +0000228end
229define ROM_SECTION_OFFSET
230 default {ROM_SIZE - FALLBACK_SIZE}
231 format "0x%x"
232 export used
Stefan Reinauerf5183cf2005-12-01 11:01:01 +0000233 comment "Default rom section offset"
Greg Watson4890a662003-06-23 01:01:17 +0000234end
235define PAYLOAD_SIZE
236 default {ROM_SECTION_SIZE - ROM_IMAGE_SIZE}
237 format "0x%x"
238 export always
Stefan Reinauerf5183cf2005-12-01 11:01:01 +0000239 comment "Default payload size"
Greg Watson4890a662003-06-23 01:01:17 +0000240end
241define _ROMBASE
242 default {PAYLOAD_SIZE}
243 format "0x%x"
244 export always
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000245 comment "Base address of coreboot in ROM"
Greg Watson499b3042003-07-28 21:15:13 +0000246end
Greg Watson0d4295f2003-11-15 15:29:30 +0000247define _ROMSTART
248 default none
249 format "0x%x"
250 export used
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000251 comment "Start address of coreboot in ROM"
Greg Watson0d4295f2003-11-15 15:29:30 +0000252end
Greg Watson499b3042003-07-28 21:15:13 +0000253define _RESET
254 default {_ROMBASE}
255 format "0x%x"
256 export always
257 comment "Hardware reset vector address"
Greg Watson4890a662003-06-23 01:01:17 +0000258end
Greg Watsoned462582003-11-05 18:21:30 +0000259define _EXCEPTION_VECTORS
260 default {_ROMBASE+0x100}
261 format "0x%x"
262 export always
263 comment "Address of exception vector table"
264end
Greg Watson4890a662003-06-23 01:01:17 +0000265define STACK_SIZE
266 default 0x2000
267 format "0x%x"
268 export always
269 comment "Default stack size"
270end
271define HEAP_SIZE
272 default 0x2000
273 format "0x%x"
Greg Watson9f461322004-03-23 17:41:15 +0000274 export always
Greg Watson4890a662003-06-23 01:01:17 +0000275 comment "Default heap size"
276end
277define _RAMBASE
Ronald G. Minnich57ffeb02003-07-30 03:05:20 +0000278 default none
Greg Watson4890a662003-06-23 01:01:17 +0000279 format "0x%x"
Greg Watson9cf8c2e2003-06-23 05:00:08 +0000280 export always
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000281 comment "Base address of coreboot in RAM"
Greg Watson4890a662003-06-23 01:01:17 +0000282end
Greg Watson0d4295f2003-11-15 15:29:30 +0000283define _RAMSTART
284 default none
285 format "0x%x"
286 export used
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000287 comment "Start address of coreboot in RAM"
Greg Watson0d4295f2003-11-15 15:29:30 +0000288end
Greg Watsoned462582003-11-05 18:21:30 +0000289define USE_DCACHE_RAM
Greg Watson4890a662003-06-23 01:01:17 +0000290 default 0
arch import user (historical)6ca76362005-07-06 17:17:25 +0000291 export always
Greg Watsoned462582003-11-05 18:21:30 +0000292 comment "Use data cache as temporary RAM if possible"
Greg Watson4890a662003-06-23 01:01:17 +0000293end
Marc Jones8ae8c882007-12-19 01:32:08 +0000294define CAR_FAM10
295 default 0
296 export always
297 comment "AMD family 10 CAR requires additional setup"
298end
Greg Watsoned462582003-11-05 18:21:30 +0000299define DCACHE_RAM_BASE
Yinghai Lud4b278c2006-10-04 20:46:15 +0000300 default 0xc0000
Greg Watson4890a662003-06-23 01:01:17 +0000301 format "0x%x"
Yinghai Lud4b278c2006-10-04 20:46:15 +0000302 export always
Greg Watsoned462582003-11-05 18:21:30 +0000303 comment "Base address of data cache when using it for temporary RAM"
Greg Watson4890a662003-06-23 01:01:17 +0000304end
Greg Watsoned462582003-11-05 18:21:30 +0000305define DCACHE_RAM_SIZE
Yinghai Lu9a791df2006-04-03 20:38:34 +0000306 default 0x1000
Greg Watson4890a662003-06-23 01:01:17 +0000307 format "0x%x"
Yinghai Lu9a791df2006-04-03 20:38:34 +0000308 export always
Greg Watsoned462582003-11-05 18:21:30 +0000309 comment "Size of data cache when using it for temporary RAM"
Greg Watson4890a662003-06-23 01:01:17 +0000310end
Yinghai Lu9a791df2006-04-03 20:38:34 +0000311define DCACHE_RAM_GLOBAL_VAR_SIZE
312 default 0
313 format "0x%x"
314 export always
315 comment "Size of region that for global variable of cache as ram stage"
316end
Yinghai Lud4b278c2006-10-04 20:46:15 +0000317define CONFIG_AP_CODE_IN_CAR
318 default 0
319 export always
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000320 comment "will copy coreboot_apc to AP cache ane execute in AP"
Yinghai Lud4b278c2006-10-04 20:46:15 +0000321end
322define MEM_TRAIN_SEQ
323 default 0
324 export always
325 comment "0: three for in bsp, 1: on every core0, 2: one for on bsp"
326end
327define WAIT_BEFORE_CPUS_INIT
328 default 0
329 export always
330 comment "execute cpus_ready_for_init if it is set to 1"
331end
Stefan Reinauer91232c12003-08-06 10:45:57 +0000332define XIP_ROM_BASE
Eric Biederman9bdb4602003-09-01 23:17:58 +0000333 default 0
Stefan Reinauer91232c12003-08-06 10:45:57 +0000334 format "0x%x"
335 export used
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000336 comment "Start address of area to cache during coreboot execution directly from ROM"
Stefan Reinauer91232c12003-08-06 10:45:57 +0000337end
338define XIP_ROM_SIZE
Eric Biederman9bdb4602003-09-01 23:17:58 +0000339 default 0
Stefan Reinauer91232c12003-08-06 10:45:57 +0000340 format "0x%x"
341 export used
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000342 comment "Size of area to cache during coreboot execution directly from ROM"
Stefan Reinauer91232c12003-08-06 10:45:57 +0000343end
Greg Watson4890a662003-06-23 01:01:17 +0000344define CONFIG_COMPRESS
345 default 1
346 export always
347 comment "Set for compressed image"
348end
349define CONFIG_UNCOMPRESSED
Ronald G. Minnichf8651ed2003-07-25 17:31:53 +0000350 format "%d"
Greg Watson4890a662003-06-23 01:01:17 +0000351 default {!CONFIG_COMPRESS}
352 export always
353 comment "Set for uncompressed image"
354end
Eric Biederman5cd81732004-03-11 15:01:31 +0000355define CONFIG_LB_MEM_TOPK
356 format "%d"
Yinghai Lu9a791df2006-04-03 20:38:34 +0000357 default 2048
Eric Biederman5cd81732004-03-11 15:01:31 +0000358 export always
359 comment "Kilobytes of memory to initialized before executing code from RAM"
360end
Greg Watson4890a662003-06-23 01:01:17 +0000361define HAVE_OPTION_TABLE
362 default 0
363 export always
364 comment "Export CMOS option table"
365end
366define USE_OPTION_TABLE
Ronald G. Minnich336b4592003-07-25 17:28:43 +0000367 format "%d"
Greg Watson4890a662003-06-23 01:01:17 +0000368 default {HAVE_OPTION_TABLE && !USE_FALLBACK_IMAGE}
369 export always
370 comment "Use option table"
371end
372
373###############################################
Eric Biederman5cd81732004-03-11 15:01:31 +0000374# CMOS variable options
375###############################################
376define LB_CKS_RANGE_START
377 default 49
378 format "%d"
379 export always
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000380 comment "First CMOS byte to use for coreboot options"
Eric Biederman5cd81732004-03-11 15:01:31 +0000381end
382define LB_CKS_RANGE_END
383 default 125
384 format "%d"
385 export always
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000386 comment "Last CMOS byte to use for coreboot options"
Eric Biederman5cd81732004-03-11 15:01:31 +0000387end
388define LB_CKS_LOC
389 default 126
390 format "%d"
391 export always
392 comment "Pair of bytes to use for CMOS checksum"
393end
394
395
396###############################################
Greg Watson4890a662003-06-23 01:01:17 +0000397# Build targets
398###############################################
399
400define CRT0
Stefan Reinauerd5994ce2004-05-27 13:54:38 +0000401 default "$(TOP)/src/arch/$(ARCH)/init/crt0.S.lb"
Greg Watson4890a662003-06-23 01:01:17 +0000402 export always
403 comment "Main initialization target"
404end
405
406###############################################
407# Debugging/Logging options
408###############################################
409
410define DEBUG
411 default 1
412 export always
413 comment "Enable debugging code"
414end
415define CONFIG_CONSOLE_VGA
416 default 0
417 export always
Torsten Duwe1f2f8002008-01-06 01:10:54 +0000418 comment "Log messages to any VGA-compatible device (may require *_ROM_RUN to bring up)"
Greg Watson4890a662003-06-23 01:01:17 +0000419end
Stefan Reinauerf5183cf2005-12-01 11:01:01 +0000420define CONFIG_CONSOLE_VGA_MULTI
421 default 0
422 export always
423 comment "Multi VGA console"
424end
Yinghai Lu2b396cd2006-05-18 16:54:30 +0000425define CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
426 default 0
427 export always
428 comment "Use onboard VGA instead of add on VGA card"
429end
Stefan Reinauerf05dcb82004-04-24 22:29:44 +0000430define CONFIG_CONSOLE_BTEXT
431 default 0
432 export always
433 comment "Log messages to btext fb console"
434end
Greg Watson4890a662003-06-23 01:01:17 +0000435define CONFIG_CONSOLE_LOGBUF
436 default 0
437 export always
438 comment "Log messages to buffer"
439end
440define CONFIG_CONSOLE_SROM
441 default 0
442 export always
443 comment "Log messages to SROM console"
444end
445define CONFIG_CONSOLE_SERIAL8250
446 default 0
447 export always
Eric Biederman9bdb4602003-09-01 23:17:58 +0000448 comment "Log messages to 8250 uart based serial console"
Greg Watson4890a662003-06-23 01:01:17 +0000449end
Yinghai Lud57241f2007-02-28 11:17:02 +0000450define CONFIG_USBDEBUG_DIRECT
451 default 0
452 export always
453 comment "Log messages to ehci debug port console"
454end
Ronald G. Minnichffc161e2003-07-23 01:42:29 +0000455define DEFAULT_CONSOLE_LOGLEVEL
456 default 7
457 export always
458 comment "Console will log at this level unless changed"
459end
Greg Watson4890a662003-06-23 01:01:17 +0000460define MAXIMUM_CONSOLE_LOGLEVEL
Greg Watsonc99bd5f2003-07-23 21:36:12 +0000461 default 8
Greg Watson4890a662003-06-23 01:01:17 +0000462 export always
Ronald G. Minnichffc161e2003-07-23 01:42:29 +0000463 comment "Error messages up to this level can be printed"
Greg Watson4890a662003-06-23 01:01:17 +0000464end
Ronald G. Minnichb9e06c22004-03-19 21:02:36 +0000465define CONFIG_SERIAL_POST
466 default 0
467 export always
468 comment "Enable SERIAL POST codes"
469end
Greg Watson4890a662003-06-23 01:01:17 +0000470define NO_POST
471 default none
Greg Watson9f461322004-03-23 17:41:15 +0000472 export used
Greg Watson4890a662003-06-23 01:01:17 +0000473 comment "Disable POST codes"
474end
Eric Biederman9bdb4602003-09-01 23:17:58 +0000475define TTYS0_BASE
476 default 0x3f8
Greg Watsoned462582003-11-05 18:21:30 +0000477 format "0x%x"
Eric Biederman9bdb4602003-09-01 23:17:58 +0000478 export always
479 comment "Base address for 8250 uart for the serial console"
480end
Greg Watson4890a662003-06-23 01:01:17 +0000481define TTYS0_BAUD
482 default 115200
483 export always
484 comment "Default baud rate for serial console"
485end
Greg Watsonbf5b5842004-01-14 17:08:14 +0000486define TTYS0_DIV
487 default none
488 format "%d"
489 export used
490 comment "Allow UART divisor to be set explicitly"
491end
Eric Biederman9bdb4602003-09-01 23:17:58 +0000492define TTYS0_LCS
493 default 0x3
Greg Watsoned462582003-11-05 18:21:30 +0000494 format "0x%x"
Eric Biederman9bdb4602003-09-01 23:17:58 +0000495 export always
496 comment "Default flow control settings for the 8250 serial console uart"
497end
Yinghai Lu5f9624d2006-10-04 22:56:21 +0000498
499define CONFIG_USE_PRINTK_IN_CAR
500 default 0
501 export always
502 comment "use printk instead of print in CAR stage code"
503end
504
Eric Biederman9bdb4602003-09-01 23:17:58 +0000505
Greg Watson4890a662003-06-23 01:01:17 +0000506###############################################
507# Mainboard options
508###############################################
509
510define MAINBOARD
511 default "Mainboard_not_set"
512 export always
513 comment "Mainboard name"
514end
515define MAINBOARD_PART_NUMBER
516 default "Part_number_not_set"
517 export always
Eric Biedermanb78c1972004-10-14 20:54:17 +0000518 format "\"%s\""
Greg Watson4890a662003-06-23 01:01:17 +0000519 comment "Part number of mainboard"
520end
521define MAINBOARD_VENDOR
522 default "Vendor_not_set"
523 export always
Eric Biedermanb78c1972004-10-14 20:54:17 +0000524 format "\"%s\""
Greg Watson4890a662003-06-23 01:01:17 +0000525 comment "Vendor of mainboard"
526end
Eric Biedermanb78c1972004-10-14 20:54:17 +0000527define MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
528 default 0
529 export always
530 comment "PCI Vendor ID of mainboard manufacturer"
531end
532define MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
533 default 0
534 format "0x%x"
535 export always
536 comment "PCI susbsystem device id assigned my mainboard manufacturer"
537end
Eric Biederman5cd81732004-03-11 15:01:31 +0000538define MAINBOARD_POWER_ON_AFTER_POWER_FAIL
539 default none
540 export used
541 comment "Default power on after power fail setting"
542end
Greg Watson499b3042003-07-28 21:15:13 +0000543define CONFIG_SYS_CLK_FREQ
544 default none
545 export used
546 comment "System clock frequency in MHz"
547end
Richard Smith2a7352c2006-04-23 23:12:21 +0000548define CONFIG_MAX_PCI_BUSES
549 default 255
550 export always
551 comment "Maximum number of PCI buses to search for devices"
552end
Greg Watson4890a662003-06-23 01:01:17 +0000553###############################################
554# SMP options
555###############################################
556
557define CONFIG_SMP
Ronald G. Minnich1807c372003-06-24 19:44:00 +0000558 default 0
Greg Watson4890a662003-06-23 01:01:17 +0000559 export always
560 comment "Define if we support SMP"
561end
Ronald G. Minnich57ffeb02003-07-30 03:05:20 +0000562define CONFIG_MAX_CPUS
563 default 1
564 export always
Eric Biederman9bdb4602003-09-01 23:17:58 +0000565 comment "Maximum CPU count for this machine"
Ronald G. Minnich57ffeb02003-07-30 03:05:20 +0000566end
arch import user (historical)ef03afa2005-07-06 17:15:30 +0000567define CONFIG_MAX_PHYSICAL_CPUS
568 default 1
569 export always
570 comment "Maximum physical CPU count for this machine"
571end
Eric Biederman9bdb4602003-09-01 23:17:58 +0000572define CONFIG_LOGICAL_CPUS
573 default 0
574 export always
575 comment "Should multiple cpus per die be enabled?"
576end
Greg Watson4890a662003-06-23 01:01:17 +0000577define HAVE_MP_TABLE
578 default none
Greg Watson9f461322004-03-23 17:41:15 +0000579 export used
Greg Watson4890a662003-06-23 01:01:17 +0000580 comment "Define to build an MP table"
581end
arch import user (historical)ef03afa2005-07-06 17:15:30 +0000582define SERIAL_CPU_INIT
583 default 1
584 export always
585 comment "Serialize CPU init"
586end
Stefan Reinauerf5183cf2005-12-01 11:01:01 +0000587define APIC_ID_OFFSET
588 default 0
589 export always
590 comment "We need to share this value between cache_as_ram_auto.c and northbridge.c"
591end
592define ENABLE_APIC_EXT_ID
593 default 0
594 export always
595 comment "Enable APIC ext id mode 8 bit"
596end
597define LIFT_BSP_APIC_ID
598 default 0
599 export always
600 comment "decide if we lift bsp apic id while ap apic id"
601end
Greg Watson4890a662003-06-23 01:01:17 +0000602###############################################
603# Boot options
604###############################################
605
Ed Swierkbe13dc72006-12-15 12:56:28 +0000606define CONFIG_IDE_PAYLOAD
Greg Watson4890a662003-06-23 01:01:17 +0000607 default 0
608 export always
609 comment "Boot from IDE device"
610end
Ed Swierkbe13dc72006-12-15 12:56:28 +0000611define CONFIG_ROM_PAYLOAD
Greg Watson4890a662003-06-23 01:01:17 +0000612 default 0
613 export always
614 comment "Boot image is located in ROM"
615end
Ed Swierkbe13dc72006-12-15 12:56:28 +0000616define CONFIG_ROM_PAYLOAD_START
Greg Watson4890a662003-06-23 01:01:17 +0000617 default {0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1}
618 format "0x%x"
619 export always
Stefan Reinauerf5183cf2005-12-01 11:01:01 +0000620 comment "ROM stream start location"
Greg Watson4890a662003-06-23 01:01:17 +0000621end
Ed Swierk1a7a5b42006-12-15 11:42:16 +0000622define CONFIG_COMPRESSED_PAYLOAD_NRV2B
Carl-Daniel Hailfingercba07dd2006-09-14 15:12:36 +0000623 default 0
624 export always
625 comment "NRV2B compressed boot image is located in ROM"
626end
Ed Swierk1a7a5b42006-12-15 11:42:16 +0000627define CONFIG_COMPRESSED_PAYLOAD_LZMA
Carl-Daniel Hailfingercba07dd2006-09-14 15:12:36 +0000628 default 0
629 export always
630 comment "LZMA compressed boot image is located in ROM"
Stefan Reinaueread73682006-05-02 12:05:13 +0000631end
Ed Swierk1a7a5b42006-12-15 11:42:16 +0000632define CONFIG_PRECOMPRESSED_PAYLOAD
Stefan Reinauer8ad7c062006-08-03 16:19:27 +0000633 default 0
634 export always
635 comment "boot image is already compressed"
636end
Ed Swierkbe13dc72006-12-15 12:56:28 +0000637define CONFIG_SERIAL_PAYLOAD
Stefan Reinauerebafa4d2006-10-07 00:13:24 +0000638 default 0
639 export always
640 comment "Download boot image from serial port"
641end
Ed Swierkbe13dc72006-12-15 12:56:28 +0000642define CONFIG_FS_PAYLOAD
Greg Watsonb8603e22004-03-13 03:18:32 +0000643 default 0
644 export always
645 comment "Boot from a filesystem"
646end
647define CONFIG_FS_EXT2
648 default 0
649 export always
650 comment "Enable ext2 filesystem support"
651end
652define CONFIG_FS_ISO9660
653 default 0
654 export always
655 comment "Enable ISO9660 filesystem support"
656end
Greg Watson711c8bd2004-03-13 04:04:58 +0000657define CONFIG_FS_FAT
658 default 0
659 export always
660 comment "Enable FAT filesystem support"
661end
Greg Watsonb8603e22004-03-13 03:18:32 +0000662define AUTOBOOT_DELAY
663 default 2
664 export always
665 comment "Delay (in seconds) before autobooting"
666end
667define AUTOBOOT_CMDLINE
668 default "hdc1:/vmlinuz root=/dev/hdc3 console=tty0 console=ttyS0,115200"
669 export always
670 format "\"%s\""
671 comment "Default command line when autobooting"
672end
Greg Watson4890a662003-06-23 01:01:17 +0000673
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000674define USE_WATCHDOG_ON_BOOT
675 default 0
676 export always
677 comment "Use the watchdog on booting"
678end
679
680###############################################
681# Plugin Device support options
682###############################################
683
684define CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT
685 default 1
686 export always
687 comment "Enable support for plugin Hypertransport busses"
688end
689define CONFIG_AGP_PLUGIN_SUPPORT
690 default 1
691 export always
692 comment "Enable support for plugin AGP busses"
693end
694define CONFIG_CARDBUS_PLUGIN_SUPPORT
695 default 1
696 export always
697 comment "Enable support cardbus plugin cards"
698end
699define CONFIG_PCIX_PLUGIN_SUPPORT
700 default 1
701 export always
702 comment "Enable support for plugin PCI-X busses"
703end
704define CONFIG_PCIEXP_PLUGIN_SUPPORT
705 default 1
706 export always
707 comment "Enable support for plugin PCI-E busses"
708end
709
Greg Watson4890a662003-06-23 01:01:17 +0000710###############################################
711# IRQ options
712###############################################
713
714define HAVE_PIRQ_TABLE
715 default none
Greg Watson9f461322004-03-23 17:41:15 +0000716 export used
Greg Watson4890a662003-06-23 01:01:17 +0000717 comment "Define if we have a PIRQ table"
718end
Nikolay Petukhov9c2255c2008-03-29 16:59:27 +0000719define PIRQ_ROUTE
720 default 0
721 export used
722 comment "Define if we have a PIRQ table and want routing IRQs"
723end
Greg Watson4890a662003-06-23 01:01:17 +0000724define IRQ_SLOT_COUNT
725 default none
Greg Watson9f461322004-03-23 17:41:15 +0000726 export used
Greg Watson4890a662003-06-23 01:01:17 +0000727 comment "Number of IRQ slots"
728end
729define CONFIG_PCIBIOS_IRQ
730 default none
Greg Watson9f461322004-03-23 17:41:15 +0000731 export used
Greg Watson4890a662003-06-23 01:01:17 +0000732 comment "PCIBIOS IRQ support"
733end
734define CONFIG_IOAPIC
735 default none
Greg Watson9f461322004-03-23 17:41:15 +0000736 export used
Greg Watson4890a662003-06-23 01:01:17 +0000737 comment "IOAPIC support"
738end
739
740###############################################
741# IDE specific options
742###############################################
743
Greg Watsoncfaeaf62004-03-13 03:28:05 +0000744define CONFIG_IDE
745 default 0
746 export always
747 comment "Define to include IDE support"
748end
Greg Watson4890a662003-06-23 01:01:17 +0000749define IDE_BOOT_DRIVE
750 default 0
751 export always
752 comment "Disk number of boot drive"
753end
754define IDE_SWAB
755 default none
Greg Watson9f461322004-03-23 17:41:15 +0000756 export used
Greg Watson4890a662003-06-23 01:01:17 +0000757 comment "Swap bytes when reading from IDE device"
758end
759define IDE_OFFSET
760 default 0
761 export always
762 comment "Sector at which to start searching for boot image"
763end
764
765###############################################
Greg Watsoned462582003-11-05 18:21:30 +0000766# Options for memory mapped I/O
767###############################################
768
Yinghai Lu5f9624d2006-10-04 22:56:21 +0000769define PCI_IO_CFG_EXT
770 default 0
771 export always
772 comment "allow 4K register space via io CFG port"
773end
774
Greg Watsoned462582003-11-05 18:21:30 +0000775define PCIC0_CFGADDR
776 default none
777 format "0x%x"
778 export used
Greg Watson90947232004-01-22 01:03:41 +0000779 comment "Address of PCI Configuration Address Register"
Greg Watsoned462582003-11-05 18:21:30 +0000780end
781define PCIC0_CFGDATA
782 default none
783 format "0x%x"
784 export used
Greg Watson90947232004-01-22 01:03:41 +0000785 comment "Address of PCI Configuration Data Register"
786end
787define ISA_IO_BASE
788 default none
789 format "0x%x"
790 export used
791 comment "Base address of PCI/ISA I/O address range"
792end
793define ISA_MEM_BASE
794 default none
795 format "0x%x"
796 export used
797 comment "Base address of PCI/ISA memory address range"
Greg Watsoned462582003-11-05 18:21:30 +0000798end
Greg Watsone3da4d32003-11-09 23:29:42 +0000799define PNP_CFGADDR
800 default none
801 format "0x%x"
802 export used
Greg Watson90947232004-01-22 01:03:41 +0000803 comment "PNP Configuration Address Register offset"
Greg Watsone3da4d32003-11-09 23:29:42 +0000804end
805define PNP_CFGDATA
806 default none
807 format "0x%x"
808 export used
Greg Watson90947232004-01-22 01:03:41 +0000809 comment "PNP Configuration Data Register offset"
Greg Watsone3da4d32003-11-09 23:29:42 +0000810end
Greg Watson90947232004-01-22 01:03:41 +0000811define _IO_BASE
Greg Watsoned462582003-11-05 18:21:30 +0000812 default none
813 format "0x%x"
814 export used
Greg Watson90947232004-01-22 01:03:41 +0000815 comment "Base address of memory mapped I/O operations"
Greg Watsoned462582003-11-05 18:21:30 +0000816end
817
818###############################################
819# Options for embedded systems
820###############################################
821
822define EMBEDDED_RAM_SIZE
823 default none
824 export used
825 comment "Embedded boards generally have fixed RAM size"
826end
827
828###############################################
Greg Watson4890a662003-06-23 01:01:17 +0000829# Misc options
830###############################################
831
Eric Biederman018d8dd2004-11-04 11:04:33 +0000832define CONFIG_CHIP_NAME
833 default 0
834 export always
835 comment "Compile in the chip name"
836end
837
Eric Biedermanf8a2ddd2004-10-30 08:05:41 +0000838define CONFIG_GDB_STUB
839 default 0
840 export used
841 comment "Compile in gdb stub support?"
842end
843
Eric Biederman6e53f502004-10-27 08:53:57 +0000844define HAVE_INIT_TIMER
845 default 0
846 export always
847 comment "Have a init_timer function"
848end
Greg Watson4890a662003-06-23 01:01:17 +0000849define HAVE_HARD_RESET
850 default none
851 export used
852 comment "Have hard reset"
853end
854define MEMORY_HOLE
855 default none
856 export used
857 comment "Set to deal with memory hole"
858end
Greg Watson4890a662003-06-23 01:01:17 +0000859define MAX_REBOOT_CNT
Eric Biederman9bdb4602003-09-01 23:17:58 +0000860 default 3
Greg Watson4890a662003-06-23 01:01:17 +0000861 export always
862 comment "Set maximum reboots"
863end
Greg Watson4890a662003-06-23 01:01:17 +0000864
865###############################################
866# Misc device options
867###############################################
868
Ronald Hoogenboom56cf01f2008-02-25 19:36:20 +0000869define HAVE_FANCTL
870 default 0
871 export used
872 comment "Include board specific FAN control initialization"
873end
Greg Watson4890a662003-06-23 01:01:17 +0000874define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
Eric Biederman9bdb4602003-09-01 23:17:58 +0000875 default 0
Greg Watson4890a662003-06-23 01:01:17 +0000876 export used
Eric Biederman9bdb4602003-09-01 23:17:58 +0000877 comment "Use timer2 to callibrate the x86 time stamp counter"
Greg Watson4890a662003-06-23 01:01:17 +0000878end
879define INTEL_PPRO_MTRR
880 default none
Greg Watson7011f9f2004-03-25 04:41:27 +0000881 export used
Greg Watson4890a662003-06-23 01:01:17 +0000882 comment ""
883end
Greg Watson4890a662003-06-23 01:01:17 +0000884define CONFIG_UDELAY_TSC
885 default 0
886 export used
Eric Biederman9bdb4602003-09-01 23:17:58 +0000887 comment "Implement udelay with the x86 time stamp counter"
Greg Watson4890a662003-06-23 01:01:17 +0000888end
Stefan Reinauer453dfdf2005-12-04 17:50:32 +0000889define CONFIG_UDELAY_IO
890 default 0
891 export used
892 comment "Implement udelay with x86 io registers"
893end
Stefan Reinauer7899a5f2003-11-19 12:29:08 +0000894define FAKE_SPDROM
895 default 0
896 export always
897 comment "Use this to fake spd rom values"
898end
Greg Watson4890a662003-06-23 01:01:17 +0000899
Stefan Reinauer688b3852004-01-28 16:56:14 +0000900define HAVE_ACPI_TABLES
901 default 0
902 export always
903 comment "Define to build ACPI tables"
904end
905
Stefan Reinauerf622d592005-11-26 16:56:05 +0000906define ACPI_SSDTX_NUM
907 default 0
908 export always
909 comment "extra ssdt num for PCI Device"
910end
911
Li-Ta Loe5266692004-03-23 21:28:05 +0000912define AGP_APERTURE_SIZE
913 default none
914 export used
Li-Ta Loa60bf672004-05-10 19:33:27 +0000915 format "0x%x"
Li-Ta Loe5266692004-03-23 21:28:05 +0000916 comment "AGP graphics virtual memory aperture size"
917end
Stefan Reinauer688b3852004-01-28 16:56:14 +0000918
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000919define HT_CHAIN_UNITID_BASE
920 default 1
921 export always
Yinghai Lud4b278c2006-10-04 20:46:15 +0000922 comment "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0"
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000923end
924
925define HT_CHAIN_END_UNITID_BASE
926 default 0x20
927 export always
928 comment "this will be unit id of the end of hypertransport chain (usually the real SB) if it is small than HT_CHAIN_UNITID_BASE, it could be 0"
929end
930
931define SB_HT_CHAIN_UNITID_OFFSET_ONLY
932 default 1
933 export always
934 comment "this will decided if only offset SB hypertransport chain"
935end
936
Yinghai Lud4b278c2006-10-04 20:46:15 +0000937define SB_HT_CHAIN_ON_BUS0
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000938 default 0
939 export always
Yinghai Lud4b278c2006-10-04 20:46:15 +0000940 comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
Stefan Reinauer7ce8c542005-12-02 21:52:30 +0000941end
942
Yinghai Lu5f9624d2006-10-04 22:56:21 +0000943define PCI_BUS_SEGN_BITS
944 default 0
945 export always
946 comment "It could be 0, 1, 2, 3 and 4 only"
947end
948
949define MMCONF_SUPPORT
950 default 0
951 export always
952 comment "enable mmconfig for pci conf"
953end
954
Marc Jones8ae8c882007-12-19 01:32:08 +0000955define MMCONF_SUPPORT_DEFAULT
956 default 0
957 export always
958 comment "enable mmconfig for pci conf"
959end
960
Yinghai Lud4b278c2006-10-04 20:46:15 +0000961define HW_MEM_HOLE_SIZEK
arch import user (historical)ef03afa2005-07-06 17:15:30 +0000962 default 0
963 export always
Stefan Reinauerf5183cf2005-12-01 11:01:01 +0000964 comment "Opteron E0 later memory hole size in K, 0 mean disable"
965end
966
Yinghai Lud4b278c2006-10-04 20:46:15 +0000967define HW_MEM_HOLE_SIZE_AUTO_INC
Stefan Reinauerf5183cf2005-12-01 11:01:01 +0000968 default 0
969 export always
970 comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek"
971end
972
Marc Jones8ae8c882007-12-19 01:32:08 +0000973define CONFIG_VAR_MTRR_HOLE
974 default 1
975 export always
976 comment "using hole in MTRR instead of increasing method"
977end
978
Stefan Reinauerf5183cf2005-12-01 11:01:01 +0000979define K8_HT_FREQ_1G_SUPPORT
Yinghai Lud4b278c2006-10-04 20:46:15 +0000980 default 0
Stefan Reinauerf5183cf2005-12-01 11:01:01 +0000981 export always
982 comment "Optern E0 later could support 1G HT, but still depends MB design"
arch import user (historical)ef03afa2005-07-06 17:15:30 +0000983end
984
Yinghai Lud4b278c2006-10-04 20:46:15 +0000985define K8_REV_F_SUPPORT
986 default 0
987 export always
988 comment "Opteron Rev F (DDR2) support"
989end
990
991define CBB
992 default 0
993 export always
994 comment "Opteron cpu bus num base"
995end
996
997define CDB
998 default 0x18
999 export always
1000 comment "Opteron cpu device num base"
1001end
1002
Marc Jones8ae8c882007-12-19 01:32:08 +00001003define HT3_SUPPORT
1004 default 0
1005 export always
1006 comment "Hypertransport 3 support, include ac HT and unganged sublink feature"
1007end
1008
1009define EXT_RT_TBL_SUPPORT
1010 default 0
1011 export always
1012 comment "support AMD family 10 extended routing table via F0x158, normally is enabled when node nums is greater than 8"
1013end
1014
1015define EXT_CONF_SUPPORT
1016 default 0
1017 export always
1018 comment "support AMD family 10 extended config space for ram, bus, io, mmio via F1x110, normally is enabled when HT3 is enabled and non ht chain nums is greater than 4"
1019end
1020
Yinghai Lud4b278c2006-10-04 20:46:15 +00001021define DIMM_SUPPORT
1022 default 0x0108
1023 format "0x%x"
1024 export always
1025 comment "DIMM support: bit 0 - sdram, bit 1: ddr1, bit 2: ddr2, bit 3: ddr3, bit 4: fbdimm, bit 8: reg"
1026end
1027
1028define CPU_SOCKET_TYPE
1029 default 0x10
1030 export always
1031 comment "cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3"
1032end
1033
1034define CPU_ADDR_BITS
1035 default 36
1036 export always
Marc Jones8ae8c882007-12-19 01:32:08 +00001037 comment "CPU hardware address lines num, for AMD K8 could be 40, and AMD family 10 could be 48"
Yinghai Lud4b278c2006-10-04 20:46:15 +00001038end
1039
Torsten Duwe1f2f8002008-01-06 01:10:54 +00001040define CONFIG_VGA_ROM_RUN
1041 default 0
1042 export always
1043 comment "Init x86 ROMs on VGA-class PCI devices"
1044end
1045
arch import user (historical)98d0d302005-07-06 17:13:46 +00001046define CONFIG_PCI_ROM_RUN
1047 default 0
1048 export always
Torsten Duwe1f2f8002008-01-06 01:10:54 +00001049 comment "Init x86 ROMs on all PCI devices"
arch import user (historical)98d0d302005-07-06 17:13:46 +00001050end
1051
Stefan Reinauerf5183cf2005-12-01 11:01:01 +00001052define CONFIG_PCI_64BIT_PREF_MEM
1053 default 0
1054 export always
1055 comment "allow PCI device get 4G above Region as pref mem"
1056end
1057
Marc Jones8ae8c882007-12-19 01:32:08 +00001058define CONFIG_AMDMCT
Yinghai Lud57241f2007-02-28 11:17:02 +00001059 default 0
1060 export always
Marc Jones8ae8c882007-12-19 01:32:08 +00001061 comment "use AMD MCT to init RAM instead of native code"
Yinghai Lud57241f2007-02-28 11:17:02 +00001062end
1063
Ronald G. Minnich2ad85db2006-09-20 16:39:30 +00001064define CONFIG_VIDEO_MB
1065 default none
1066 export used
1067 comment "Integrated graphics with UMA has dynamic setup"
1068end
1069
Juergen Beisert37f16692007-10-07 21:00:02 +00001070define CONFIG_SPLASH_GRAPHIC
1071 default 0
1072 export used
1073 comment "Paint a splash screen"
1074end
1075
Juergen Beisert4ac32172007-10-05 21:00:10 +00001076define CONFIG_GX1_VIDEO
1077 default 0
1078 export used
1079 comment "Build in GX1's graphic support"
1080end
Ronald G. Minnich2ad85db2006-09-20 16:39:30 +00001081
Juergen Beisert4ac32172007-10-05 21:00:10 +00001082define CONFIG_GX1_VIDEOMODE
1083 default none
1084 export used
1085 comment "Define video mode after reset"
1086# could be
1087# 0 for 640x480
1088# 1 for 800x600
1089# 2 for 1024x768
1090# 3 for 1280x960
1091# 4 for 1280x1024
1092end
arch import user (historical)98d0d302005-07-06 17:13:46 +00001093
Greg Watson062d5402003-07-17 13:14:07 +00001094###############################################
Ronald G. Minniche1313fa2003-09-26 15:23:53 +00001095# Board specific options
Greg Watson062d5402003-07-17 13:14:07 +00001096###############################################
1097
1098###############################################
1099# Options for motorola/sandpoint
1100###############################################
1101define CONFIG_SANDPOINT_ALTIMUS
1102 default 0
Greg Watson375505f2003-07-17 22:10:11 +00001103 export never
Greg Watson062d5402003-07-17 13:14:07 +00001104 comment "Configure Sandpoint with Altimus PMC"
1105end
1106define CONFIG_SANDPOINT_TALUS
1107 default 0
Greg Watson375505f2003-07-17 22:10:11 +00001108 export never
Greg Watson062d5402003-07-17 13:14:07 +00001109 comment "Configure Sandpoint with Talus PMC"
1110end
1111define CONFIG_SANDPOINT_UNITY
1112 default 0
Greg Watson375505f2003-07-17 22:10:11 +00001113 export never
Greg Watson062d5402003-07-17 13:14:07 +00001114 comment "Configure Sandpoint with Unity PMC"
1115end
1116define CONFIG_SANDPOINT_VALIS
1117 default 0
Greg Watson375505f2003-07-17 22:10:11 +00001118 export never
Greg Watson062d5402003-07-17 13:14:07 +00001119 comment "Configure Sandpoint with Valis PMC"
1120end
1121define CONFIG_SANDPOINT_GYRUS
1122 default 0
Greg Watson375505f2003-07-17 22:10:11 +00001123 export never
Greg Watson062d5402003-07-17 13:14:07 +00001124 comment "Configure Sandpoint with Gyrus PMC"
1125end
Greg Watson24aa3c82004-01-13 22:01:09 +00001126
1127###############################################
1128# Options for totalimpact/briq
1129###############################################
1130define CONFIG_BRIQ_750FX
1131 default 0
1132 export never
1133 comment "Configure briQ with PowerPC 750FX"
1134end
1135define CONFIG_BRIQ_7400
1136 default 0
1137 export never
1138 comment "Configure briQ with PowerPC G4"
1139end