blob: f304545b74bdab584cd23d49432722a8d6d94643 [file] [log] [blame]
Uwe Hermannb80dbf02007-04-22 19:08:13 +00001/*
Stefan Reinauer7e61e452008-01-18 10:35:56 +00002 * This file is part of the coreboot project.
Uwe Hermannb80dbf02007-04-22 19:08:13 +00003 *
4 * Copyright (C) 2005 Linux Networx
5 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
Yinghai Lu13f1c2a2005-07-08 02:49:49 +000020
21#include <console/console.h>
22#include <device/device.h>
23#include <device/pci.h>
24#include <device/pci_ids.h>
25#include <device/pciexp.h>
26
Yinghai Lu13f1c2a2005-07-08 02:49:49 +000027static void pciexp_tune_dev(device_t dev)
28{
29 unsigned cap;
30
31 cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
32 if (!cap) {
33 /* error... */
34 return;
35 }
Stefan Reinauerf6eb88a2010-01-17 13:54:08 +000036#ifdef CONFIG_PCIE_TUNING
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +000037 printk(BIOS_DEBUG, "PCIe: tuning %s\n", dev_path(dev));
Stefan Reinauerf6eb88a2010-01-17 13:54:08 +000038
39 // TODO make this depending on ASPM
40 /* Enable ASPM Role Based Error Reporting */
41 u32 reg32;
42 reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP);
43 reg32 |= PCI_EXP_DEVCAP_RBER;
44 pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32);
45#endif
Yinghai Lu13f1c2a2005-07-08 02:49:49 +000046}
47
Stefan Reinauer14e22772010-04-27 06:56:47 +000048unsigned int pciexp_scan_bus(struct bus *bus,
49 unsigned min_devfn, unsigned max_devfn,
Yinghai Lu13f1c2a2005-07-08 02:49:49 +000050 unsigned int max)
51{
52 device_t child;
53 max = pci_scan_bus(bus, min_devfn, max_devfn, max);
54 for(child = bus->children; child; child = child->sibling) {
Stefan Reinauer2b34db82009-02-28 20:10:20 +000055 if ( (child->path.pci.devfn < min_devfn) ||
56 (child->path.pci.devfn > max_devfn))
Yinghai Lu13f1c2a2005-07-08 02:49:49 +000057 {
58 continue;
59 }
60 pciexp_tune_dev(child);
61 }
62 return max;
63}
64
Yinghai Lu13f1c2a2005-07-08 02:49:49 +000065unsigned int pciexp_scan_bridge(device_t dev, unsigned int max)
66{
67 return do_pci_scan_bridge(dev, max, pciexp_scan_bus);
68}
69
70/** Default device operations for PCI Express bridges */
71static struct pci_operations pciexp_bus_ops_pci = {
72 .set_subsystem = 0,
73};
74
75struct device_operations default_pciexp_ops_bus = {
76 .read_resources = pci_bus_read_resources,
77 .set_resources = pci_dev_set_resources,
78 .enable_resources = pci_bus_enable_resources,
79 .init = 0,
80 .scan_bus = pciexp_scan_bridge,
81 .enable = 0,
82 .reset_bus = pci_bus_reset,
83 .ops_pci = &pciexp_bus_ops_pci,
84};