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review.coreboot.org / coreboot / d3801f4f6fe985b7c16ada84a457da25f23b87a0 / . / src / cpu / x86 / Kconfig
blob: 0eaee2ed40bca6fb5036b5598428c9ede6319783 [file] [log] [blame]
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]1config SERIAL_CPU_INIT
2 bool
3 default y
4
Patrick Georgi88f55b22009-09-25 18:43:02 +0000[diff] [blame]5config WAIT_BEFORE_CPUS_INIT
6 bool
7 default n
8
Patrick Georgi0e9a9252009-10-06 20:48:07 +0000[diff] [blame]9config UDELAY_IO
10 bool
Patrick Georgi1f807fd2010-01-04 20:09:27 +0000[diff] [blame]11 default y if !UDELAY_LAPIC && !UDELAY_TSC
Patrick Georgi0e9a9252009-10-06 20:48:07 +0000[diff] [blame]12 default n
13
14config UDELAY_LAPIC
15 bool
16 default n
17
Ronald G. Minnich669c4a92009-08-29 03:00:51 +0000[diff] [blame]18config UDELAY_TSC
19 bool
20 default n
21
efdesign9878834b72011-08-04 16:18:16 -0600[diff] [blame]22config UDELAY_TIMER2
23 bool
24 default n
25
Patrick Georgia4c0a1d2010-09-08 10:58:02 +0000[diff] [blame]26config TSC_CALIBRATE_WITH_IO
Ronald G. Minnich669c4a92009-08-29 03:00:51 +0000[diff] [blame]27 bool
28 default n
29
Uwe Hermannf9d4c2b2009-08-25 12:19:28 +0000[diff] [blame]30config XIP_ROM_SIZE
Patrick Georgi0588d192009-08-12 15:00:51 +0000[diff] [blame]31 hex
Patrick Georgi1c93d902012-03-16 21:16:55 +0100[diff] [blame]32 default ROM_SIZE if ROMCC
Patrick Georgif1ce6f22010-04-12 09:50:53 +0000[diff] [blame]33 default 0x10000
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000[diff] [blame]34
35config CPU_ADDR_BITS
36 int
37 default 36
38
39config LOGICAL_CPUS
40 bool
41 default y
42
Stefan Reinauer00093a82011-11-02 16:12:34 -0700[diff] [blame]43config CACHE_ROM
44 bool
45 default n
Duncan Laurie8bb77232012-01-09 22:11:25 -0800[diff] [blame]46
47config SMM_TSEG
48 bool
49 default n
50
51config SMM_TSEG_SIZE
52 hex
53 default 0