Angel Pons | 80d9238 | 2020-04-05 15:47:00 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
| 6 | #include <device/pci_ids.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 7 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 9 | #include <arch/ioapic.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 10 | #include <acpi/acpi.h> |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 11 | #include <cpu/x86/smm.h> |
| 12 | #include <bootstate.h> |
| 13 | |
| 14 | #include <soc/lpc.h> |
| 15 | #include <soc/pci_devs.h> |
| 16 | #include <soc/ramstage.h> |
| 17 | #include <soc/iomap.h> |
| 18 | #include <soc/pcr.h> |
| 19 | #include <soc/p2sb.h> |
| 20 | #include <soc/acpi.h> |
| 21 | |
| 22 | #include "chip.h" |
| 23 | |
Kyösti Mälkki | 04a4037 | 2021-06-06 08:04:28 +0300 | [diff] [blame] | 24 | /* PCH I/O APIC redirection entries */ |
| 25 | #define PCH_REDIR_ETR 120 |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 26 | |
| 27 | /** |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 28 | * Set miscellaneous static southbridge features. |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 29 | * |
| 30 | * @param dev PCI device with I/O APIC control registers |
| 31 | */ |
| 32 | static void pch_enable_ioapic(struct device *dev) |
| 33 | { |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 34 | /* affirm full set of redirection table entries ("write once") */ |
Kyösti Mälkki | 04a4037 | 2021-06-06 08:04:28 +0300 | [diff] [blame] | 35 | ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR); |
Kyösti Mälkki | ea6d12a | 2021-06-08 11:25:29 +0300 | [diff] [blame] | 36 | |
Kyösti Mälkki | 682613f | 2021-06-08 11:31:19 +0300 | [diff] [blame] | 37 | setup_ioapic((void *)IO_APIC_ADDR, IO_APIC0); |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 38 | } |
| 39 | |
Stephen Douthit | 56a74bc | 2019-08-05 12:49:08 -0400 | [diff] [blame] | 40 | /* interrupt router lookup for internal devices */ |
| 41 | struct dnv_ir_lut { |
| 42 | /* (dev << 3) | fn */ |
| 43 | u8 devfn; |
| 44 | u8 ir; |
| 45 | }; |
| 46 | |
| 47 | #define DEVFN(dev, fn) ((dev << 3) | (fn)) |
| 48 | |
| 49 | static const struct dnv_ir_lut dnv_ir_lut[] = { |
| 50 | {.devfn = DEVFN(0x05, 0), .ir = 3}, /* RCEC */ |
| 51 | {.devfn = DEVFN(0x06, 0), .ir = 4}, /* Virtual RP to QAT */ |
| 52 | {.devfn = DEVFN(0x09, 0), .ir = 7}, /* PCIe RP0 */ |
| 53 | {.devfn = DEVFN(0x0a, 0), .ir = 7}, /* PCIe RP1 */ |
| 54 | {.devfn = DEVFN(0x0b, 0), .ir = 7}, /* PCIe RP2 */ |
| 55 | {.devfn = DEVFN(0x0c, 0), .ir = 7}, /* PCIe RP3 */ |
| 56 | {.devfn = DEVFN(0x0e, 0), .ir = 8}, /* PCIe RP4 */ |
| 57 | {.devfn = DEVFN(0x0f, 0), .ir = 8}, /* PCIe RP5 */ |
| 58 | {.devfn = DEVFN(0x10, 0), .ir = 8}, /* PCIe RP6 */ |
| 59 | {.devfn = DEVFN(0x11, 0), .ir = 8}, /* PCIe RP7 */ |
| 60 | {.devfn = DEVFN(0x12, 0), .ir = 10}, /* SMBus - Host */ |
| 61 | {.devfn = DEVFN(0x13, 0), .ir = 6}, /* AHCI0 */ |
| 62 | {.devfn = DEVFN(0x14, 0), .ir = 11}, /* AHCI1 */ |
| 63 | {.devfn = DEVFN(0x15, 0), .ir = 9}, /* USB */ |
| 64 | {.devfn = DEVFN(0x16, 0), .ir = 1}, /* Virtual RP to LAN0 */ |
| 65 | {.devfn = DEVFN(0x17, 0), .ir = 2}, /* Virtual RP to LAN1 */ |
| 66 | {.devfn = DEVFN(0x18, 0), .ir = 5}, /* ME HECI1 */ |
| 67 | {.devfn = DEVFN(0x18, 1), .ir = 5}, /* ME HECI1 */ |
| 68 | {.devfn = DEVFN(0x18, 2), .ir = 5}, /* ME PTIO-IDER */ |
| 69 | {.devfn = DEVFN(0x18, 3), .ir = 5}, /* ME PTIO-KT */ |
| 70 | {.devfn = DEVFN(0x18, 4), .ir = 5}, /* ME HECI3 */ |
| 71 | {.devfn = DEVFN(0x1a, 0), .ir = 10}, /* HSUART0 */ |
| 72 | {.devfn = DEVFN(0x1a, 1), .ir = 10}, /* HSUART1 */ |
| 73 | {.devfn = DEVFN(0x1a, 2), .ir = 10}, /* HSUART2 */ |
| 74 | {.devfn = DEVFN(0x1b, 0), .ir = 12}, /* IE HECI1 */ |
| 75 | {.devfn = DEVFN(0x1b, 1), .ir = 12}, /* IE HECI1 */ |
| 76 | {.devfn = DEVFN(0x1b, 2), .ir = 12}, /* IE PTIO-IDER */ |
| 77 | {.devfn = DEVFN(0x1b, 3), .ir = 12}, /* IE PTIO-KT */ |
| 78 | {.devfn = DEVFN(0x1b, 4), .ir = 12}, /* IE HECI3 */ |
| 79 | {.devfn = DEVFN(0x1c, 0), .ir = 12}, /* SDHCI */ |
| 80 | {.devfn = DEVFN(0x1f, 0), .ir = 0}, /* LPC */ |
| 81 | {.devfn = DEVFN(0x1f, 1), .ir = 0}, /* PS2B */ |
| 82 | {.devfn = DEVFN(0x1f, 4), .ir = 0}, /* SMBus - Legacy */ |
| 83 | {.devfn = DEVFN(0x1f, 7), .ir = 0}, /* Trace Hub */ |
| 84 | }; |
| 85 | |
| 86 | /* |
| 87 | * Only 6 of the 8 root ports have swizzling, return '1' if this bdf is one of |
| 88 | * them, '0' otherwise |
| 89 | */ |
| 90 | static int is_dnv_swizzled_rp(uint16_t bdf) |
| 91 | { |
| 92 | switch (bdf) { |
| 93 | case DEVFN(10, 0): |
| 94 | case DEVFN(11, 0): |
| 95 | case DEVFN(12, 0): |
| 96 | case DEVFN(15, 0): |
| 97 | case DEVFN(16, 0): |
| 98 | case DEVFN(17, 0): |
| 99 | return 1; |
| 100 | } |
| 101 | |
| 102 | return 0; |
| 103 | } |
| 104 | |
| 105 | /* |
| 106 | * Figure out which upstream interrupt pin a downstream device gets swizzled to |
| 107 | * |
| 108 | * config - pointer to chip_info containing routing info |
| 109 | * devfn - device/function of root port to check swizzling for |
| 110 | * pin - interrupt pin 1-4 = A-D |
| 111 | * |
| 112 | * Return new pin mapping, 0 if invalid pin |
| 113 | */ |
| 114 | static int dnv_get_swizzled_pin(config_t *config, u8 devfn, u8 pin) |
| 115 | { |
| 116 | if (pin < 1 || pin > 4) |
| 117 | return 0; |
| 118 | |
| 119 | devfn >>= 3; |
| 120 | if (devfn < 13) |
| 121 | devfn -= 9; |
| 122 | else |
| 123 | devfn -= 14; |
| 124 | |
| 125 | return ((pin - 1 + devfn) % 4) + 1; |
| 126 | } |
| 127 | |
| 128 | /* |
| 129 | * Figure out which upstream interrupt pin a downstream device gets swizzled to |
| 130 | * |
| 131 | * config - pointer to chip_info containing routing info |
| 132 | * devfn - device/function of root port to check swizzling for |
| 133 | * pin - interrupt pin 1-4 = A-D |
| 134 | * |
| 135 | * Return new pin mapping, 0 if invalid pin |
| 136 | */ |
| 137 | static int dnv_get_ir(config_t *config, u8 devfn, u8 pin) |
| 138 | { |
| 139 | int i = 0; |
| 140 | int line = 0xff; |
| 141 | u16 ir = 0xffff; |
| 142 | |
| 143 | /* The only valid pin values are 1-4 for A-D */ |
| 144 | if (pin < 1 || pin > 4) { |
| 145 | printk(BIOS_WARNING, "%s: pin %d is invalid\n", __func__, pin); |
| 146 | goto dnv_get_ir_done; |
| 147 | } |
| 148 | |
| 149 | for (i = 0; i < ARRAY_SIZE(dnv_ir_lut); i++) { |
| 150 | if (dnv_ir_lut[i].devfn == devfn) |
| 151 | break; |
| 152 | } |
| 153 | |
| 154 | if (i == ARRAY_SIZE(dnv_ir_lut)) { |
| 155 | printk(BIOS_WARNING, "%s: no entry\n", __func__); |
| 156 | goto dnv_get_ir_done; |
| 157 | } |
| 158 | |
| 159 | switch (dnv_ir_lut[i].ir) { |
| 160 | case 0: |
| 161 | ir = config->ir00_routing; |
| 162 | break; |
| 163 | case 1: |
| 164 | ir = config->ir01_routing; |
| 165 | break; |
| 166 | case 2: |
| 167 | ir = config->ir02_routing; |
| 168 | break; |
| 169 | case 3: |
| 170 | ir = config->ir03_routing; |
| 171 | break; |
| 172 | case 4: |
| 173 | ir = config->ir04_routing; |
| 174 | break; |
| 175 | case 5: |
| 176 | ir = config->ir05_routing; |
| 177 | break; |
| 178 | case 6: |
| 179 | ir = config->ir06_routing; |
| 180 | break; |
| 181 | case 7: |
| 182 | ir = config->ir07_routing; |
| 183 | break; |
| 184 | case 8: |
| 185 | ir = config->ir08_routing; |
| 186 | break; |
| 187 | case 9: |
| 188 | ir = config->ir09_routing; |
| 189 | break; |
| 190 | case 10: |
| 191 | ir = config->ir10_routing; |
| 192 | break; |
| 193 | case 11: |
| 194 | ir = config->ir11_routing; |
| 195 | break; |
| 196 | case 12: |
| 197 | ir = config->ir12_routing; |
| 198 | break; |
| 199 | default: |
| 200 | printk(BIOS_ERR, "%s: invalid ir %d for entry %d\n", __func__, dnv_ir_lut[i].ir, |
| 201 | i); |
| 202 | goto dnv_get_ir_done; |
| 203 | } |
| 204 | |
| 205 | ir >>= (pin - 1) * 4; |
| 206 | ir &= 0xf; |
| 207 | switch (ir) { |
| 208 | case 0: |
| 209 | line = config->pirqa_routing; |
| 210 | break; |
| 211 | case 1: |
| 212 | line = config->pirqb_routing; |
| 213 | break; |
| 214 | case 2: |
| 215 | line = config->pirqc_routing; |
| 216 | break; |
| 217 | case 3: |
| 218 | line = config->pirqd_routing; |
| 219 | break; |
| 220 | case 4: |
| 221 | line = config->pirqe_routing; |
| 222 | break; |
| 223 | case 5: |
| 224 | line = config->pirqf_routing; |
| 225 | break; |
| 226 | case 6: |
| 227 | line = config->pirqg_routing; |
| 228 | break; |
| 229 | case 7: |
| 230 | line = config->pirqh_routing; |
| 231 | break; |
| 232 | default: |
| 233 | printk(BIOS_ERR, "%s: invalid ir pirq %d for entry %d\n", __func__, ir, i); |
| 234 | break; |
| 235 | } |
| 236 | |
| 237 | dnv_get_ir_done: |
| 238 | return line; |
| 239 | } |
| 240 | |
| 241 | /* |
| 242 | * PCI devices have the INT_LINE (0x3C) and INT_PIN (0x3D) registers which |
| 243 | * report interrupt routing information to operating systems and drivers. The |
| 244 | * INT_PIN register is generally read only and reports which interrupt pin |
| 245 | * A - D it uses. The INT_LINE register is configurable and reports which IRQ |
| 246 | * (generally the PIC IRQs 1 - 15) it will use. This needs to take interrupt |
| 247 | * pin swizzling on devices that are downstream on a PCI bridge into account. |
| 248 | */ |
| 249 | static u8 dnv_get_int_line(struct device *irq_dev) |
| 250 | { |
| 251 | config_t *config; |
| 252 | struct device *targ_dev = NULL; |
| 253 | uint16_t parent_bdf = 0; |
| 254 | int8_t original_int_pin = 0, new_int_pin = 0, swiz_int_pin = 0; |
| 255 | uint8_t int_line = 0xff; |
| 256 | |
Fabio Aiuto | d835da9 | 2022-09-30 11:25:28 +0200 | [diff] [blame] | 257 | if (!is_enabled_pci(irq_dev)) { |
Stephen Douthit | 56a74bc | 2019-08-05 12:49:08 -0400 | [diff] [blame] | 258 | printk(BIOS_ERR, "%s for non pci device?\n", __func__); |
| 259 | goto dnv_get_int_line_done; |
| 260 | } |
| 261 | |
| 262 | /* |
| 263 | * Get the INT_PIN swizzled up to the root port if necessary |
| 264 | * using the existing coreboot pci_device code |
| 265 | */ |
| 266 | original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); |
| 267 | new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev); |
| 268 | if (targ_dev == NULL || new_int_pin < 1) |
| 269 | goto dnv_get_int_line_done; |
| 270 | |
| 271 | printk(BIOS_DEBUG, "%s: irq_dev %s, targ_dev %s:\n", __func__, dev_path(irq_dev), |
| 272 | dev_path(targ_dev)); |
| 273 | printk(BIOS_DEBUG, "%s: std swizzle %s from %c to %c\n", __func__, dev_path(targ_dev), |
| 274 | '@' + original_int_pin, '@' + new_int_pin); |
| 275 | |
| 276 | /* Swizzle this device if needed */ |
| 277 | config = targ_dev->chip_info; |
| 278 | parent_bdf = targ_dev->path.pci.devfn | targ_dev->bus->secondary << 8; |
| 279 | if (is_dnv_swizzled_rp(parent_bdf) && irq_dev != targ_dev) { |
| 280 | swiz_int_pin = dnv_get_swizzled_pin(config, parent_bdf, new_int_pin); |
| 281 | printk(BIOS_DEBUG, "%s: dnv swizzle %s from %c to %c\n", __func__, |
| 282 | dev_path(targ_dev), '@' + new_int_pin, '@' + swiz_int_pin); |
| 283 | } else { |
| 284 | swiz_int_pin = new_int_pin; |
| 285 | } |
| 286 | |
| 287 | /* Look up the routing for the pin */ |
| 288 | int_line = dnv_get_ir(config, parent_bdf, swiz_int_pin); |
| 289 | |
| 290 | dnv_get_int_line_done: |
| 291 | printk(BIOS_DEBUG, "\tINT_LINE\t\t: %d\n", int_line); |
| 292 | return int_line; |
| 293 | } |
| 294 | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 295 | /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control |
| 296 | * 0x00 - 0000 = Reserved |
| 297 | * 0x01 - 0001 = Reserved |
| 298 | * 0x02 - 0010 = Reserved |
| 299 | * 0x03 - 0011 = IRQ3 |
| 300 | * 0x04 - 0100 = IRQ4 |
| 301 | * 0x05 - 0101 = IRQ5 |
| 302 | * 0x06 - 0110 = IRQ6 |
| 303 | * 0x07 - 0111 = IRQ7 |
| 304 | * 0x08 - 1000 = Reserved |
| 305 | * 0x09 - 1001 = IRQ9 |
| 306 | * 0x0A - 1010 = IRQ10 |
| 307 | * 0x0B - 1011 = IRQ11 |
| 308 | * 0x0C - 1100 = IRQ12 |
| 309 | * 0x0D - 1101 = Reserved |
| 310 | * 0x0E - 1110 = IRQ14 |
| 311 | * 0x0F - 1111 = IRQ15 |
| 312 | * PIRQ[n]_ROUT[7] - PIRQ Routing Control |
| 313 | * 0x80 - The PIRQ is not routed. |
| 314 | */ |
| 315 | |
Elyes HAOUAS | 2ec4183 | 2018-05-27 17:40:58 +0200 | [diff] [blame] | 316 | static void pch_pirq_init(struct device *dev) |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 317 | { |
Elyes HAOUAS | 2ec4183 | 2018-05-27 17:40:58 +0200 | [diff] [blame] | 318 | struct device *irq_dev; |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 319 | /* Get the chip configuration */ |
Kyösti Mälkki | 8950cfb | 2019-07-13 22:16:25 +0300 | [diff] [blame] | 320 | config_t *config = config_of(dev); |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 321 | |
| 322 | /* Initialize PIRQ Routings */ |
| 323 | write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQA_ROUT), |
| 324 | config->pirqa_routing); |
| 325 | write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQB_ROUT), |
| 326 | config->pirqb_routing); |
| 327 | write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQC_ROUT), |
| 328 | config->pirqc_routing); |
| 329 | write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQD_ROUT), |
| 330 | config->pirqd_routing); |
| 331 | |
| 332 | write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQE_ROUT), |
| 333 | config->pirqe_routing); |
| 334 | write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQF_ROUT), |
| 335 | config->pirqf_routing); |
| 336 | write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQG_ROUT), |
| 337 | config->pirqg_routing); |
| 338 | write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQH_ROUT), |
| 339 | config->pirqh_routing); |
| 340 | |
| 341 | /* Initialize device's Interrupt Routings */ |
| 342 | write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR00), |
| 343 | config->ir00_routing); |
| 344 | write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR01), |
| 345 | config->ir01_routing); |
| 346 | write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR02), |
| 347 | config->ir02_routing); |
| 348 | write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR03), |
| 349 | config->ir03_routing); |
| 350 | write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR04), |
| 351 | config->ir04_routing); |
| 352 | write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR05), |
| 353 | config->ir05_routing); |
| 354 | write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR06), |
| 355 | config->ir06_routing); |
| 356 | write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR07), |
| 357 | config->ir07_routing); |
| 358 | write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR08), |
| 359 | config->ir08_routing); |
| 360 | write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR09), |
| 361 | config->ir09_routing); |
| 362 | write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR10), |
| 363 | config->ir10_routing); |
| 364 | write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR11), |
| 365 | config->ir11_routing); |
| 366 | write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR12), |
| 367 | config->ir12_routing); |
| 368 | |
| 369 | /* Initialize device's Interrupt Polarity Control */ |
| 370 | write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC0), |
| 371 | config->ipc0); |
| 372 | write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC1), |
| 373 | config->ipc1); |
| 374 | write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC2), |
| 375 | config->ipc2); |
| 376 | write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC3), |
| 377 | config->ipc3); |
| 378 | |
| 379 | for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { |
Stephen Douthit | 56a74bc | 2019-08-05 12:49:08 -0400 | [diff] [blame] | 380 | int devfn = irq_dev->path.pci.devfn; |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 381 | u8 int_pin = 0, int_line = 0; |
| 382 | |
Fabio Aiuto | d835da9 | 2022-09-30 11:25:28 +0200 | [diff] [blame] | 383 | if (!is_enabled_pci(irq_dev)) |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 384 | continue; |
| 385 | |
| 386 | int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); |
| 387 | |
Stephen Douthit | 56a74bc | 2019-08-05 12:49:08 -0400 | [diff] [blame] | 388 | int_line = dnv_get_int_line(irq_dev); |
| 389 | printk(BIOS_DEBUG, "%s: %02x:%02x.%d pin %d int line %d\n", __func__, |
| 390 | irq_dev->bus->secondary, devfn >> 3, devfn & 0x7, int_pin, int_line); |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 391 | |
| 392 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); |
| 393 | } |
| 394 | } |
| 395 | |
Elyes HAOUAS | 2ec4183 | 2018-05-27 17:40:58 +0200 | [diff] [blame] | 396 | static void pci_p2sb_read_resources(struct device *dev) |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 397 | { |
| 398 | struct resource *res; |
| 399 | |
| 400 | /* Add MMIO resource |
| 401 | * Use 0xda as an unused index for PCR BAR. |
| 402 | */ |
| 403 | res = new_resource(dev, 0xda); |
| 404 | res->base = DEFAULT_PCR_BASE; |
| 405 | res->size = 16 * 1024 * 1024; /* 16MB PCR config space */ |
| 406 | res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | |
| 407 | IORESOURCE_ASSIGNED; |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 408 | |
| 409 | /* Add MMIO resource |
| 410 | * Use 0xdb as an unused index for IOAPIC. |
| 411 | */ |
| 412 | res = new_resource(dev, 0xdb); /* IOAPIC */ |
| 413 | res->base = IO_APIC_ADDR; |
| 414 | res->size = 0x00001000; |
| 415 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 416 | } |
| 417 | |
| 418 | static void pch_enable_serial_irqs(struct device *dev) |
| 419 | { |
| 420 | /* Set packet length and toggle silent mode bit for one frame. */ |
| 421 | pci_write_config8(dev, SERIRQ_CNTL, |
| 422 | (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 423 | #if !CONFIG(SERIRQ_CONTINUOUS_MODE) |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 424 | pci_write_config8(dev, SERIRQ_CNTL, |
| 425 | (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); |
| 426 | #endif |
| 427 | } |
| 428 | |
| 429 | static void lpc_init(struct device *dev) |
| 430 | { |
Elyes HAOUAS | e98dbf3 | 2021-01-16 17:33:21 +0100 | [diff] [blame] | 431 | printk(BIOS_DEBUG, "pch: %s\n", __func__); |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 432 | |
| 433 | /* Get the base address */ |
| 434 | |
| 435 | /* Set the value for PCI command register. */ |
| 436 | pci_write_config16(dev, PCI_COMMAND, |
| 437 | PCI_COMMAND_SPECIAL | PCI_COMMAND_MASTER | |
| 438 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 439 | |
| 440 | /* Serial IRQ initialization. */ |
| 441 | pch_enable_serial_irqs(dev); |
| 442 | |
| 443 | /* IO APIC initialization. */ |
| 444 | pch_enable_ioapic(dev); |
| 445 | |
| 446 | /* Setup the PIRQ. */ |
| 447 | pch_pirq_init(dev); |
| 448 | } |
| 449 | |
Elyes HAOUAS | 2ec4183 | 2018-05-27 17:40:58 +0200 | [diff] [blame] | 450 | static void pch_lpc_add_mmio_resources(struct device *dev) { /* TODO */ } |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 451 | |
Elyes HAOUAS | 2ec4183 | 2018-05-27 17:40:58 +0200 | [diff] [blame] | 452 | static void pch_lpc_add_io_resources(struct device *dev) |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 453 | { |
| 454 | struct resource *res; |
| 455 | u8 io_index = 0; |
| 456 | |
| 457 | /* Add an extra subtractive resource for both memory and I/O. */ |
| 458 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
| 459 | res->base = 0; |
| 460 | res->size = 0x1000; |
| 461 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 462 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 463 | |
| 464 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
| 465 | res->base = 0xff000000; |
| 466 | res->size = 0x01000000; /* 16 MB for flash */ |
| 467 | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | |
| 468 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 469 | } |
| 470 | |
Elyes HAOUAS | 2ec4183 | 2018-05-27 17:40:58 +0200 | [diff] [blame] | 471 | static void lpc_read_resources(struct device *dev) |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 472 | { |
| 473 | /* Get the normal PCI resources of this device. */ |
| 474 | pci_dev_read_resources(dev); |
| 475 | |
| 476 | /* Add non-standard MMIO resources. */ |
| 477 | pch_lpc_add_mmio_resources(dev); |
| 478 | |
| 479 | /* Add IO resources. */ |
| 480 | pch_lpc_add_io_resources(dev); |
| 481 | |
| 482 | /* Add MMIO resource for IOAPIC. */ |
| 483 | pci_p2sb_read_resources(dev); |
| 484 | } |
| 485 | |
| 486 | static void pch_decode_init(struct device *dev) { /* TODO */ } |
| 487 | |
Elyes HAOUAS | 2ec4183 | 2018-05-27 17:40:58 +0200 | [diff] [blame] | 488 | static void lpc_enable_resources(struct device *dev) |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 489 | { |
| 490 | pch_decode_init(dev); |
| 491 | pci_dev_enable_resources(dev); |
| 492 | } |
| 493 | |
| 494 | /* Set bit in Function Disable register to hide this device */ |
| 495 | static void pch_hide_devfn(uint32_t devfn) { /* TODO */ } |
| 496 | |
Elyes HAOUAS | 2ec4183 | 2018-05-27 17:40:58 +0200 | [diff] [blame] | 497 | void southcluster_enable_dev(struct device *dev) |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 498 | { |
Elyes HAOUAS | 924fe94 | 2020-04-29 09:48:09 +0200 | [diff] [blame] | 499 | u16 reg16; |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 500 | |
| 501 | if (!dev->enabled) { |
| 502 | printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); |
| 503 | |
| 504 | /* Ensure memory, io, and bus master are all disabled */ |
Elyes HAOUAS | 924fe94 | 2020-04-29 09:48:09 +0200 | [diff] [blame] | 505 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 506 | reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 507 | PCI_COMMAND_IO); |
Elyes HAOUAS | 924fe94 | 2020-04-29 09:48:09 +0200 | [diff] [blame] | 508 | pci_write_config16(dev, PCI_COMMAND, reg16); |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 509 | |
| 510 | /* Hide this device if possible */ |
| 511 | pch_hide_devfn(dev->path.pci.devfn); |
| 512 | } else { |
| 513 | /* Enable SERR */ |
Elyes HAOUAS | 924fe94 | 2020-04-29 09:48:09 +0200 | [diff] [blame] | 514 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 515 | } |
| 516 | } |
| 517 | |
| 518 | static struct device_operations device_ops = { |
| 519 | .read_resources = lpc_read_resources, |
| 520 | .set_resources = pci_dev_set_resources, |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 521 | #if CONFIG(HAVE_ACPI_TABLES) |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 522 | .write_acpi_tables = southcluster_write_acpi_tables, |
| 523 | #endif |
| 524 | .enable_resources = lpc_enable_resources, |
| 525 | .init = lpc_init, |
| 526 | .enable = southcluster_enable_dev, |
Nico Huber | 51b75ae | 2019-03-14 16:02:05 +0100 | [diff] [blame] | 527 | .scan_bus = scan_static_bus, |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 528 | .ops_pci = &soc_pci_ops, |
| 529 | }; |
| 530 | |
| 531 | static const struct pci_driver lpc_driver __pci_driver = { |
| 532 | .ops = &device_ops, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 533 | .vendor = PCI_VID_INTEL, |
| 534 | .device = PCI_DID_INTEL_DNV_LPC, |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 535 | }; |
| 536 | |
| 537 | static void finalize_chipset(void *unused) |
| 538 | { |
Kyösti Mälkki | b658548 | 2020-06-01 15:11:14 +0300 | [diff] [blame] | 539 | apm_control(APM_CNT_FINALIZE); |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 540 | } |
| 541 | |
| 542 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); |
| 543 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL); |