Subrata Banik | 01ae11b | 2017-03-04 23:32:41 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 4 | * Copyright (C) 2017-2018 Intel Corporation. |
Subrata Banik | 01ae11b | 2017-03-04 23:32:41 +0530 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <arch/io.h> |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 17 | #include <cbmem.h> |
| 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <device/pci_ids.h> |
Subrata Banik | 01ae11b | 2017-03-04 23:32:41 +0530 | [diff] [blame] | 21 | #include <intelblocks/systemagent.h> |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 22 | #include <soc/iomap.h> |
Subrata Banik | 01ae11b | 2017-03-04 23:32:41 +0530 | [diff] [blame] | 23 | #include <soc/pci_devs.h> |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 24 | #include <soc/systemagent.h> |
| 25 | #include "systemagent_def.h" |
Subrata Banik | 01ae11b | 2017-03-04 23:32:41 +0530 | [diff] [blame] | 26 | |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 27 | /* SoC override function */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 28 | __weak void soc_systemagent_init(struct device *dev) |
Subrata Banik | 01ae11b | 2017-03-04 23:32:41 +0530 | [diff] [blame] | 29 | { |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 30 | /* no-op */ |
Subrata Banik | 01ae11b | 2017-03-04 23:32:41 +0530 | [diff] [blame] | 31 | } |
| 32 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 33 | __weak void soc_add_fixed_mmio_resources(struct device *dev, |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 34 | int *resource_cnt) |
| 35 | { |
| 36 | /* no-op */ |
| 37 | } |
| 38 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 39 | __weak int soc_get_uncore_prmmr_base_and_mask(uint64_t *base, |
Pratik Prajapati | 82cdfa7 | 2017-08-28 14:48:55 -0700 | [diff] [blame] | 40 | uint64_t *mask) |
| 41 | { |
| 42 | /* return failure for this dummy API */ |
| 43 | return -1; |
| 44 | } |
| 45 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 46 | __weak size_t soc_reserved_mmio_size(void) |
Subrata Banik | 73b8503 | 2017-09-17 21:16:22 +0530 | [diff] [blame] | 47 | { |
| 48 | return 0; |
| 49 | } |
| 50 | |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 51 | /* |
| 52 | * Add all known fixed MMIO ranges that hang off the host bridge/memory |
| 53 | * controller device. |
| 54 | */ |
| 55 | void sa_add_fixed_mmio_resources(struct device *dev, int *resource_cnt, |
| 56 | const struct sa_mmio_descriptor *sa_fixed_resources, size_t count) |
| 57 | { |
| 58 | int i; |
| 59 | int index = *resource_cnt; |
| 60 | |
| 61 | for (i = 0; i < count; i++) { |
| 62 | uintptr_t base; |
| 63 | size_t size; |
| 64 | |
| 65 | size = sa_fixed_resources[i].size; |
| 66 | base = sa_fixed_resources[i].base; |
| 67 | |
| 68 | mmio_resource(dev, index++, base / KiB, size / KiB); |
| 69 | } |
| 70 | |
| 71 | *resource_cnt = index; |
| 72 | } |
| 73 | |
| 74 | /* |
| 75 | * DRAM memory mapped register |
| 76 | * |
| 77 | * TOUUD: This 64 bit register defines the Top of Upper Usable DRAM |
| 78 | * TOLUD: This 32 bit register defines the Top of Low Usable DRAM |
| 79 | * BGSM: This register contains the base address of stolen DRAM memory for GTT |
| 80 | * TSEG: This register contains the base address of TSEG DRAM memory |
| 81 | */ |
| 82 | static const struct sa_mem_map_descriptor sa_memory_map[MAX_MAP_ENTRIES] = { |
| 83 | { TOUUD, true, "TOUUD" }, |
| 84 | { TOLUD, false, "TOLUD" }, |
| 85 | { BGSM, false, "BGSM" }, |
| 86 | { TSEG, false, "TSEG" }, |
| 87 | }; |
| 88 | |
| 89 | /* Read DRAM memory map register value through PCI configuration space */ |
Elyes HAOUAS | 4a13126 | 2018-09-16 17:35:48 +0200 | [diff] [blame] | 90 | static void sa_read_map_entry(struct device *dev, |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 91 | const struct sa_mem_map_descriptor *entry, uint64_t *result) |
| 92 | { |
| 93 | uint64_t value = 0; |
| 94 | |
| 95 | if (entry->is_64_bit) { |
| 96 | value = pci_read_config32(dev, entry->reg + 4); |
| 97 | value <<= 32; |
| 98 | } |
| 99 | |
| 100 | value |= pci_read_config32(dev, entry->reg); |
| 101 | /* All registers are on a 1MiB granularity. */ |
| 102 | value = ALIGN_DOWN(value, 1 * MiB); |
| 103 | |
| 104 | *result = value; |
| 105 | } |
| 106 | |
| 107 | static void sa_get_mem_map(struct device *dev, uint64_t *values) |
| 108 | { |
| 109 | int i; |
| 110 | for (i = 0; i < MAX_MAP_ENTRIES; i++) |
| 111 | sa_read_map_entry(dev, &sa_memory_map[i], &values[i]); |
| 112 | } |
| 113 | |
| 114 | /* |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 115 | * These are the host memory ranges that should be added: |
| 116 | * - 0 -> 0xa0000: cacheable |
| 117 | * - 0xc0000 -> top_of_ram : cacheable |
| 118 | * - top_of_ram -> TSEG - DPR: uncacheable |
| 119 | * - TESG - DPR -> BGSM: cacheable with standard MTRRs and reserved |
| 120 | * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved |
| 121 | * - 4GiB -> TOUUD: cacheable |
| 122 | * |
| 123 | * The default SMRAM space is reserved so that the range doesn't |
| 124 | * have to be saved during S3 Resume. Once marked reserved the OS |
| 125 | * cannot use the memory. This is a bit of an odd place to reserve |
| 126 | * the region, but the CPU devices don't have dev_ops->read_resources() |
| 127 | * called on them. |
| 128 | * |
| 129 | * The range 0xa0000 -> 0xc0000 does not have any resources |
| 130 | * associated with it to handle legacy VGA memory. If this range |
| 131 | * is not omitted the mtrr code will setup the area as cacheable |
| 132 | * causing VGA access to not work. |
| 133 | * |
| 134 | * The TSEG region is mapped as cacheable so that one can perform |
| 135 | * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes |
| 136 | * precedence over the existing MTRRs covering this region. |
| 137 | * |
| 138 | * It should be noted that cacheable entry types need to be added in |
| 139 | * order. The reason is that the current MTRR code assumes this and |
| 140 | * falls over itself if it isn't. |
| 141 | * |
| 142 | * The resource index starts low and should not meet or exceed |
| 143 | * PCI_BASE_ADDRESS_0. |
| 144 | */ |
| 145 | static void sa_add_dram_resources(struct device *dev, int *resource_count) |
| 146 | { |
| 147 | uintptr_t base_k, touud_k; |
| 148 | size_t dpr_size = 0, size_k; |
Subrata Banik | 73b8503 | 2017-09-17 21:16:22 +0530 | [diff] [blame] | 149 | size_t reserved_mmio_size; |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 150 | uint64_t sa_map_values[MAX_MAP_ENTRIES]; |
| 151 | uintptr_t top_of_ram; |
| 152 | int index = *resource_count; |
| 153 | |
| 154 | if (IS_ENABLED(CONFIG_SA_ENABLE_DPR)) |
Subrata Banik | bd6ac22 | 2017-08-21 16:42:15 +0530 | [diff] [blame] | 155 | dpr_size = sa_get_dpr_size(); |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 156 | |
Elyes HAOUAS | 88607a4 | 2018-10-05 10:36:45 +0200 | [diff] [blame] | 157 | /* Get SoC reserve memory size as per user selection */ |
| 158 | reserved_mmio_size = soc_reserved_mmio_size(); |
Subrata Banik | 73b8503 | 2017-09-17 21:16:22 +0530 | [diff] [blame] | 159 | |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 160 | top_of_ram = (uintptr_t)cbmem_top(); |
| 161 | |
| 162 | /* 0 - > 0xa0000 */ |
| 163 | base_k = 0; |
| 164 | size_k = (0xa0000 / KiB) - base_k; |
| 165 | ram_resource(dev, index++, base_k, size_k); |
| 166 | |
| 167 | /* 0xc0000 -> top_of_ram */ |
| 168 | base_k = 0xc0000 / KiB; |
| 169 | size_k = (top_of_ram / KiB) - base_k; |
| 170 | ram_resource(dev, index++, base_k, size_k); |
| 171 | |
| 172 | sa_get_mem_map(dev, &sa_map_values[0]); |
| 173 | |
Subrata Banik | 73b8503 | 2017-09-17 21:16:22 +0530 | [diff] [blame] | 174 | /* top_of_ram -> TSEG - DPR - Intel Reserve Memory Size*/ |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 175 | base_k = top_of_ram; |
Subrata Banik | 73b8503 | 2017-09-17 21:16:22 +0530 | [diff] [blame] | 176 | size_k = sa_map_values[SA_TSEG_REG] - dpr_size - base_k |
| 177 | - reserved_mmio_size; |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 178 | mmio_resource(dev, index++, base_k / KiB, size_k / KiB); |
| 179 | |
Subrata Banik | 73b8503 | 2017-09-17 21:16:22 +0530 | [diff] [blame] | 180 | /* TSEG - DPR - Intel Reserve Memory Size -> BGSM */ |
| 181 | base_k = sa_map_values[SA_TSEG_REG] - dpr_size - reserved_mmio_size; |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 182 | size_k = sa_map_values[SA_BGSM_REG] - base_k; |
| 183 | reserved_ram_resource(dev, index++, base_k / KiB, size_k / KiB); |
| 184 | |
| 185 | /* BGSM -> TOLUD */ |
| 186 | base_k = sa_map_values[SA_BGSM_REG]; |
| 187 | size_k = sa_map_values[SA_TOLUD_REG] - base_k; |
| 188 | mmio_resource(dev, index++, base_k / KiB, size_k / KiB); |
| 189 | |
| 190 | /* 4GiB -> TOUUD */ |
| 191 | base_k = 4 * (GiB / KiB); /* 4GiB */ |
| 192 | touud_k = sa_map_values[SA_TOUUD_REG] / KiB; |
| 193 | size_k = touud_k - base_k; |
| 194 | if (touud_k > base_k) |
| 195 | ram_resource(dev, index++, base_k, size_k); |
| 196 | |
| 197 | /* |
| 198 | * Reserve everything between A segment and 1MB: |
| 199 | * |
| 200 | * 0xa0000 - 0xbffff: legacy VGA |
| 201 | * 0xc0000 - 0xfffff: RAM |
| 202 | */ |
| 203 | mmio_resource(dev, index++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB); |
| 204 | reserved_ram_resource(dev, index++, 0xc0000 / KiB, |
| 205 | (1*MiB - 0xc0000) / KiB); |
| 206 | |
| 207 | *resource_count = index; |
| 208 | } |
| 209 | |
| 210 | static bool is_imr_enabled(uint32_t imr_base_reg) |
| 211 | { |
| 212 | return !!(imr_base_reg & (1 << 31)); |
| 213 | } |
| 214 | |
Elyes HAOUAS | 4a13126 | 2018-09-16 17:35:48 +0200 | [diff] [blame] | 215 | static void imr_resource(struct device *dev, int idx, uint32_t base, |
| 216 | uint32_t mask) |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 217 | { |
| 218 | uint32_t base_k, size_k; |
| 219 | /* Bits 28:0 encode the base address bits 38:10, hence the KiB unit. */ |
| 220 | base_k = (base & 0x0fffffff); |
| 221 | /* Bits 28:0 encode the AND mask used for comparison, in KiB. */ |
| 222 | size_k = ((~mask & 0x0fffffff) + 1); |
| 223 | /* |
| 224 | * IMRs sit in lower DRAM. Mark them cacheable, otherwise we run |
| 225 | * out of MTRRs. Memory reserved by IMRs is not usable for host |
| 226 | * so mark it reserved. |
| 227 | */ |
| 228 | reserved_ram_resource(dev, idx, base_k, size_k); |
| 229 | } |
| 230 | |
| 231 | /* |
| 232 | * Add IMR ranges that hang off the host bridge/memory |
| 233 | * controller device in case CONFIG_SA_ENABLE_IMR is selected by SoC. |
| 234 | */ |
| 235 | static void sa_add_imr_resources(struct device *dev, int *resource_cnt) |
| 236 | { |
| 237 | size_t i, imr_offset; |
| 238 | uint32_t base, mask; |
| 239 | int index = *resource_cnt; |
| 240 | |
| 241 | for (i = 0; i < MCH_NUM_IMRS; i++) { |
| 242 | imr_offset = i * MCH_IMR_PITCH; |
| 243 | base = MCHBAR32(imr_offset + MCH_IMR0_BASE); |
| 244 | mask = MCHBAR32(imr_offset + MCH_IMR0_MASK); |
| 245 | |
| 246 | if (is_imr_enabled(base)) |
| 247 | imr_resource(dev, index++, base, mask); |
| 248 | } |
| 249 | |
| 250 | *resource_cnt = index; |
| 251 | } |
| 252 | |
| 253 | static void systemagent_read_resources(struct device *dev) |
| 254 | { |
| 255 | int index = 0; |
| 256 | |
| 257 | /* Read standard PCI resources. */ |
| 258 | pci_dev_read_resources(dev); |
| 259 | |
| 260 | /* Add all fixed MMIO resources. */ |
| 261 | soc_add_fixed_mmio_resources(dev, &index); |
| 262 | /* Calculate and add DRAM resources. */ |
| 263 | sa_add_dram_resources(dev, &index); |
| 264 | if (IS_ENABLED(CONFIG_SA_ENABLE_IMR)) |
| 265 | /* Add the isolated memory ranges (IMRs). */ |
| 266 | sa_add_imr_resources(dev, &index); |
| 267 | } |
| 268 | |
| 269 | void enable_power_aware_intr(void) |
| 270 | { |
| 271 | uint8_t pair; |
| 272 | |
| 273 | /* Enable Power Aware Interrupt Routing */ |
| 274 | pair = MCHBAR8(MCH_PAIR); |
| 275 | pair &= ~0x7; /* Clear 2:0 */ |
| 276 | pair |= 0x4; /* Fixed Priority */ |
| 277 | MCHBAR8(MCH_PAIR) = pair; |
| 278 | } |
| 279 | |
| 280 | static struct device_operations systemagent_ops = { |
Elyes HAOUAS | 1d19127 | 2018-11-27 12:23:48 +0100 | [diff] [blame] | 281 | .read_resources = systemagent_read_resources, |
| 282 | .set_resources = pci_dev_set_resources, |
| 283 | .enable_resources = pci_dev_enable_resources, |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 284 | .init = soc_systemagent_init, |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame] | 285 | .ops_pci = &pci_dev_ops_pci, |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 286 | }; |
| 287 | |
| 288 | static const unsigned short systemagent_ids[] = { |
| 289 | PCI_DEVICE_ID_INTEL_GLK_NB, |
| 290 | PCI_DEVICE_ID_INTEL_APL_NB, |
Lijian Zhao | bbedef9 | 2017-07-29 16:38:38 -0700 | [diff] [blame] | 291 | PCI_DEVICE_ID_INTEL_CNL_ID_U, |
| 292 | PCI_DEVICE_ID_INTEL_CNL_ID_Y, |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 293 | PCI_DEVICE_ID_INTEL_SKL_ID_U, |
| 294 | PCI_DEVICE_ID_INTEL_SKL_ID_Y, |
| 295 | PCI_DEVICE_ID_INTEL_SKL_ID_ULX, |
| 296 | PCI_DEVICE_ID_INTEL_SKL_ID_H, |
Krzysztof Sywula | bb0cf01 | 2018-08-15 09:26:35 -0700 | [diff] [blame] | 297 | PCI_DEVICE_ID_INTEL_WHL_ID_Wx2, |
| 298 | PCI_DEVICE_ID_INTEL_WHL_ID_Wx4, |
Gaggery Tsai | e415a4c | 2018-03-21 22:36:18 +0800 | [diff] [blame] | 299 | PCI_DEVICE_ID_INTEL_KBL_ID_S, |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 300 | PCI_DEVICE_ID_INTEL_SKL_ID_H_EM, |
| 301 | PCI_DEVICE_ID_INTEL_KBL_ID_U, |
| 302 | PCI_DEVICE_ID_INTEL_KBL_ID_Y, |
| 303 | PCI_DEVICE_ID_INTEL_KBL_ID_H, |
| 304 | PCI_DEVICE_ID_INTEL_KBL_U_R, |
V Sowmya | acc2a48 | 2018-01-23 15:27:23 +0530 | [diff] [blame] | 305 | PCI_DEVICE_ID_INTEL_KBL_ID_DT, |
Maulik | fc19ab5 | 2018-01-05 22:40:35 +0530 | [diff] [blame] | 306 | PCI_DEVICE_ID_INTEL_CFL_ID_U, |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 307 | PCI_DEVICE_ID_INTEL_CFL_ID_H, |
| 308 | PCI_DEVICE_ID_INTEL_CFL_ID_S, |
Aamir Bohra | 9eac039 | 2018-06-30 12:07:04 +0530 | [diff] [blame] | 309 | PCI_DEVICE_ID_INTEL_ICL_ID_U, |
| 310 | PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2, |
| 311 | PCI_DEVICE_ID_INTEL_ICL_ID_Y, |
| 312 | PCI_DEVICE_ID_INTEL_ICL_ID_Y_2, |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 313 | 0 |
| 314 | }; |
| 315 | |
| 316 | static const struct pci_driver systemagent_driver __pci_driver = { |
| 317 | .ops = &systemagent_ops, |
| 318 | .vendor = PCI_VENDOR_ID_INTEL, |
| 319 | .devices = systemagent_ids |
| 320 | }; |