Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <arch/io.h> |
| 22 | #include <console/console.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include "pch.h" |
| 27 | |
| 28 | typedef struct southbridge_intel_bd82x6x_config config_t; |
| 29 | |
| 30 | static void sata_init(struct device *dev) |
| 31 | { |
| 32 | u32 reg32; |
| 33 | u16 reg16; |
| 34 | /* Get the chip configuration */ |
| 35 | config_t *config = dev->chip_info; |
| 36 | |
| 37 | printk(BIOS_DEBUG, "pch_sata: initializing...\n"); |
| 38 | |
| 39 | if (config == NULL) { |
| 40 | printk(BIOS_ERR, "pch_sata: error: device not in devicetree.cb!\n"); |
| 41 | return; |
| 42 | } |
| 43 | |
| 44 | /* SATA configuration */ |
| 45 | |
| 46 | /* Enable BARs */ |
| 47 | pci_write_config16(dev, PCI_COMMAND, 0x0007); |
| 48 | |
| 49 | if (config->ide_legacy_combined) { |
| 50 | printk(BIOS_DEBUG, "SATA controller in combined mode.\n"); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 51 | |
| 52 | /* No AHCI: clear AHCI base */ |
| 53 | pci_write_config32(dev, 0x24, 0x00000000); |
| 54 | /* And without AHCI BAR no memory decoding */ |
| 55 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 56 | reg16 &= ~PCI_COMMAND_MEMORY; |
| 57 | pci_write_config16(dev, PCI_COMMAND, reg16); |
| 58 | |
| 59 | pci_write_config8(dev, 0x09, 0x80); |
| 60 | |
| 61 | /* Set timings */ |
| 62 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | |
| 63 | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); |
| 64 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | |
| 65 | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | |
| 66 | IDE_PPE0 | IDE_IE0 | IDE_TIME0); |
| 67 | |
| 68 | /* Sync DMA */ |
| 69 | pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); |
| 70 | pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); |
| 71 | |
| 72 | /* Set IDE I/O Configuration */ |
| 73 | reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; |
| 74 | pci_write_config32(dev, IDE_CONFIG, reg32); |
| 75 | |
| 76 | /* Port enable */ |
| 77 | reg16 = pci_read_config16(dev, 0x92); |
| 78 | reg16 &= ~0x3f; |
| 79 | reg16 |= config->sata_port_map; |
| 80 | pci_write_config16(dev, 0x92, reg16); |
| 81 | |
| 82 | /* SATA Initialization register */ |
| 83 | pci_write_config32(dev, 0x94, |
| 84 | ((config->sata_port_map ^ 0x3f) << 24) | 0x183); |
| 85 | } else if(config->sata_ahci) { |
| 86 | u32 abar; |
| 87 | |
| 88 | printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 89 | |
| 90 | /* Set Interrupt Line */ |
| 91 | /* Interrupt Pin is set by D31IP.PIP */ |
| 92 | pci_write_config8(dev, INTR_LN, 0x0a); |
| 93 | |
| 94 | /* Set timings */ |
| 95 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | |
| 96 | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | |
| 97 | IDE_PPE0 | IDE_IE0 | IDE_TIME0); |
| 98 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | |
| 99 | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); |
| 100 | |
| 101 | /* Sync DMA */ |
| 102 | pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); |
| 103 | pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); |
| 104 | |
| 105 | /* Set IDE I/O Configuration */ |
| 106 | reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; |
| 107 | pci_write_config32(dev, IDE_CONFIG, reg32); |
| 108 | |
| 109 | /* for AHCI, Port Enable is managed in memory mapped space */ |
| 110 | reg16 = pci_read_config16(dev, 0x92); |
| 111 | reg16 &= ~0x3f; /* 6 ports SKU + ORM */ |
| 112 | reg16 |= 0x8000 | config->sata_port_map; |
| 113 | pci_write_config16(dev, 0x92, reg16); |
| 114 | |
| 115 | /* SATA Initialization register */ |
| 116 | pci_write_config32(dev, 0x94, |
| 117 | ((config->sata_port_map ^ 0x3f) << 24) | 0x183); |
| 118 | |
| 119 | /* Initialize AHCI memory-mapped space */ |
| 120 | abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); |
| 121 | printk(BIOS_DEBUG, "ABAR: %08X\n", abar); |
| 122 | /* CAP (HBA Capabilities) : enable power management */ |
| 123 | reg32 = read32(abar + 0x00); |
| 124 | reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS |
| 125 | reg32 &= ~0x00020060; // clear SXS+EMS+PMS |
| 126 | write32(abar + 0x00, reg32); |
| 127 | /* PI (Ports implemented) */ |
| 128 | write32(abar + 0x0c, config->sata_port_map); |
| 129 | (void) read32(abar + 0x0c); /* Read back 1 */ |
| 130 | (void) read32(abar + 0x0c); /* Read back 2 */ |
| 131 | /* CAP2 (HBA Capabilities Extended)*/ |
| 132 | reg32 = read32(abar + 0x24); |
| 133 | reg32 &= ~0x00000002; |
| 134 | write32(abar + 0x24, reg32); |
| 135 | /* VSP (Vendor Specific Register */ |
| 136 | reg32 = read32(abar + 0xa0); |
| 137 | reg32 &= ~0x00000005; |
| 138 | write32(abar + 0xa0, reg32); |
| 139 | } else { |
| 140 | printk(BIOS_DEBUG, "SATA controller in plain mode.\n"); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 141 | |
| 142 | /* No AHCI: clear AHCI base */ |
| 143 | pci_write_config32(dev, 0x24, 0x00000000); |
| 144 | |
| 145 | /* And without AHCI BAR no memory decoding */ |
| 146 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 147 | reg16 &= ~PCI_COMMAND_MEMORY; |
| 148 | pci_write_config16(dev, PCI_COMMAND, reg16); |
| 149 | |
| 150 | /* Native mode capable on both primary and secondary (0xa) |
| 151 | * or'ed with enabled (0x50) = 0xf |
| 152 | */ |
| 153 | pci_write_config8(dev, 0x09, 0x8f); |
| 154 | |
| 155 | /* Set Interrupt Line */ |
| 156 | /* Interrupt Pin is set by D31IP.PIP */ |
| 157 | pci_write_config8(dev, INTR_LN, 0xff); |
| 158 | |
| 159 | /* Set timings */ |
| 160 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | |
| 161 | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | |
| 162 | IDE_PPE0 | IDE_IE0 | IDE_TIME0); |
| 163 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | |
| 164 | IDE_SITRE | IDE_ISP_3_CLOCKS | |
| 165 | IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); |
| 166 | |
| 167 | /* Sync DMA */ |
| 168 | pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); |
| 169 | pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); |
| 170 | |
| 171 | /* Set IDE I/O Configuration */ |
| 172 | reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; |
| 173 | pci_write_config32(dev, IDE_CONFIG, reg32); |
| 174 | |
| 175 | /* Port enable */ |
| 176 | reg16 = pci_read_config16(dev, 0x92); |
| 177 | reg16 &= ~0x3f; |
| 178 | reg16 |= config->sata_port_map; |
| 179 | pci_write_config16(dev, 0x92, reg16); |
| 180 | |
| 181 | /* SATA Initialization register */ |
| 182 | pci_write_config32(dev, 0x94, |
| 183 | ((config->sata_port_map ^ 0x3f) << 24) | 0x183); |
| 184 | } |
| 185 | } |
| 186 | |
Stefan Reinauer | 816d081 | 2012-04-30 16:42:07 -0700 | [diff] [blame] | 187 | static void sata_enable(device_t dev) |
| 188 | { |
| 189 | /* Get the chip configuration */ |
| 190 | config_t *config = dev->chip_info; |
| 191 | u16 map = 0; |
| 192 | |
| 193 | if (!config) |
| 194 | return; |
| 195 | |
| 196 | /* |
| 197 | * Set SATA controller mode early so the resource allocator can |
| 198 | * properly assign IO/Memory resources for the controller. |
| 199 | */ |
| 200 | if (config->sata_ahci) |
| 201 | map = 0x0060; |
| 202 | |
| 203 | map |= (config->sata_port_map ^ 0x3f) << 8; |
| 204 | |
| 205 | pci_write_config16(dev, 0x90, map); |
| 206 | } |
| 207 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 208 | static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 209 | { |
| 210 | if (!vendor || !device) { |
| 211 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 212 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 213 | } else { |
| 214 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 215 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 216 | } |
| 217 | } |
| 218 | |
| 219 | static struct pci_operations sata_pci_ops = { |
| 220 | .set_subsystem = sata_set_subsystem, |
| 221 | }; |
| 222 | |
| 223 | static struct device_operations sata_ops = { |
| 224 | .read_resources = pci_dev_read_resources, |
| 225 | .set_resources = pci_dev_set_resources, |
| 226 | .enable_resources = pci_dev_enable_resources, |
| 227 | .init = sata_init, |
Stefan Reinauer | 816d081 | 2012-04-30 16:42:07 -0700 | [diff] [blame] | 228 | .enable = sata_enable, |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 229 | .scan_bus = 0, |
| 230 | .ops_pci = &sata_pci_ops, |
| 231 | }; |
| 232 | |
Stefan Reinauer | 9a380ab | 2012-06-22 13:16:11 -0700 | [diff] [blame] | 233 | static const unsigned short pci_device_ids[] = { 0x1c00, 0x1c01, 0x1c02, 0x1c03, |
| 234 | 0x1e00, 0x1e01, 0x1e02, 0x1e03, |
| 235 | 0 }; |
| 236 | |
| 237 | static const struct pci_driver pch_sata __pci_driver = { |
| 238 | .ops = &sata_ops, |
| 239 | .vendor = PCI_VENDOR_ID_INTEL, |
| 240 | .devices = pci_device_ids, |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 241 | }; |
| 242 | |