Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 5 | * Copyright (C) 2015 Intel Corporation. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
| 18 | #include <bootstate.h> |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 19 | #include <chip.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 20 | #include <console/console.h> |
| 21 | #include <console/post_codes.h> |
| 22 | #include <cpu/x86/smm.h> |
| 23 | #include <reg_script.h> |
| 24 | #include <spi-generic.h> |
| 25 | #include <stdlib.h> |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 26 | #include <soc/lpc.h> |
Dhaval Sharma | 9dca83c | 2016-01-18 17:28:20 +0530 | [diff] [blame] | 27 | #include <soc/me.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 28 | #include <soc/pci_devs.h> |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 29 | #include <soc/pcr.h> |
| 30 | #include <soc/pm.h> |
Barnali Sarkar | 0dddcd7 | 2016-08-02 17:49:56 +0530 | [diff] [blame] | 31 | #include <soc/smbus.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 32 | #include <soc/spi.h> |
| 33 | #include <soc/systemagent.h> |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 34 | #include <device/pci.h> |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 35 | #include <chip.h> |
| 36 | |
| 37 | #define PCH_P2SB_EPMASK0 0xB0 |
| 38 | #define PCH_P2SB_EPMASK(mask_number) PCH_P2SB_EPMASK0 + (mask_number * 4) |
| 39 | |
| 40 | #define PCH_P2SB_E0 0xE0 |
Archana Patni | 6c1bf27 | 2015-12-18 23:38:21 +0530 | [diff] [blame] | 41 | #define PCH_PWRM_ACPI_TMR_CTL 0xFC |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 42 | |
| 43 | static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask) |
| 44 | { |
| 45 | uint32_t reg32; |
| 46 | |
| 47 | reg32 = pci_read_config32(dev, PCH_P2SB_EPMASK(epmask_id)); |
| 48 | pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask); |
| 49 | } |
| 50 | |
| 51 | static void pch_disable_heci(void) |
| 52 | { |
| 53 | device_t dev; |
| 54 | u8 reg8; |
| 55 | uint32_t mask; |
| 56 | |
| 57 | dev = PCH_DEV_P2SB; |
| 58 | |
| 59 | /* |
| 60 | * if p2sb device 1f.1 is not present or hidden in devicetree |
| 61 | * p2sb device becomes NULL |
| 62 | */ |
| 63 | if (!dev) |
| 64 | return; |
| 65 | |
| 66 | /* unhide p2sb device */ |
| 67 | pci_write_config8(dev, PCH_P2SB_E0 + 1, 0); |
| 68 | |
| 69 | /* disable heci */ |
| 70 | pcr_andthenor32(PID_PSF1, PSF_BASE_ADDRESS + PCH_PCR_PSFX_T0_SHDW_PCIEN, |
| 71 | ~0, PCH_PCR_PSFX_T0_SHDW_PCIEN_FUNDIS); |
| 72 | |
| 73 | /* Remove the host accessing right to PSF register range. */ |
| 74 | /* Set p2sb PCI offset EPMASK5 C4h [29, 28, 27, 26] to [1, 1, 1, 1] */ |
| 75 | mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26); |
| 76 | pch_configure_endpoints(dev, 5, mask); |
| 77 | |
| 78 | /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */ |
| 79 | reg8 = pci_read_config8(dev, PCH_P2SB_E0 + 2); |
| 80 | pci_write_config8(dev, PCH_P2SB_E0 + 2, reg8 | (1 << 1)); |
| 81 | |
| 82 | /* hide p2sb device */ |
| 83 | pci_write_config8(dev, PCH_P2SB_E0 + 1, 1); |
| 84 | } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 85 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 86 | static void pch_finalize_script(void) |
| 87 | { |
| 88 | device_t dev; |
| 89 | uint32_t reg32, hsfs; |
| 90 | void *spibar = get_spi_bar(); |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 91 | u16 tcobase; |
| 92 | u16 tcocnt; |
| 93 | uint8_t *pmcbase; |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 94 | config_t *config; |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 95 | u32 pmsyncreg; |
Archana Patni | 6c1bf27 | 2015-12-18 23:38:21 +0530 | [diff] [blame] | 96 | u8 reg8; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 97 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 98 | /* Set SPI opcode menu */ |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 99 | write16(spibar + SPIBAR_PREOP, SPI_OPPREFIX); |
| 100 | write16(spibar + SPIBAR_OPTYPE, SPI_OPTYPE); |
| 101 | write32(spibar + SPIBAR_OPMENU_LOWER, SPI_OPMENU_LOWER); |
| 102 | write32(spibar + SPIBAR_OPMENU_UPPER, SPI_OPMENU_UPPER); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 103 | /* Lock SPIBAR */ |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 104 | hsfs = read32(spibar + SPIBAR_HSFS); |
| 105 | hsfs |= SPIBAR_HSFS_FLOCKDN; |
| 106 | write32(spibar + SPIBAR_HSFS, hsfs); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 107 | |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 108 | /*TCO Lock down */ |
Barnali Sarkar | 49eca13 | 2016-08-12 00:05:27 +0530 | [diff] [blame] | 109 | tcobase = smbus_tco_regs(); |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 110 | tcocnt = inw(tcobase + TCO1_CNT); |
| 111 | tcocnt |= TCO_LOCK; |
| 112 | outw(tcocnt, tcobase + TCO1_CNT); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 113 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 114 | /* Lock down ABASE and sleep stretching policy */ |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 115 | dev = PCH_DEV_PMC; |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 116 | reg32 = pci_read_config32(dev, GEN_PMCON_B); |
| 117 | reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK); |
| 118 | pci_write_config32(dev, GEN_PMCON_B, reg32); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 119 | |
| 120 | /* PMSYNC */ |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 121 | pmcbase = pmc_mmio_regs(); |
| 122 | pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); |
| 123 | pmsyncreg |= PMSYNC_LOCK; |
| 124 | write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 125 | |
Dhaval Sharma | 9dca83c | 2016-01-18 17:28:20 +0530 | [diff] [blame] | 126 | /* Display me status before we hide it */ |
| 127 | intel_me_status(); |
| 128 | |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 129 | /* we should disable Heci1 based on the devicetree policy */ |
| 130 | config = dev->chip_info; |
Archana Patni | 6c1bf27 | 2015-12-18 23:38:21 +0530 | [diff] [blame] | 131 | |
| 132 | /* |
| 133 | * Disable ACPI PM timer based on dt policy |
| 134 | * |
| 135 | * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. |
| 136 | * Disabling ACPI PM timer also switches off TCO |
| 137 | */ |
| 138 | |
| 139 | if (config->PmTimerDisabled) { |
| 140 | reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); |
| 141 | reg8 |= (1 << 1); |
| 142 | write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); |
| 143 | } |
| 144 | |
| 145 | /* we should disable Heci1 based on the devicetree policy */ |
Archana Patni | 7846e34 | 2015-11-11 01:29:23 +0530 | [diff] [blame] | 146 | if (config->HeciEnabled == 0) |
| 147 | pch_disable_heci(); |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 148 | } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 149 | |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 150 | static void soc_lockdown(void) |
| 151 | { |
| 152 | u8 reg8; |
| 153 | device_t dev; |
| 154 | const struct device *dev1 = dev_find_slot(0, PCH_DEVFN_LPC); |
| 155 | const struct soc_intel_skylake_config *config = dev1->chip_info; |
| 156 | |
| 157 | /* Global SMI Lock */ |
| 158 | if (config->LockDownConfigGlobalSmi == 0) { |
| 159 | dev = PCH_DEV_PMC; |
| 160 | reg8 = pci_read_config8(dev, GEN_PMCON_A); |
| 161 | reg8 |= SMI_LOCK; |
| 162 | pci_write_config8(dev, GEN_PMCON_A, reg8); |
| 163 | } |
| 164 | |
| 165 | /* Bios Interface Lock */ |
| 166 | if (config->LockDownConfigBiosInterface == 0) { |
| 167 | pci_write_config8(PCH_DEV_LPC, BIOS_CNTL, |
| 168 | pci_read_config8(PCH_DEV_LPC, |
| 169 | BIOS_CNTL) | LPC_BC_BILD); |
| 170 | /* Reads back for posted write to take effect */ |
| 171 | pci_read_config8(PCH_DEV_LPC, BIOS_CNTL); |
| 172 | pci_write_config32(PCH_DEV_SPI, SPIBAR_BIOS_CNTL, |
| 173 | pci_read_config32(PCH_DEV_SPI, |
| 174 | SPIBAR_BIOS_CNTL) | |
| 175 | SPIBAR_BC_BILD); |
| 176 | /* Reads back for posted write to take effect */ |
| 177 | pci_read_config32(PCH_DEV_SPI, SPIBAR_BIOS_CNTL); |
| 178 | /* GCS reg of DMI */ |
| 179 | pcr_andthenor8(PID_DMI, R_PCH_PCR_DMI_GCS, 0xFF, |
| 180 | B_PCH_PCR_DMI_GCS_BILD); |
| 181 | } |
| 182 | |
| 183 | /* Bios Lock */ |
| 184 | if (config->LockDownConfigBiosLock == 0) { |
| 185 | pci_write_config8(PCH_DEV_LPC, BIOS_CNTL, |
| 186 | pci_read_config8(PCH_DEV_LPC, |
| 187 | BIOS_CNTL) | LPC_BC_LE); |
| 188 | pci_write_config8(PCH_DEV_SPI, BIOS_CNTL, |
| 189 | pci_read_config8(PCH_DEV_SPI, |
| 190 | BIOS_CNTL) | SPIBAR_BC_LE); |
| 191 | } |
| 192 | |
| 193 | /* SPIEiss */ |
| 194 | if (config->LockDownConfigSpiEiss == 0) { |
| 195 | pci_write_config8(PCH_DEV_LPC, BIOS_CNTL, |
| 196 | pci_read_config8(PCH_DEV_LPC, |
| 197 | BIOS_CNTL) | LPC_BC_EISS); |
| 198 | pci_write_config8(PCH_DEV_SPI, BIOS_CNTL, |
| 199 | pci_read_config8(PCH_DEV_SPI, |
| 200 | SPIBAR_BIOS_CNTL) | |
| 201 | SPIBAR_BC_EISS); |
| 202 | } |
| 203 | } |
| 204 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 205 | static void soc_finalize(void *unused) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 206 | { |
| 207 | printk(BIOS_DEBUG, "Finalizing chipset.\n"); |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 208 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 209 | pch_finalize_script(); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 210 | |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 211 | soc_lockdown(); |
| 212 | |
Duncan Laurie | 6f0e6fa | 2016-02-09 09:40:39 -0800 | [diff] [blame] | 213 | printk(BIOS_DEBUG, "Finalizing SMM.\n"); |
| 214 | outb(APM_CNT_FINALIZE, APM_CNT); |
| 215 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 216 | /* Indicate finalize step with post code */ |
| 217 | post_code(POST_OS_BOOT); |
| 218 | } |
| 219 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 220 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); |
| 221 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL); |