Werner Zeh | 6c57146 | 2016-07-05 07:16:34 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Mario Scheithauer | a39aede | 2017-11-06 16:47:27 +0100 | [diff] [blame] | 4 | * Copyright (C) 2016-2017 Siemens AG |
Werner Zeh | 6c57146 | 2016-07-05 07:16:34 +0200 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <types.h> |
Werner Zeh | 6c57146 | 2016-07-05 07:16:34 +0200 | [diff] [blame] | 17 | #include <device/pci.h> |
| 18 | #include <device/pci_ids.h> |
| 19 | #include <device/pci_ops.h> |
| 20 | #include <device/pci_def.h> |
| 21 | #include <string.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 22 | #include <device/mmio.h> |
Werner Zeh | 6c57146 | 2016-07-05 07:16:34 +0200 | [diff] [blame] | 23 | #include <delay.h> |
| 24 | #include <hwilib.h> |
Werner Zeh | f1f67c3 | 2017-10-19 07:21:54 +0200 | [diff] [blame] | 25 | #include <bootstate.h> |
Werner Zeh | 6c57146 | 2016-07-05 07:16:34 +0200 | [diff] [blame] | 26 | #include "nc_fpga.h" |
| 27 | |
Werner Zeh | f1f67c3 | 2017-10-19 07:21:54 +0200 | [diff] [blame] | 28 | static void *nc_fpga_bar0; |
| 29 | |
Werner Zeh | 6c57146 | 2016-07-05 07:16:34 +0200 | [diff] [blame] | 30 | #define FPGA_SET_PARAM(src, dst) \ |
| 31 | { \ |
Werner Zeh | 2db7922 | 2017-07-05 15:52:52 +0200 | [diff] [blame] | 32 | uint32_t var; \ |
| 33 | if (hwilib_get_field(src, (uint8_t *)&var, sizeof(var))) \ |
Werner Zeh | d5960c4 | 2017-07-14 10:24:00 +0200 | [diff] [blame] | 34 | dst = ((typeof(dst))var); \ |
Werner Zeh | 6c57146 | 2016-07-05 07:16:34 +0200 | [diff] [blame] | 35 | } |
| 36 | |
| 37 | static void init_temp_mon (void *base_adr) |
| 38 | { |
| 39 | uint32_t cc[5], i = 0; |
| 40 | uint8_t num = 0; |
| 41 | volatile fan_ctrl_t *ctrl = (fan_ctrl_t *)base_adr; |
| 42 | |
| 43 | /* Program sensor delay first. */ |
| 44 | FPGA_SET_PARAM(FANSensorDelay, ctrl->sensordelay); |
| 45 | /* Program correction curve for every used sensor. */ |
Werner Zeh | 2db7922 | 2017-07-05 15:52:52 +0200 | [diff] [blame] | 46 | if ((hwilib_get_field(FANSensorNum, &num, 1) != 1) || |
Werner Zeh | 6c57146 | 2016-07-05 07:16:34 +0200 | [diff] [blame] | 47 | (num == 0) || (num > MAX_NUM_SENSORS)) |
| 48 | return; |
| 49 | for (i = 0; i < num; i ++) { |
| 50 | if (hwilib_get_field(FANSensorCfg0 + i, (uint8_t *)&cc[0], |
| 51 | sizeof(cc)) == sizeof(cc)) { |
| 52 | ctrl->sensorcfg[cc[0]].rmin = cc[1] & 0xffff; |
| 53 | ctrl->sensorcfg[cc[0]].rmax = cc[2] & 0xffff; |
| 54 | ctrl->sensorcfg[cc[0]].nmin = cc[3] & 0xffff; |
| 55 | ctrl->sensorcfg[cc[0]].nmax = cc[4] & 0xffff; |
| 56 | } |
| 57 | } |
| 58 | ctrl->sensornum = num; |
Mario Scheithauer | 0b42c8a | 2017-09-26 13:37:49 +0200 | [diff] [blame] | 59 | |
| 60 | /* Program sensor selection and temperature thresholds. */ |
| 61 | FPGA_SET_PARAM(FANSensorSelect, ctrl->sensorselect); |
| 62 | FPGA_SET_PARAM(T_Warn, ctrl->t_warn); |
| 63 | FPGA_SET_PARAM(T_Crit, ctrl->t_crit); |
Werner Zeh | 6c57146 | 2016-07-05 07:16:34 +0200 | [diff] [blame] | 64 | } |
| 65 | |
| 66 | static void init_fan_ctrl (void *base_adr) |
| 67 | { |
Werner Zeh | 89a7b6b | 2017-06-30 10:38:08 +0200 | [diff] [blame] | 68 | uint8_t mask = 0, freeze_disable = 0, fan_req = 0; |
Werner Zeh | 6c57146 | 2016-07-05 07:16:34 +0200 | [diff] [blame] | 69 | volatile fan_ctrl_t *ctrl = (fan_ctrl_t *)base_adr; |
| 70 | |
| 71 | /* Program all needed fields of FAN controller. */ |
Werner Zeh | 6c57146 | 2016-07-05 07:16:34 +0200 | [diff] [blame] | 72 | FPGA_SET_PARAM(FANSamplingTime, ctrl->samplingtime); |
| 73 | FPGA_SET_PARAM(FANSetPoint, ctrl->setpoint); |
| 74 | FPGA_SET_PARAM(FANHystCtrl, ctrl->hystctrl); |
| 75 | FPGA_SET_PARAM(FANHystVal, ctrl->hystval); |
| 76 | FPGA_SET_PARAM(FANHystThreshold, ctrl->hystthreshold); |
| 77 | FPGA_SET_PARAM(FANKp, ctrl->kp); |
| 78 | FPGA_SET_PARAM(FANKi, ctrl->ki); |
| 79 | FPGA_SET_PARAM(FANKd, ctrl->kd); |
| 80 | FPGA_SET_PARAM(FANMaxSpeed, ctrl->fanmax); |
Werner Zeh | c38ab85 | 2017-07-27 13:48:18 +0200 | [diff] [blame] | 81 | FPGA_SET_PARAM(FANStartSpeed, ctrl->fanmin); |
Werner Zeh | 6c57146 | 2016-07-05 07:16:34 +0200 | [diff] [blame] | 82 | /* Set freeze and FAN configuration. */ |
| 83 | if ((hwilib_get_field(FF_FanReq, &fan_req, 1) == 1) && |
Werner Zeh | 89a7b6b | 2017-06-30 10:38:08 +0200 | [diff] [blame] | 84 | (hwilib_get_field(FF_FreezeDis, &freeze_disable, 1) == 1)) { |
Werner Zeh | 6c57146 | 2016-07-05 07:16:34 +0200 | [diff] [blame] | 85 | if (!fan_req) |
| 86 | mask = 1; |
Elyes HAOUAS | 1943f37 | 2018-05-04 16:30:39 +0200 | [diff] [blame] | 87 | else if (fan_req && !freeze_disable) |
Werner Zeh | 6c57146 | 2016-07-05 07:16:34 +0200 | [diff] [blame] | 88 | mask = 2; |
| 89 | else |
| 90 | mask = 3; |
| 91 | ctrl->fanmon = mask << 10; |
| 92 | } |
| 93 | } |
| 94 | |
| 95 | /** \brief This function is the driver entry point for the init phase |
| 96 | * of the PCI bus allocator. It will initialize all the needed parts |
| 97 | * of NC_FPGA. |
| 98 | * @param *dev Pointer to the used PCI device |
| 99 | * @return void Nothing is given back |
| 100 | */ |
| 101 | static void nc_fpga_init(struct device *dev) |
| 102 | { |
| 103 | void *bar0_ptr = NULL; |
| 104 | uint8_t cmd_reg; |
| 105 | uint32_t cap = 0; |
| 106 | |
| 107 | /* All we need is mapped to BAR 0, get the address. */ |
| 108 | bar0_ptr = (void *)(pci_read_config32(dev, PCI_BASE_ADDRESS_0) & |
| 109 | ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); |
| 110 | cmd_reg = pci_read_config8(dev, PCI_COMMAND); |
| 111 | /* Ensure BAR0 has a valid value. */ |
| 112 | if (!bar0_ptr || !(cmd_reg & PCI_COMMAND_MEMORY)) |
| 113 | return; |
| 114 | /* Ensure this is really a NC FPGA by checking magic register. */ |
| 115 | if (read32(bar0_ptr + NC_MAGIC_OFFSET) != NC_FPGA_MAGIC) |
| 116 | return; |
Werner Zeh | f1f67c3 | 2017-10-19 07:21:54 +0200 | [diff] [blame] | 117 | /* Save BAR0 address so that it can be used on all NC_FPGA devices to |
| 118 | set the FW_DONE bit before jumping to payload. */ |
| 119 | nc_fpga_bar0 = bar0_ptr; |
Werner Zeh | 6c57146 | 2016-07-05 07:16:34 +0200 | [diff] [blame] | 120 | /* Open hwinfo block. */ |
| 121 | if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) |
| 122 | return; |
| 123 | /* Set up FAN controller and temperature monitor according to */ |
| 124 | /* capability bits. */ |
| 125 | cap = read32(bar0_ptr + NC_CAP1_OFFSET); |
| 126 | if (cap & (NC_CAP1_TEMP_MON | NC_CAP1_FAN_CTRL)) |
| 127 | init_temp_mon(bar0_ptr + NC_FANMON_CTRL_OFFSET); |
| 128 | if (cap & NC_CAP1_FAN_CTRL) |
| 129 | init_fan_ctrl(bar0_ptr + NC_FANMON_CTRL_OFFSET); |
Mario Scheithauer | c4ff1de | 2017-06-12 10:02:10 +0200 | [diff] [blame] | 130 | if (cap & NC_CAP1_DSAVE_NMI_DELAY) { |
| 131 | uint16_t *dsave_ptr = (uint16_t *)(bar0_ptr + NC_DSAVE_OFFSET); |
| 132 | FPGA_SET_PARAM(NvramVirtTimeDsaveReset, *dsave_ptr); |
| 133 | } |
| 134 | if (cap & NC_CAP1_BL_BRIGHTNESS_CTRL) { |
| 135 | uint8_t *bl_bn_ptr = |
| 136 | (uint8_t *)(bar0_ptr + NC_BL_BRIGHTNESS_OFFSET); |
| 137 | uint8_t *bl_pwm_ptr = (uint8_t *)(bar0_ptr + NC_BL_PWM_OFFSET); |
| 138 | FPGA_SET_PARAM(BL_Brightness, *bl_bn_ptr); |
| 139 | FPGA_SET_PARAM(PF_PwmFreq, *bl_pwm_ptr); |
| 140 | } |
Werner Zeh | 6c57146 | 2016-07-05 07:16:34 +0200 | [diff] [blame] | 141 | } |
| 142 | |
Werner Zeh | f1f67c3 | 2017-10-19 07:21:54 +0200 | [diff] [blame] | 143 | #if IS_ENABLED(CONFIG_NC_FPGA_NOTIFY_CB_READY) |
| 144 | /* Set FW_DONE bit in FPGA before jumping to payload. */ |
| 145 | static void set_fw_done(void *unused) |
| 146 | { |
| 147 | uint32_t reg; |
| 148 | |
| 149 | if (nc_fpga_bar0) { |
| 150 | reg = read32(nc_fpga_bar0 + NC_DIAG_CTRL_OFFSET); |
| 151 | reg |= NC_DIAG_FW_DONE; |
| 152 | write32(nc_fpga_bar0 + NC_DIAG_CTRL_OFFSET, reg); |
| 153 | } |
| 154 | } |
| 155 | |
| 156 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, set_fw_done, NULL); |
| 157 | #endif |
| 158 | |
Werner Zeh | 6c57146 | 2016-07-05 07:16:34 +0200 | [diff] [blame] | 159 | static struct device_operations nc_fpga_ops = { |
| 160 | .read_resources = pci_dev_read_resources, |
| 161 | .set_resources = pci_dev_set_resources, |
| 162 | .enable_resources = pci_dev_enable_resources, |
| 163 | .init = nc_fpga_init, |
| 164 | .scan_bus = 0, |
| 165 | .ops_pci = 0, |
| 166 | }; |
| 167 | |
Mario Scheithauer | c4ff1de | 2017-06-12 10:02:10 +0200 | [diff] [blame] | 168 | static const unsigned short nc_fpga_device_ids[] = { 0x4080, 0x4091, 0 }; |
Werner Zeh | 6c57146 | 2016-07-05 07:16:34 +0200 | [diff] [blame] | 169 | |
| 170 | static const struct pci_driver nc_fpga_driver __pci_driver = { |
| 171 | .ops = &nc_fpga_ops, |
Mario Scheithauer | c4ff1de | 2017-06-12 10:02:10 +0200 | [diff] [blame] | 172 | .vendor = PCI_VENDOR_ID_SIEMENS, |
Werner Zeh | 6c57146 | 2016-07-05 07:16:34 +0200 | [diff] [blame] | 173 | .devices = nc_fpga_device_ids, |
| 174 | }; |