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Patrick Georgi0588d192009-08-12 15:00:51 +00001##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00002## This file is part of the coreboot project.
Patrick Georgi0588d192009-08-12 15:00:51 +00003##
Alexandru Gagniuc70c660f2012-08-23 02:32:58 -05004## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
Stefan Reinauer16f515a2010-01-20 18:44:30 +00005## Copyright (C) 2009-2010 coresystems GmbH
Patrick Georgi0588d192009-08-12 15:00:51 +00006##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00007## This program is free software; you can redistribute it and/or modify
8## it under the terms of the GNU General Public License as published by
9## the Free Software Foundation; version 2 of the License.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, write to the Free Software
Patrick Georgib890a122015-03-26 15:17:45 +010018## Foundation, Inc.
Patrick Georgi0588d192009-08-12 15:00:51 +000019##
20
Uwe Hermannad8c95f2012-04-12 22:00:03 +020021mainmenu "coreboot configuration"
Patrick Georgi0588d192009-08-12 15:00:51 +000022
Uwe Hermannc04be932009-10-05 13:55:28 +000023menu "General setup"
24
25config LOCALVERSION
Uwe Hermann168b11b2009-10-07 16:15:40 +000026 string "Local version string"
Uwe Hermannc04be932009-10-05 13:55:28 +000027 help
28 Append an extra string to the end of the coreboot version.
29
Uwe Hermann168b11b2009-10-07 16:15:40 +000030 This can be useful if, for instance, you want to append the
31 respective board's hostname or some other identifying string to
32 the coreboot version number, so that you can easily distinguish
33 boot logs of different boards from each other.
34
Patrick Georgi4b8a2412010-02-09 19:35:16 +000035config CBFS_PREFIX
36 string "CBFS prefix to use"
37 default "fallback"
38 help
39 Select the prefix to all files put into the image. It's "fallback"
40 by default, "normal" is a common alternative.
41
Vadim Bendeburyadcb0952014-05-01 12:23:09 -070042config COMMON_CBFS_SPI_WRAPPER
43 bool
44 default n
45 depends on SPI_FLASH
46 depends on !ARCH_X86
47 help
48 Use common wrapper to interface CBFS to SPI bootrom.
49
Vadim Bendebury6bfabce2014-12-25 15:07:22 -080050config MULTIPLE_CBFS_INSTANCES
Martin Roth595e7772015-04-26 18:53:26 -060051 bool "Multiple CBFS instances in the bootrom"
52 default n
53 depends on !ARCH_X86
54 help
55 Account for the firmware image containing more than one CBFS
56 instance. Locations of instances are known at build time and are
57 communicated between coreboot stages to make sure the next stage is
58 loaded from the appropriate instance.
Vadim Bendebury6bfabce2014-12-25 15:07:22 -080059
Patrick Georgi23d89cc2010-03-16 01:17:19 +000060choice
Uwe Hermannad8c95f2012-04-12 22:00:03 +020061 prompt "Compiler to use"
Patrick Georgi23d89cc2010-03-16 01:17:19 +000062 default COMPILER_GCC
63 help
64 This option allows you to select the compiler used for building
65 coreboot.
66
67config COMPILER_GCC
68 bool "GCC"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020069 help
70 Use the GNU Compiler Collection (GCC) to build coreboot.
71
72 For details see http://gcc.gnu.org.
73
Patrick Georgi23d89cc2010-03-16 01:17:19 +000074config COMPILER_LLVM_CLANG
75 bool "LLVM/clang"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020076 help
77 Use LLVM/clang to build coreboot.
78
79 For details see http://clang.llvm.org.
80
Patrick Georgi23d89cc2010-03-16 01:17:19 +000081endchoice
82
Patrick Georgi9b0de712013-12-29 18:45:23 +010083config ANY_TOOLCHAIN
84 bool "Allow building with any toolchain"
85 default n
86 depends on COMPILER_GCC
87 help
88 Many toolchains break when building coreboot since it uses quite
89 unusual linker features. Unless developers explicitely request it,
90 we'll have to assume that they use their distro compiler by mistake.
91 Make sure that using patched compilers is a conscious decision.
92
Patrick Georgi516a2a72010-03-25 21:45:25 +000093config CCACHE
Uwe Hermannad8c95f2012-04-12 22:00:03 +020094 bool "Use ccache to speed up (re)compilation"
Patrick Georgi516a2a72010-03-25 21:45:25 +000095 default n
96 help
97 Enables the use of ccache for faster builds.
Uwe Hermannad8c95f2012-04-12 22:00:03 +020098
99 Requires the ccache utility in your system $PATH.
100
101 For details see https://ccache.samba.org.
Patrick Georgi516a2a72010-03-25 21:45:25 +0000102
Sol Boucher69b88bf2015-02-26 11:47:19 -0800103config FMD_GENPARSER
104 bool "Generate flashmap descriptor parser using flex and bison"
105 default n
Sol Boucher69b88bf2015-02-26 11:47:19 -0800106 help
107 Enable this option if you are working on the flashmap descriptor
108 parser and made changes to fmd_scanner.l or fmd_parser.y.
109
110 Otherwise, say N to use the provided pregenerated scanner/parser.
111
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000112config SCONFIG_GENPARSER
113 bool "Generate SCONFIG parser using flex and bison"
114 default n
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000115 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200116 Enable this option if you are working on the sconfig device tree
Sol Boucher69b88bf2015-02-26 11:47:19 -0800117 parser and made changes to sconfig.l or sconfig.y.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200118
Sol Boucher69b88bf2015-02-26 11:47:19 -0800119 Otherwise, say N to use the provided pregenerated scanner/parser.
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000120
Joe Korty6d772522010-05-19 18:41:15 +0000121config USE_OPTION_TABLE
122 bool "Use CMOS for configuration values"
123 default n
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000124 depends on HAVE_OPTION_TABLE
Joe Korty6d772522010-05-19 18:41:15 +0000125 help
126 Enable this option if coreboot shall read options from the "CMOS"
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200127 NVRAM instead of using hard-coded values.
Joe Korty6d772522010-05-19 18:41:15 +0000128
Timothy Pearsonf20c6e82015-02-14 16:15:31 -0600129config STATIC_OPTION_TABLE
130 bool "Load default configuration values into CMOS on each boot"
131 default n
132 depends on USE_OPTION_TABLE
133 help
134 Enable this option to reset "CMOS" NVRAM values to default on
135 every boot. Use this if you want the NVRAM configuration to
136 never be modified from its default values.
137
Julius Wernercdf92ea2014-12-09 12:18:00 -0800138config UNCOMPRESSED_RAMSTAGE
139 bool
140 default n
141
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000142config COMPRESS_RAMSTAGE
143 bool "Compress ramstage with LZMA"
Julius Wernercdf92ea2014-12-09 12:18:00 -0800144 default y if !UNCOMPRESSED_RAMSTAGE
145 default n
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000146 help
147 Compress ramstage to save memory in the flash image. Note
148 that decompression might slow down booting if the boot flash
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200149 is connected through a slow link (i.e. SPI).
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000150
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200151config INCLUDE_CONFIG_FILE
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200152 bool "Include the coreboot .config file into the ROM image"
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200153 default y
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200154 help
155 Include the .config file that was used to compile coreboot
156 in the (CBFS) ROM image. This is useful if you want to know which
157 options were used to build a specific coreboot.rom image.
158
Daniele Forsi53847a22014-07-22 18:00:56 +0200159 Saying Y here will increase the image size by 2-3KB.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200160
161 You can use the following command to easily list the options:
162
163 grep -a CONFIG_ coreboot.rom
164
165 Alternatively, you can also use cbfstool to print the image
166 contents (including the raw 'config' item we're looking for).
167
168 Example:
169
170 $ cbfstool coreboot.rom print
171 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
172 offset 0x0
173 Alignment: 64 bytes
Steve Goodrichf0269122012-05-18 11:18:47 -0600174
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200175 Name Offset Type Size
176 cmos_layout.bin 0x0 cmos layout 1159
177 fallback/romstage 0x4c0 stage 339756
Daniele Forsi53847a22014-07-22 18:00:56 +0200178 fallback/ramstage 0x53440 stage 186664
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200179 fallback/payload 0x80dc0 payload 51526
180 config 0x8d740 raw 3324
181 (empty) 0x8e480 null 3610440
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200182
Kyösti Mälkkif8bf5a12013-10-11 22:08:02 +0300183config EARLY_CBMEM_INIT
Kyösti Mälkki3bf38542014-12-18 22:22:04 +0200184 def_bool !LATE_CBMEM_INIT
185
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700186config COLLECT_TIMESTAMPS
187 bool "Create a table of timestamps collected during boot"
Kyösti Mälkki26447932013-10-11 21:14:59 +0300188 default n
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700189 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200190 Make coreboot create a table of timer-ID/timer-value pairs to
191 allow measuring time spent at different phases of the boot process.
192
Aaron Durbin1936f6c2015-07-03 17:04:21 -0500193config HAS_PRECBMEM_TIMESTAMP_REGION
194 bool "Timestamp region exists for pre-cbmem timestamps"
195 default y if ARCH_ROMSTAGE_X86_32 && CACHE_AS_RAM
196 depends on COLLECT_TIMESTAMPS
197 help
198 A separate region is maintained to allow storing of timestamps before
199 cbmem comes up. This is useful for storing timestamps across different
200 stage boundaries.
201
Patrick Georgi7e9b9d82012-04-30 21:06:10 +0200202config USE_BLOBS
203 bool "Allow use of binary-only repository"
204 default n
205 help
206 This draws in the blobs repository, which contains binary files that
207 might be required for some chipsets or boards.
208 This flag ensures that a "Free" option remains available for users.
209
Stefan Reinauerd37ab452012-12-18 16:23:28 -0800210config COVERAGE
211 bool "Code coverage support"
212 depends on COMPILER_GCC
213 default n
214 help
215 Add code coverage support for coreboot. This will store code
216 coverage information in CBMEM for extraction from user space.
217 If unsure, say N.
218
Stefan Reinauer58470e32014-10-17 13:08:36 +0200219config RELOCATABLE_MODULES
Vladimir Serbinenko633352c2015-05-30 22:21:37 +0200220 bool
Stefan Reinauer58470e32014-10-17 13:08:36 +0200221 default n
222 help
223 If RELOCATABLE_MODULES is selected then support is enabled for
224 building relocatable modules in the RAM stage. Those modules can be
225 loaded anywhere and all the relocations are handled automatically.
226
227config RELOCATABLE_RAMSTAGE
Vladimir Serbinenko633352c2015-05-30 22:21:37 +0200228 depends on EARLY_CBMEM_INIT
Stefan Reinauer58470e32014-10-17 13:08:36 +0200229 bool "Build the ramstage to be relocatable in 32-bit address space."
230 default n
Vladimir Serbinenko633352c2015-05-30 22:21:37 +0200231 select RELOCATABLE_MODULES
Stefan Reinauer58470e32014-10-17 13:08:36 +0200232 help
233 The reloctable ramstage support allows for the ramstage to be built
234 as a relocatable module. The stage loader can identify a place
235 out of the OS way so that copying memory is unnecessary during an S3
236 wake. When selecting this option the romstage is responsible for
237 determing a stack location to use for loading the ramstage.
238
239config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
240 depends on RELOCATABLE_RAMSTAGE
241 bool "Cache the relocated ramstage outside of cbmem."
242 default n
243 help
244 The relocated ramstage is saved in an area specified by the
245 by the board and/or chipset.
246
Aaron Durbin0424c952015-03-28 23:56:22 -0500247config FLASHMAP_OFFSET
248 hex "Flash Map Offset"
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -0700249 default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC
250 default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
Aaron Durbin0424c952015-03-28 23:56:22 -0500251 default CBFS_SIZE if !ARCH_X86
252 default 0
253 help
254 Offset of flash map in firmware image
255
Stefan Reinauer58470e32014-10-17 13:08:36 +0200256choice
257 prompt "Bootblock behaviour"
258 default BOOTBLOCK_SIMPLE
259
260config BOOTBLOCK_SIMPLE
261 bool "Always load fallback"
262
263config BOOTBLOCK_NORMAL
264 bool "Switch to normal if CMOS says so"
265
266endchoice
267
268config BOOTBLOCK_SOURCE
269 string
270 default "bootblock_simple.c" if BOOTBLOCK_SIMPLE
271 default "bootblock_normal.c" if BOOTBLOCK_NORMAL
272
Timothy Pearson44724082015-03-16 11:47:45 -0500273config SKIP_MAX_REBOOT_CNT_CLEAR
274 bool "Do not clear reboot count after successful boot"
275 default n
Timothy Pearson44724082015-03-16 11:47:45 -0500276 help
277 Do not clear the reboot count immediately after successful boot.
278 Set to allow the payload to control normal/fallback image recovery.
279
Stefan Reinauer58470e32014-10-17 13:08:36 +0200280config UPDATE_IMAGE
281 bool "Update existing coreboot.rom image"
282 default n
283 help
284 If this option is enabled, no new coreboot.rom file
285 is created. Instead it is expected that there already
286 is a suitable file for further processing.
287 The bootblock will not be modified.
288
Stefan Reinauerd06258c2015-03-26 16:29:00 -0700289config GENERIC_GPIO_LIB
290 bool
291 default n
292 help
293 If enabled, compile the generic GPIO library. A "generic" GPIO
294 implies configurability usually found on SoCs, particularly the
295 ability to control internal pull resistors.
296
297config BOARD_ID_AUTO
298 bool
299 default n
300 help
301 Mainboards that can read a board ID from the hardware straps
302 (ie. GPIO) select this configuration option.
303
304config BOARD_ID_MANUAL
305 bool "Add board ID file to CBFS"
306 default n
307 depends on !BOARD_ID_AUTO
308 help
309 If you want to maintain a board ID, but the hardware does not
310 have straps to automatically determine the ID, you can say Y
311 here and add a file named 'board_id' to CBFS. If you don't know
312 what this is about, say N.
313
314config BOARD_ID_STRING
315 string "Board ID"
316 default "(none)"
317 depends on BOARD_ID_MANUAL
318 help
319 This string is placed in the 'board_id' CBFS file for indicating
320 board type.
321
David Hendricks627b3bd2014-11-03 17:42:09 -0800322config RAM_CODE_SUPPORT
323 bool "Discover RAM configuration code and store it in coreboot table"
324 default n
325 help
326 If enabled, coreboot discovers RAM configuration (value obtained by
327 reading board straps) and stores it in coreboot table.
328
Uwe Hermannc04be932009-10-05 13:55:28 +0000329endmenu
330
Alexander Couzens77103792015-04-16 02:03:26 +0200331source "src/acpi/Kconfig"
332
Martin Roth026e4dc2015-06-19 23:17:15 -0600333menu "Mainboard"
334
Stefan Reinauera48ca842015-04-04 01:58:28 +0200335source "src/mainboard/Kconfig"
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000336
Martin Roth026e4dc2015-06-19 23:17:15 -0600337config CBFS_SIZE
338 hex "Size of CBFS filesystem in ROM"
Martin Roth59aa2b12015-06-20 16:17:12 -0600339 default 0x100000 if HAVE_INTEL_FIRMWARE || \
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -0700340 NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC || \
341 NORTHBRIDGE_INTEL_IVYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE || \
342 NORTHBRIDGE_INTEL_SANDYBRIDGE || \
Martin Rothc407cb92015-06-23 19:59:30 -0600343 NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BRASWELL || \
Martin Roth026e4dc2015-06-19 23:17:15 -0600344 SOC_INTEL_BROADWELL
Aaron Durbin2ca127402015-07-30 13:34:29 -0500345 default 0x200000 if SOC_INTEL_SKYLAKE
Martin Roth026e4dc2015-06-19 23:17:15 -0600346 default ROM_SIZE
347 help
348 This is the part of the ROM actually managed by CBFS, located at the
349 end of the ROM (passed through cbfstool -o) on x86 and at at the start
350 of the ROM (passed through cbfstool -s) everywhere else. It defaults
351 to span the whole ROM on all but Intel systems that use an Intel Firmware
352 Descriptor. It can be overridden to make coreboot live alongside other
353 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
354 binaries.
355
356endmenu
357
Vladimir Serbinenkoa9db82f2014-10-16 13:21:47 +0200358config SYSTEM_TYPE_LAPTOP
Martin Roth595e7772015-04-26 18:53:26 -0600359 default n
360 bool
Vladimir Serbinenkoa9db82f2014-10-16 13:21:47 +0200361
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000362menu "Chipset"
363
Duncan Lauried2119762015-06-08 18:11:56 -0700364comment "SoC"
365source "src/soc/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000366comment "CPU"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200367source "src/cpu/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000368comment "Northbridge"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200369source "src/northbridge/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000370comment "Southbridge"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200371source "src/southbridge/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000372comment "Super I/O"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200373source "src/superio/*/Kconfig"
Sven Schnelle7592e8b2011-01-27 11:43:03 +0000374comment "Embedded Controllers"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200375source "src/ec/acpi/Kconfig"
376source "src/ec/*/*/Kconfig"
Marc Jones78687972015-04-22 23:16:31 -0600377source "src/drivers/intel/fsp1_0/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000378
Martin Roth59aa2b12015-06-20 16:17:12 -0600379source "src/southbridge/intel/common/firmware/Kconfig"
Martin Rothe1523ec2015-06-19 22:30:43 -0600380source "src/vendorcode/*/Kconfig"
Martin Roth59aa2b12015-06-20 16:17:12 -0600381
Martin Rothe1523ec2015-06-19 22:30:43 -0600382source "src/arch/*/Kconfig"
383
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000384endmenu
Patrick Georgi0588d192009-08-12 15:00:51 +0000385
Stefan Reinauera48ca842015-04-04 01:58:28 +0200386source "src/device/Kconfig"
Stefan Reinauer95a63962012-11-13 17:00:01 -0800387
Rudolf Marekd9c25492010-05-16 15:31:53 +0000388menu "Generic Drivers"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200389source "src/drivers/*/Kconfig"
Rudolf Marekd9c25492010-05-16 15:31:53 +0000390endmenu
391
Patrick Georgi0770f252015-04-22 13:28:21 +0200392config RTC
393 bool
394 default n
395
Stefan Reinauer7cb01e02013-08-29 16:05:02 -0700396config TPM
397 bool
398 default n
399 select LPC_TPM if ARCH_X86
Gabe Black51edd542013-09-30 23:00:33 -0700400 select I2C_TPM if ARCH_ARM
Furquan Shaikh2af76f42014-04-28 16:39:40 -0700401 select I2C_TPM if ARCH_ARM64
Stefan Reinauer7cb01e02013-08-29 16:05:02 -0700402 help
403 Enable this option to enable TPM support in coreboot.
404
405 If unsure, say N.
406
Kyösti Mälkkieaee6e22014-04-30 01:35:29 +0300407config RAMTOP
408 hex
409 default 0x200000
410 depends on ARCH_X86
411
Patrick Georgi0588d192009-08-12 15:00:51 +0000412config HEAP_SIZE
413 hex
Myles Watson04000f42009-10-16 19:12:49 +0000414 default 0x4000
Patrick Georgi0588d192009-08-12 15:00:51 +0000415
Julius Wernerc3e7c4e2014-09-19 13:18:16 -0700416config STACK_SIZE
417 hex
Thaminda Edirisooriya1daee062015-07-09 13:53:34 -0700418 default 0x0 if (ARCH_RAMSTAGE_ARM || ARCH_RAMSTAGE_MIPS || ARCH_RAMSTAGE_RISCV)
Julius Wernerc3e7c4e2014-09-19 13:18:16 -0700419 default 0x1000
420
Patrick Georgi0588d192009-08-12 15:00:51 +0000421config MAX_CPUS
422 int
423 default 1
424
425config MMCONF_SUPPORT_DEFAULT
426 bool
427 default n
428
429config MMCONF_SUPPORT
430 bool
431 default n
432
Kyösti Mälkki5687fc92013-11-28 18:11:49 +0200433config BOOTMODE_STRAPS
434 bool
435 default n
436
Stefan Reinauera48ca842015-04-04 01:58:28 +0200437source "src/console/Kconfig"
Patrick Georgi0588d192009-08-12 15:00:51 +0000438
439config HAVE_ACPI_RESUME
440 bool
441 default n
442
Patrick Georgi0588d192009-08-12 15:00:51 +0000443config HAVE_HARD_RESET
444 bool
Uwe Hermann748475b2009-10-09 11:47:21 +0000445 default n
Patrick Georgi37bdb872010-02-27 08:39:04 +0000446 help
447 This variable specifies whether a given board has a hard_reset
448 function, no matter if it's provided by board code or chipset code.
449
Aaron Durbina4217912013-04-29 22:31:51 -0500450config HAVE_MONOTONIC_TIMER
451 def_bool n
452 help
453 The board/chipset provides a monotonic timer.
454
Aaron Durbine5e36302014-09-25 10:05:15 -0500455config GENERIC_UDELAY
456 def_bool n
457 depends on HAVE_MONOTONIC_TIMER
458 help
459 The board/chipset uses a generic udelay function utilizing the
460 monotonic timer.
461
Aaron Durbin340ca912013-04-30 09:58:12 -0500462config TIMER_QUEUE
463 def_bool n
464 depends on HAVE_MONOTONIC_TIMER
465 help
Kyösti Mälkkiecd84242013-09-13 07:57:49 +0300466 Provide a timer queue for performing time-based callbacks.
Aaron Durbin340ca912013-04-30 09:58:12 -0500467
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500468config COOP_MULTITASKING
469 def_bool n
Aaron Durbin38c326d2013-05-06 12:22:23 -0500470 depends on TIMER_QUEUE && ARCH_X86
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500471 help
472 Cooperative multitasking allows callbacks to be multiplexed on the
473 main thread of ramstage. With this enabled it allows for multiple
474 execution paths to take place when they have udelay() calls within
475 their code.
476
477config NUM_THREADS
478 int
479 default 4
480 depends on COOP_MULTITASKING
481 help
482 How many execution threads to cooperatively multitask with.
483
Patrick Georgi0588d192009-08-12 15:00:51 +0000484config HAVE_OPTION_TABLE
485 bool
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000486 default n
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000487 help
488 This variable specifies whether a given board has a cmos.layout
489 file containing NVRAM/CMOS bit definitions.
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000490 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
Patrick Georgi0588d192009-08-12 15:00:51 +0000491
Patrick Georgi0588d192009-08-12 15:00:51 +0000492config PIRQ_ROUTE
493 bool
494 default n
495
496config HAVE_SMI_HANDLER
497 bool
498 default n
499
500config PCI_IO_CFG_EXT
501 bool
502 default n
503
504config IOAPIC
505 bool
506 default n
507
Kyösti Mälkki107f72e2014-01-06 11:06:26 +0200508config CACHE_ROM_SIZE_OVERRIDE
Stefan Reinauer5b635792012-08-16 14:05:42 -0700509 hex
Kyösti Mälkki107f72e2014-01-06 11:06:26 +0200510 default 0
Stefan Reinauer5b635792012-08-16 14:05:42 -0700511
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000512# TODO: Can probably be removed once all chipsets have kconfig options for it.
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000513config VIDEO_MB
514 int
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000515 default 0
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000516
Myles Watson45bb25f2009-09-22 18:49:08 +0000517config USE_WATCHDOG_ON_BOOT
518 bool
519 default n
520
521config VGA
522 bool
523 default n
524 help
525 Build board-specific VGA code.
526
527config GFXUMA
528 bool
Myles Watsond73c1b52009-10-26 15:14:07 +0000529 default n
Myles Watson45bb25f2009-09-22 18:49:08 +0000530 help
531 Enable Unified Memory Architecture for graphics.
532
Myles Watsonb8e20272009-10-15 13:35:47 +0000533config HAVE_ACPI_TABLES
534 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000535 help
536 This variable specifies whether a given board has ACPI table support.
537 It is usually set in mainboard/*/Kconfig.
Myles Watsonb8e20272009-10-15 13:35:47 +0000538
539config HAVE_MP_TABLE
540 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000541 help
542 This variable specifies whether a given board has MP table support.
543 It is usually set in mainboard/*/Kconfig.
544 Whether or not the MP table is actually generated by coreboot
545 is configurable by the user via GENERATE_MP_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000546
547config HAVE_PIRQ_TABLE
548 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000549 help
550 This variable specifies whether a given board has PIRQ table support.
551 It is usually set in mainboard/*/Kconfig.
552 Whether or not the PIRQ table is actually generated by coreboot
553 is configurable by the user via GENERATE_PIRQ_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000554
Alexandru Gagniuc70c660f2012-08-23 02:32:58 -0500555config MAX_PIRQ_LINKS
556 int
557 default 4
558 help
559 This variable specifies the number of PIRQ interrupt links which are
560 routable. On most chipsets, this is 4, INTA through INTD. Some
561 chipsets offer more than four links, commonly up to INTH. They may
562 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
563 table specifies links greater than 4, pirq_route_irqs will not
564 function properly, unless this variable is correctly set.
565
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200566config COMMON_FADT
567 bool
568 default n
569
Myles Watsond73c1b52009-10-26 15:14:07 +0000570#These Options are here to avoid "undefined" warnings.
571#The actual selection and help texts are in the following menu.
572
Uwe Hermann168b11b2009-10-07 16:15:40 +0000573menu "System tables"
Myles Watson45bb25f2009-09-22 18:49:08 +0000574
Myles Watsonb8e20272009-10-15 13:35:47 +0000575config GENERATE_MP_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800576 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
577 bool
578 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000579 help
580 Generate an MP table (conforming to the Intel MultiProcessor
581 specification 1.4) for this board.
582
583 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000584
Myles Watsonb8e20272009-10-15 13:35:47 +0000585config GENERATE_PIRQ_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800586 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
587 bool
588 default HAVE_PIRQ_TABLE
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000589 help
590 Generate a PIRQ table for this board.
591
592 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000593
Sven Schnelle164bcfd2011-08-14 20:56:34 +0200594config GENERATE_SMBIOS_TABLES
595 depends on ARCH_X86
596 bool "Generate SMBIOS tables"
597 default y
598 help
599 Generate SMBIOS tables for this board.
600
601 If unsure, say Y.
602
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200603config SMBIOS_PROVIDED_BY_MOBO
604 bool
605 default n
606
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200607config MAINBOARD_SERIAL_NUMBER
608 string "SMBIOS Serial Number"
609 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200610 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200611 default "123456789"
Martin Roth595e7772015-04-26 18:53:26 -0600612 help
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200613 The Serial Number to store in SMBIOS structures.
614
615config MAINBOARD_VERSION
616 string "SMBIOS Version Number"
617 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200618 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200619 default "1.0"
620 help
621 The Version Number to store in SMBIOS structures.
622
623config MAINBOARD_SMBIOS_MANUFACTURER
624 string "SMBIOS Manufacturer"
625 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200626 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200627 default MAINBOARD_VENDOR
628 help
629 Override the default Manufacturer stored in SMBIOS structures.
630
631config MAINBOARD_SMBIOS_PRODUCT_NAME
632 string "SMBIOS Product name"
633 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200634 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200635 default MAINBOARD_PART_NUMBER
636 help
637 Override the default Product name stored in SMBIOS structures.
638
Myles Watson45bb25f2009-09-22 18:49:08 +0000639endmenu
640
Patrick Georgi0588d192009-08-12 15:00:51 +0000641menu "Payload"
642
Patrick Georgi0588d192009-08-12 15:00:51 +0000643choice
Uwe Hermann168b11b2009-10-07 16:15:40 +0000644 prompt "Add a payload"
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000645 default PAYLOAD_NONE if !ARCH_X86
646 default PAYLOAD_SEABIOS if ARCH_X86
Patrick Georgi0588d192009-08-12 15:00:51 +0000647
Uwe Hermann168b11b2009-10-07 16:15:40 +0000648config PAYLOAD_NONE
649 bool "None"
650 help
651 Select this option if you want to create an "empty" coreboot
652 ROM image for a certain mainboard, i.e. a coreboot ROM image
653 which does not yet contain a payload.
654
655 For such an image to be useful, you have to use 'cbfstool'
656 to add a payload to the ROM image later.
657
Patrick Georgi0588d192009-08-12 15:00:51 +0000658config PAYLOAD_ELF
Uwe Hermann168b11b2009-10-07 16:15:40 +0000659 bool "An ELF executable payload"
Patrick Georgi0588d192009-08-12 15:00:51 +0000660 help
661 Select this option if you have a payload image (an ELF file)
662 which coreboot should run as soon as the basic hardware
663 initialization is completed.
664
665 You will be able to specify the location and file name of the
666 payload image later.
Patrick Georgi0588d192009-08-12 15:00:51 +0000667
Stefan Reinauer1a8b7bf2015-06-30 15:58:56 -0700668source "payloads/external/*/Kconfig.name"
Stefan Reinauercc5b3442013-01-15 17:02:58 -0800669
Stefan Reinauerf1939bb2010-12-30 17:39:50 +0000670endchoice
671
Stefan Reinauer1a8b7bf2015-06-30 15:58:56 -0700672source "payloads/external/*/Kconfig"
Stefan Reinauere50952f2011-04-15 03:34:05 +0000673
Stefan Reinauerbccbbe62010-12-19 21:20:14 +0000674config PAYLOAD_FILE
Cristi Magherusanb5034d42009-08-17 14:47:32 +0000675 string "Payload path and filename"
Patrick Georgi0588d192009-08-12 15:00:51 +0000676 depends on PAYLOAD_ELF
677 default "payload.elf"
678 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000679 The path and filename of the ELF executable file to use as payload.
Patrick Georgi0588d192009-08-12 15:00:51 +0000680
Uwe Hermann168b11b2009-10-07 16:15:40 +0000681# TODO: Defined if no payload? Breaks build?
682config COMPRESSED_PAYLOAD_LZMA
683 bool "Use LZMA compression for payloads"
684 default y
Stefan Reinauer1a8b7bf2015-06-30 15:58:56 -0700685 depends on !PAYLOAD_NONE && !PAYLOAD_LINUX
Uwe Hermann168b11b2009-10-07 16:15:40 +0000686 help
687 In order to reduce the size payloads take up in the ROM chip
688 coreboot can compress them using the LZMA algorithm.
689
Peter Stugea758ca22009-09-17 16:21:31 +0000690endmenu
691
Uwe Hermann168b11b2009-10-07 16:15:40 +0000692menu "Debugging"
693
694# TODO: Better help text and detailed instructions.
Patrick Georgi0588d192009-08-12 15:00:51 +0000695config GDB_STUB
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000696 bool "GDB debugging support"
Rudolf Marek65888022012-03-25 20:51:16 +0200697 default n
Patrick Georgi0588d192009-08-12 15:00:51 +0000698 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000699 If enabled, you will be able to set breakpoints for gdb debugging.
Stefan Reinauer8677a232010-12-11 20:33:41 +0000700 See src/arch/x86/lib/c_start.S for details.
Patrick Georgi0588d192009-08-12 15:00:51 +0000701
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200702config GDB_WAIT
703 bool "Wait for a GDB connection"
704 default n
705 depends on GDB_STUB
706 help
707 If enabled, coreboot will wait for a GDB connection.
708
Julius Wernerd82e0cf2015-02-17 17:27:23 -0800709config FATAL_ASSERTS
710 bool "Halt when hitting a BUG() or assertion error"
711 default n
712 help
713 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
714
Stefan Reinauerfe422182012-05-02 16:33:18 -0700715config DEBUG_CBFS
716 bool "Output verbose CBFS debug messages"
717 default n
Stefan Reinauerfe422182012-05-02 16:33:18 -0700718 help
719 This option enables additional CBFS related debug messages.
720
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000721config HAVE_DEBUG_RAM_SETUP
722 def_bool n
723
Uwe Hermann01ce6012010-03-05 10:03:50 +0000724config DEBUG_RAM_SETUP
725 bool "Output verbose RAM init debug messages"
726 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000727 depends on HAVE_DEBUG_RAM_SETUP
Uwe Hermann01ce6012010-03-05 10:03:50 +0000728 help
729 This option enables additional RAM init related debug messages.
730 It is recommended to enable this when debugging issues on your
731 board which might be RAM init related.
732
733 Note: This option will increase the size of the coreboot image.
734
735 If unsure, say N.
736
Patrick Georgie82618d2010-10-01 14:50:12 +0000737config HAVE_DEBUG_CAR
738 def_bool n
739
Peter Stuge5015f792010-11-10 02:00:32 +0000740config DEBUG_CAR
741 def_bool n
742 depends on HAVE_DEBUG_CAR
743
744if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
Uwe Hermanna953f372010-11-10 00:14:32 +0000745# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
746# printk(BIOS_DEBUG, ...) calls.
Patrick Georgie82618d2010-10-01 14:50:12 +0000747config DEBUG_CAR
748 bool "Output verbose Cache-as-RAM debug messages"
749 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000750 depends on HAVE_DEBUG_CAR
Patrick Georgie82618d2010-10-01 14:50:12 +0000751 help
752 This option enables additional CAR related debug messages.
Peter Stuge5015f792010-11-10 02:00:32 +0000753endif
Patrick Georgie82618d2010-10-01 14:50:12 +0000754
Myles Watson80e914ff2010-06-01 19:25:31 +0000755config DEBUG_PIRQ
756 bool "Check PIRQ table consistency"
757 default n
758 depends on GENERATE_PIRQ_TABLE
759 help
760 If unsure, say N.
761
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000762config HAVE_DEBUG_SMBUS
763 def_bool n
764
Uwe Hermann01ce6012010-03-05 10:03:50 +0000765config DEBUG_SMBUS
766 bool "Output verbose SMBus debug messages"
767 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000768 depends on HAVE_DEBUG_SMBUS
Uwe Hermann01ce6012010-03-05 10:03:50 +0000769 help
770 This option enables additional SMBus (and SPD) debug messages.
771
772 Note: This option will increase the size of the coreboot image.
773
774 If unsure, say N.
775
776config DEBUG_SMI
777 bool "Output verbose SMI debug messages"
778 default n
779 depends on HAVE_SMI_HANDLER
Martin Roth3a543182015-09-28 15:27:24 -0600780 select SPI_FLASH_SMM if SPI_CONSOLE
Uwe Hermann01ce6012010-03-05 10:03:50 +0000781 help
782 This option enables additional SMI related debug messages.
783
784 Note: This option will increase the size of the coreboot image.
785
786 If unsure, say N.
787
Stefan Reinauerbc0f7a62010-08-01 15:41:14 +0000788config DEBUG_SMM_RELOCATION
789 bool "Debug SMM relocation code"
790 default n
791 depends on HAVE_SMI_HANDLER
792 help
793 This option enables additional SMM handler relocation related
794 debug messages.
795
796 Note: This option will increase the size of the coreboot image.
797
798 If unsure, say N.
799
Uwe Hermanna953f372010-11-10 00:14:32 +0000800# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
801# printk(BIOS_DEBUG, ...) calls.
802config DEBUG_MALLOC
Stefan Reinauer95a63962012-11-13 17:00:01 -0800803 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
804 bool
Uwe Hermanna953f372010-11-10 00:14:32 +0000805 default n
Uwe Hermanna953f372010-11-10 00:14:32 +0000806 help
807 This option enables additional malloc related debug messages.
808
809 Note: This option will increase the size of the coreboot image.
810
811 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300812
813# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
814# printk(BIOS_DEBUG, ...) calls.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300815config DEBUG_ACPI
Stefan Reinauer95a63962012-11-13 17:00:01 -0800816 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
817 bool
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300818 default n
819 help
820 This option enables additional ACPI related debug messages.
821
822 Note: This option will slightly increase the size of the coreboot image.
823
824 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300825
Uwe Hermanna953f372010-11-10 00:14:32 +0000826# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
827# printk(BIOS_DEBUG, ...) calls.
Myles Watson6c9bc012010-09-07 22:30:15 +0000828config REALMODE_DEBUG
Stefan Reinauer95a63962012-11-13 17:00:01 -0800829 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
830 bool
Myles Watson6c9bc012010-09-07 22:30:15 +0000831 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000832 depends on PCI_OPTION_ROM_RUN_REALMODE
Myles Watson6c9bc012010-09-07 22:30:15 +0000833 help
834 This option enables additional x86emu related debug messages.
835
836 Note: This option will increase the time to emulate a ROM.
837
838 If unsure, say N.
839
Uwe Hermann01ce6012010-03-05 10:03:50 +0000840config X86EMU_DEBUG
841 bool "Output verbose x86emu debug messages"
842 default n
843 depends on PCI_OPTION_ROM_RUN_YABEL
844 help
845 This option enables additional x86emu related debug messages.
846
847 Note: This option will increase the size of the coreboot image.
848
849 If unsure, say N.
850
851config X86EMU_DEBUG_JMP
852 bool "Trace JMP/RETF"
853 default n
854 depends on X86EMU_DEBUG
855 help
856 Print information about JMP and RETF opcodes from x86emu.
857
858 Note: This option will increase the size of the coreboot image.
859
860 If unsure, say N.
861
862config X86EMU_DEBUG_TRACE
863 bool "Trace all opcodes"
864 default n
865 depends on X86EMU_DEBUG
866 help
867 Print _all_ opcodes that are executed by x86emu.
Stefan Reinauer14e22772010-04-27 06:56:47 +0000868
Uwe Hermann01ce6012010-03-05 10:03:50 +0000869 WARNING: This will produce a LOT of output and take a long time.
870
871 Note: This option will increase the size of the coreboot image.
872
873 If unsure, say N.
874
875config X86EMU_DEBUG_PNP
876 bool "Log Plug&Play accesses"
877 default n
878 depends on X86EMU_DEBUG
879 help
880 Print Plug And Play accesses made by option ROMs.
881
882 Note: This option will increase the size of the coreboot image.
883
884 If unsure, say N.
885
886config X86EMU_DEBUG_DISK
887 bool "Log Disk I/O"
888 default n
889 depends on X86EMU_DEBUG
890 help
891 Print Disk I/O related messages.
892
893 Note: This option will increase the size of the coreboot image.
894
895 If unsure, say N.
896
897config X86EMU_DEBUG_PMM
898 bool "Log PMM"
899 default n
900 depends on X86EMU_DEBUG
901 help
902 Print messages related to POST Memory Manager (PMM).
903
904 Note: This option will increase the size of the coreboot image.
905
906 If unsure, say N.
907
908
909config X86EMU_DEBUG_VBE
910 bool "Debug VESA BIOS Extensions"
911 default n
912 depends on X86EMU_DEBUG
913 help
914 Print messages related to VESA BIOS Extension (VBE) functions.
915
916 Note: This option will increase the size of the coreboot image.
917
918 If unsure, say N.
919
920config X86EMU_DEBUG_INT10
921 bool "Redirect INT10 output to console"
922 default n
923 depends on X86EMU_DEBUG
924 help
925 Let INT10 (i.e. character output) calls print messages to debug output.
926
927 Note: This option will increase the size of the coreboot image.
928
929 If unsure, say N.
930
931config X86EMU_DEBUG_INTERRUPTS
932 bool "Log intXX calls"
933 default n
934 depends on X86EMU_DEBUG
935 help
936 Print messages related to interrupt handling.
937
938 Note: This option will increase the size of the coreboot image.
939
940 If unsure, say N.
941
942config X86EMU_DEBUG_CHECK_VMEM_ACCESS
943 bool "Log special memory accesses"
944 default n
945 depends on X86EMU_DEBUG
946 help
947 Print messages related to accesses to certain areas of the virtual
948 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
949
950 Note: This option will increase the size of the coreboot image.
951
952 If unsure, say N.
953
954config X86EMU_DEBUG_MEM
955 bool "Log all memory accesses"
956 default n
957 depends on X86EMU_DEBUG
958 help
959 Print memory accesses made by option ROM.
960 Note: This also includes accesses to fetch instructions.
961
962 Note: This option will increase the size of the coreboot image.
963
964 If unsure, say N.
965
966config X86EMU_DEBUG_IO
967 bool "Log IO accesses"
968 default n
969 depends on X86EMU_DEBUG
970 help
971 Print I/O accesses made by option ROM.
972
973 Note: This option will increase the size of the coreboot image.
974
975 If unsure, say N.
976
Denis 'GNUtoo' Carikli4cdc5d62013-05-15 00:19:49 +0200977config X86EMU_DEBUG_TIMINGS
978 bool "Output timing information"
979 default n
980 depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
981 help
982 Print timing information needed by i915tool.
983
984 If unsure, say N.
985
Stefan Reinauerdfb098d2011-11-17 12:50:54 -0800986config DEBUG_TPM
987 bool "Output verbose TPM debug messages"
988 default n
989 depends on TPM
990 help
991 This option enables additional TPM related debug messages.
992
Stefan Reinauer1c56d9b2012-05-10 11:27:32 -0700993config DEBUG_SPI_FLASH
994 bool "Output verbose SPI flash debug messages"
995 default n
996 depends on SPI_FLASH
997 help
998 This option enables additional SPI flash related debug messages.
999
Kyösti Mälkki3be80cc2013-06-06 10:46:37 +03001000config DEBUG_USBDEBUG
1001 bool "Output verbose USB 2.0 EHCI debug dongle messages"
1002 default n
1003 depends on USBDEBUG
1004 help
1005 This option enables additional USB 2.0 debug dongle related messages.
1006
1007 Select this to debug the connection of usbdebug dongle. Note that
1008 you need some other working console to receive the messages.
1009
Stefan Reinauer8e073822012-04-04 00:07:22 +02001010if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1011# Only visible with the right southbridge and loglevel.
1012config DEBUG_INTEL_ME
1013 bool "Verbose logging for Intel Management Engine"
1014 default n
1015 help
1016 Enable verbose logging for Intel Management Engine driver that
1017 is present on Intel 6-series chipsets.
1018endif
1019
Rudolf Marek7f0e9302011-09-02 23:23:41 +02001020config TRACE
1021 bool "Trace function calls"
1022 default n
1023 help
1024 If enabled, every function will print information to console once
1025 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1026 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
1027 of calling function. Please note some printk releated functions
1028 are omitted from trace to have good looking console dumps.
Stefan Reinauerd37ab452012-12-18 16:23:28 -08001029
1030config DEBUG_COVERAGE
1031 bool "Debug code coverage"
1032 default n
1033 depends on COVERAGE
1034 help
1035 If enabled, the code coverage hooks in coreboot will output some
1036 information about the coverage data that is dumped.
1037
Uwe Hermann168b11b2009-10-07 16:15:40 +00001038endmenu
1039
Myles Watsond73c1b52009-10-26 15:14:07 +00001040# These probably belong somewhere else, but they are needed somewhere.
Myles Watsond73c1b52009-10-26 15:14:07 +00001041config ENABLE_APIC_EXT_ID
1042 bool
1043 default n
Myles Watson2e672732009-11-12 16:38:03 +00001044
1045config WARNINGS_ARE_ERRORS
1046 bool
Edward O'Callaghan63f6dc72014-11-18 03:17:54 +11001047 default y
Patrick Georgi436f99b2009-11-27 16:55:13 +00001048
Peter Stuge51eafde2010-10-13 06:23:02 +00001049# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1050# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1051# mutually exclusive. One of these options must be selected in the
1052# mainboard Kconfig if the chipset supports enabling and disabling of
1053# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1054# in mainboard/Kconfig to know if the button should be enabled or not.
1055
1056config POWER_BUTTON_DEFAULT_ENABLE
1057 def_bool n
1058 help
1059 Select when the board has a power button which can optionally be
1060 disabled by the user.
1061
1062config POWER_BUTTON_DEFAULT_DISABLE
1063 def_bool n
1064 help
1065 Select when the board has a power button which can optionally be
1066 enabled by the user, e.g. when the board ships with a jumper over
1067 the power switch contacts.
1068
1069config POWER_BUTTON_FORCE_ENABLE
1070 def_bool n
1071 help
1072 Select when the board requires that the power button is always
1073 enabled.
1074
1075config POWER_BUTTON_FORCE_DISABLE
1076 def_bool n
1077 help
1078 Select when the board requires that the power button is always
1079 disabled, e.g. when it has been hardwired to ground.
1080
1081config POWER_BUTTON_IS_OPTIONAL
1082 bool
1083 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1084 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1085 help
1086 Internal option that controls ENABLE_POWER_BUTTON visibility.
Duncan Laurie72748002013-10-31 08:26:23 -07001087
1088config REG_SCRIPT
1089 bool
Duncan Laurie72748002013-10-31 08:26:23 -07001090 default n
1091 help
1092 Internal option that controls whether we compile in register scripts.
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07001093
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07001094config MAX_REBOOT_CNT
1095 int
1096 default 3
Timothy Pearson17ada2e2015-03-18 01:31:34 -05001097 help
1098 Internal option that sets the maximum number of bootblock executions allowed
1099 with the normal image enabled before assuming the normal image is defective
Vadim Bendebury9c9c3362014-07-23 09:40:02 -07001100 and switching to the fallback image.