Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 secunet Security Networks AG |
| 5 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 18 | #include <device/pci_ops.h> |
Martin Roth | cbe3892 | 2016-01-05 19:40:41 -0700 | [diff] [blame] | 19 | #include "iomap.h" |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 20 | #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) |
Martin Roth | cbe3892 | 2016-01-05 19:40:41 -0700 | [diff] [blame] | 21 | #include <southbridge/intel/i82801gx/i82801gx.h> /* DEFAULT_PMBASE */ |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 22 | #else |
| 23 | #include <southbridge/intel/i82801jx/i82801jx.h> /* DEFAULT_PMBASE */ |
| 24 | #endif |
Arthur Heymans | eff0c6a | 2016-06-18 21:52:30 +0200 | [diff] [blame] | 25 | #include <pc80/mc146818rtc.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 26 | #include "x4x.h" |
Arthur Heymans | ef7e98a | 2016-12-30 21:07:18 +0100 | [diff] [blame] | 27 | #include <console/console.h> |
Arthur Heymans | ef7e98a | 2016-12-30 21:07:18 +0100 | [diff] [blame] | 28 | #include <romstage_handoff.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 29 | |
| 30 | void x4x_early_init(void) |
| 31 | { |
Antonello Dettori | 60a6e15 | 2016-09-03 10:45:33 +0200 | [diff] [blame] | 32 | const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 33 | |
| 34 | /* Setup MCHBAR. */ |
| 35 | pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1); |
| 36 | |
| 37 | /* Setup DMIBAR. */ |
| 38 | pci_write_config32(d0f0, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1); |
| 39 | |
| 40 | /* Setup EPBAR. */ |
| 41 | pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1); |
| 42 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 43 | /* Setup HECIBAR */ |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 44 | pci_write_config32(PCI_DEV(0, 3, 0), 0x10, DEFAULT_HECIBAR); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 45 | |
| 46 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
| 47 | pci_write_config8(d0f0, D0F0_PAM(0), 0x30); |
| 48 | pci_write_config8(d0f0, D0F0_PAM(1), 0x33); |
| 49 | pci_write_config8(d0f0, D0F0_PAM(2), 0x33); |
| 50 | pci_write_config8(d0f0, D0F0_PAM(3), 0x33); |
| 51 | pci_write_config8(d0f0, D0F0_PAM(4), 0x33); |
| 52 | pci_write_config8(d0f0, D0F0_PAM(5), 0x33); |
| 53 | pci_write_config8(d0f0, D0F0_PAM(6), 0x33); |
| 54 | |
Arthur Heymans | 5e3cb72 | 2017-03-05 10:57:02 +0100 | [diff] [blame] | 55 | if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) { |
| 56 | /* Enable internal GFX */ |
| 57 | pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); |
Arthur Heymans | eff0c6a | 2016-06-18 21:52:30 +0200 | [diff] [blame] | 58 | |
Nico Huber | cfd433b | 2017-05-12 17:10:58 +0200 | [diff] [blame] | 59 | /* Set preallocated IGD size from cmos */ |
| 60 | u8 gfxsize = 6; /* 6 for 64MiB, default if not set in cmos */ |
| 61 | get_option(&gfxsize, "gfx_uma_size"); |
| 62 | if (gfxsize > 12) |
Arthur Heymans | 5e3cb72 | 2017-03-05 10:57:02 +0100 | [diff] [blame] | 63 | gfxsize = 6; |
Arthur Heymans | 16a70a4 | 2017-09-22 12:22:24 +0200 | [diff] [blame] | 64 | /* Need at least 4M for cbmem_top alignment */ |
| 65 | else if (gfxsize < 1) |
| 66 | gfxsize = 1; |
| 67 | /* Set GTT size to 2+2M */ |
| 68 | pci_write_config16(d0f0, D0F0_GGC, 0x0b00 | (gfxsize + 1) << 4); |
Arthur Heymans | 5e3cb72 | 2017-03-05 10:57:02 +0100 | [diff] [blame] | 69 | } else { /* Does not feature internal graphics */ |
| 70 | pci_write_config32(d0f0, D0F0_DEVEN, D0EN | D1EN | PEG1EN); |
| 71 | pci_write_config16(d0f0, D0F0_GGC, (1 << 1)); |
Arthur Heymans | eff0c6a | 2016-06-18 21:52:30 +0200 | [diff] [blame] | 72 | } |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 73 | } |
Arthur Heymans | ef7e98a | 2016-12-30 21:07:18 +0100 | [diff] [blame] | 74 | |
| 75 | static void init_egress(void) |
| 76 | { |
| 77 | u32 reg32; |
| 78 | |
| 79 | /* VC0: TC0 only */ |
| 80 | EPBAR8(0x14) = 1; |
| 81 | EPBAR8(0x4) = 1; |
| 82 | |
| 83 | switch (MCHBAR32(0xc00) & 0x7) { |
| 84 | case 0x0: |
| 85 | /* FSB 1066 */ |
| 86 | EPBAR32(0x2c) = 0x0001a6db; |
| 87 | break; |
| 88 | case 0x2: |
| 89 | /* FSB 800 */ |
| 90 | EPBAR32(0x2c) = 0x00014514; |
| 91 | break; |
| 92 | default: |
| 93 | case 0x4: |
| 94 | /* FSB 1333 */ |
| 95 | EPBAR32(0x2c) = 0x00022861; |
| 96 | break; |
| 97 | } |
| 98 | EPBAR32(0x28) = 0x0a0a0a0a; |
| 99 | EPBAR8(0xc) = (EPBAR8(0xc) & ~0xe) | 2; |
| 100 | EPBAR32(0x1c) = (EPBAR32(0x1c) & ~0x7f0000) | 0x0a0000; |
| 101 | MCHBAR8(0x3c) = MCHBAR8(0x3c) | 0x7; |
| 102 | |
| 103 | /* VC1: ID1, TC7 */ |
| 104 | reg32 = (EPBAR32(0x20) & ~(7 << 24)) | (1 << 24); |
| 105 | reg32 = (reg32 & ~0xfe) | (1 << 7); |
| 106 | EPBAR32(0x20) = reg32; |
| 107 | |
| 108 | /* Init VC1 port arbitration table */ |
| 109 | EPBAR32(0x100) = 0x001000001; |
| 110 | EPBAR32(0x104) = 0x000040000; |
| 111 | EPBAR32(0x108) = 0x000001000; |
| 112 | EPBAR32(0x10c) = 0x000000040; |
| 113 | EPBAR32(0x110) = 0x001000001; |
| 114 | EPBAR32(0x114) = 0x000040000; |
| 115 | EPBAR32(0x118) = 0x000001000; |
| 116 | EPBAR32(0x11c) = 0x000000040; |
| 117 | |
| 118 | /* Load table */ |
| 119 | reg32 = EPBAR32(0x20) | (1 << 16); |
| 120 | EPBAR32(0x20) = reg32; |
| 121 | asm("nop"); |
| 122 | EPBAR32(0x20) = reg32; |
| 123 | |
| 124 | /* Wait for table load */ |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 125 | while ((EPBAR8(0x26) & (1 << 0)) != 0) |
| 126 | ; |
Arthur Heymans | ef7e98a | 2016-12-30 21:07:18 +0100 | [diff] [blame] | 127 | |
| 128 | /* VC1: enable */ |
| 129 | EPBAR32(0x20) |= 1 << 31; |
| 130 | |
| 131 | /* Wait for VC1 */ |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 132 | while ((EPBAR8(0x26) & (1 << 1)) != 0) |
| 133 | ; |
Arthur Heymans | ef7e98a | 2016-12-30 21:07:18 +0100 | [diff] [blame] | 134 | |
| 135 | printk(BIOS_DEBUG, "Done Egress Port\n"); |
| 136 | } |
| 137 | |
| 138 | static void init_dmi(void) |
| 139 | { |
| 140 | u32 reg32; |
Arthur Heymans | ef7e98a | 2016-12-30 21:07:18 +0100 | [diff] [blame] | 141 | |
| 142 | /* Assume IGD present */ |
| 143 | |
| 144 | /* Clear error status */ |
| 145 | DMIBAR32(0x1c4) = 0xffffffff; |
| 146 | DMIBAR32(0x1d0) = 0xffffffff; |
| 147 | |
| 148 | /* VC0: TC0 only */ |
| 149 | DMIBAR8(DMIVC0RCTL) = 1; |
| 150 | DMIBAR8(0x4) = 1; |
| 151 | |
| 152 | /* VC1: ID1, TC7 */ |
| 153 | reg32 = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24); |
| 154 | reg32 = (reg32 & ~0xff) | 1 << 7; |
| 155 | |
| 156 | /* VC1: enable */ |
| 157 | reg32 |= 1 << 31; |
| 158 | reg32 = (reg32 & ~(0x7 << 17)) | (0x4 << 17); |
| 159 | |
| 160 | DMIBAR32(DMIVC1RCTL) = reg32; |
| 161 | |
| 162 | /* Set up VCs in southbridge RCBA */ |
| 163 | RCBA8(0x3022) &= ~1; |
| 164 | |
| 165 | reg32 = (0x5 << 28) | (1 << 6); /* PCIe x4 */ |
| 166 | RCBA32(0x2020) = (RCBA32(0x2020) & ~((0xf << 28) | (0x7 << 6))) | reg32; |
| 167 | |
| 168 | /* Assign VC1 id 1 */ |
| 169 | RCBA32(0x20) = (RCBA32(0x20) & ~(0x7 << 24)) | (1 << 24); |
| 170 | |
| 171 | /* Map TC7 to VC1 */ |
| 172 | RCBA8(0x20) &= 1; |
| 173 | RCBA8(0x20) |= 1 << 7; |
| 174 | |
| 175 | /* Map TC0 to VC0 */ |
| 176 | RCBA8(0x14) &= 1; |
| 177 | |
| 178 | /* Init DMI VC1 port arbitration table */ |
| 179 | RCBA32(0x20) &= 0xfff1ffff; |
| 180 | RCBA32(0x20) |= 1 << 19; |
| 181 | |
| 182 | RCBA32(0x30) = 0x0000000f; |
| 183 | RCBA32(0x34) = 0x000f0000; |
| 184 | RCBA32(0x38) = 0; |
| 185 | RCBA32(0x3c) = 0x000000f0; |
| 186 | RCBA32(0x40) = 0x0f000000; |
| 187 | RCBA32(0x44) = 0; |
| 188 | RCBA32(0x48) = 0x0000f000; |
| 189 | RCBA32(0x4c) = 0; |
| 190 | RCBA32(0x50) = 0x0000000f; |
| 191 | RCBA32(0x54) = 0x000f0000; |
| 192 | RCBA32(0x58) = 0; |
| 193 | RCBA32(0x5c) = 0x000000f0; |
| 194 | RCBA32(0x60) = 0x0f000000; |
| 195 | RCBA32(0x64) = 0; |
| 196 | RCBA32(0x68) = 0x0000f000; |
| 197 | RCBA32(0x6c) = 0; |
| 198 | |
| 199 | RCBA32(0x20) |= 1 << 16; |
| 200 | |
| 201 | /* Enable VC1 */ |
| 202 | RCBA32(0x20) |= 1 << 31; |
| 203 | |
| 204 | /* Wait for VC1 */ |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 205 | while ((RCBA8(0x26) & (1 << 1)) != 0) |
| 206 | ; |
Arthur Heymans | ef7e98a | 2016-12-30 21:07:18 +0100 | [diff] [blame] | 207 | |
| 208 | /* Wait for table load */ |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 209 | while ((RCBA8(0x26) & (1 << 0)) != 0) |
| 210 | ; |
Arthur Heymans | ef7e98a | 2016-12-30 21:07:18 +0100 | [diff] [blame] | 211 | |
| 212 | /* ASPM on DMI link */ |
| 213 | RCBA16(0x1a8) &= ~0x3; |
Elyes HAOUAS | 0c89c1c | 2019-05-20 18:39:27 +0200 | [diff] [blame] | 214 | /* FIXME: Do we need to read RCBA16(0x1a8)? */ |
| 215 | RCBA16(0x1a8); |
Arthur Heymans | ef7e98a | 2016-12-30 21:07:18 +0100 | [diff] [blame] | 216 | RCBA32(0x2010) = (RCBA32(0x2010) & ~(0x3 << 10)) | (1 << 10); |
Elyes HAOUAS | 0c89c1c | 2019-05-20 18:39:27 +0200 | [diff] [blame] | 217 | /* FIXME: Do we need to read RCBA32(0x2010)? */ |
| 218 | RCBA32(0x2010); |
Arthur Heymans | ef7e98a | 2016-12-30 21:07:18 +0100 | [diff] [blame] | 219 | |
| 220 | /* Set up VC1 max time */ |
| 221 | RCBA32(0x1c) = (RCBA32(0x1c) & ~0x7f0000) | 0x120000; |
| 222 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 223 | while ((DMIBAR32(0x26) & (1 << 1)) != 0) |
| 224 | ; |
Arthur Heymans | ef7e98a | 2016-12-30 21:07:18 +0100 | [diff] [blame] | 225 | printk(BIOS_DEBUG, "Done DMI setup\n"); |
| 226 | |
| 227 | /* ASPM on DMI */ |
| 228 | DMIBAR32(0x200) &= ~(0x3 << 26); |
| 229 | DMIBAR16(0x210) = (DMIBAR16(0x210) & ~(0xff7)) | 0x101; |
| 230 | DMIBAR32(0x88) &= ~0x3; |
| 231 | DMIBAR32(0x88) |= 0x3; |
Elyes HAOUAS | 0c89c1c | 2019-05-20 18:39:27 +0200 | [diff] [blame] | 232 | /* FIXME: Do we need to read RCBA16(0x88)? */ |
| 233 | DMIBAR16(0x88); |
Arthur Heymans | ef7e98a | 2016-12-30 21:07:18 +0100 | [diff] [blame] | 234 | } |
| 235 | |
| 236 | static void x4x_prepare_resume(int s3resume) |
| 237 | { |
Arthur Heymans | ef7e98a | 2016-12-30 21:07:18 +0100 | [diff] [blame] | 238 | romstage_handoff_init(s3resume); |
| 239 | } |
| 240 | |
| 241 | void x4x_late_init(int s3resume) |
| 242 | { |
| 243 | init_egress(); |
| 244 | init_dmi(); |
| 245 | x4x_prepare_resume(s3resume); |
| 246 | } |