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Uwe Hermannb80dbf02007-04-22 19:08:13 +00001/*
Stefan Reinauer7e61e452008-01-18 10:35:56 +00002 * This file is part of the coreboot project.
Uwe Hermannb80dbf02007-04-22 19:08:13 +00003 *
4 * Copyright (C) 2005 Linux Networx
5 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
6 * Copyright (C) 2005 Ronald G. Minnich <rminnich@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
Paul Menzela46a7122013-02-23 18:37:27 +010019 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Uwe Hermannb80dbf02007-04-22 19:08:13 +000020 */
Yinghai Lu304f24c2005-07-08 02:56:47 +000021
22#include <console/console.h>
23#include <device/device.h>
24#include <device/pci.h>
25#include <device/pci_ids.h>
26#include <device/cardbus.h>
27
Uwe Hermannd453dd02010-10-18 00:00:57 +000028/*
29 * I don't think this code is quite correct but it is close.
Yinghai Lu304f24c2005-07-08 02:56:47 +000030 * Anyone with a cardbus bridge and a little time should be able
31 * to make it usable quickly. -- Eric Biederman 24 March 2005
32 */
33
34/*
Uwe Hermannd453dd02010-10-18 00:00:57 +000035 * IO should be max 256 bytes. However, since we may have a P2P bridge below
36 * a cardbus bridge, we need 4K.
Yinghai Lu304f24c2005-07-08 02:56:47 +000037 */
Uwe Hermannd453dd02010-10-18 00:00:57 +000038#define CARDBUS_IO_SIZE 4096
39#define CARDBUS_MEM_SIZE (32 * 1024 * 1024)
Yinghai Lu304f24c2005-07-08 02:56:47 +000040
Uwe Hermannd453dd02010-10-18 00:00:57 +000041static void cardbus_record_bridge_resource(device_t dev, resource_t moving,
42 resource_t min_size, unsigned int index, unsigned long type)
Yinghai Lu304f24c2005-07-08 02:56:47 +000043{
Yinghai Lu304f24c2005-07-08 02:56:47 +000044 struct resource *resource;
Uwe Hermanne4870472010-11-04 23:23:47 +000045 unsigned long gran;
46 resource_t step;
Uwe Hermannd453dd02010-10-18 00:00:57 +000047
48 /* Initialize the constraints on the current bus. */
Myles Watson03adcfd2010-06-07 16:51:11 +000049 resource = NULL;
Uwe Hermanne4870472010-11-04 23:23:47 +000050 if (!moving)
51 return;
Uwe Hermannd453dd02010-10-18 00:00:57 +000052
Uwe Hermanne4870472010-11-04 23:23:47 +000053 resource = new_resource(dev, index);
54 resource->size = 0;
55 gran = 0;
56 step = 1;
57 while ((moving & step) == 0) {
58 gran += 1;
59 step <<= 1;
Yinghai Lu304f24c2005-07-08 02:56:47 +000060 }
Uwe Hermanne4870472010-11-04 23:23:47 +000061 resource->gran = gran;
62 resource->align = gran;
63 resource->limit = moving | (step - 1);
64 resource->flags = type;
65
66 /* Don't let the minimum size exceed what we can put in the resource. */
67 if ((min_size - 1) > resource->limit)
68 min_size = resource->limit + 1;
69
70 resource->size = min_size;
Yinghai Lu304f24c2005-07-08 02:56:47 +000071}
72
Uwe Hermannd453dd02010-10-18 00:00:57 +000073static void cardbus_size_bridge_resource(device_t dev, unsigned int index)
Yinghai Lu304f24c2005-07-08 02:56:47 +000074{
75 struct resource *resource;
76 resource_t min_size;
Uwe Hermannd453dd02010-10-18 00:00:57 +000077
Yinghai Lu304f24c2005-07-08 02:56:47 +000078 resource = find_resource(dev, index);
79 if (resource) {
80 min_size = resource->size;
Uwe Hermannd453dd02010-10-18 00:00:57 +000081 /*
82 * Always allocate at least the miniumum size to a
Yinghai Lu304f24c2005-07-08 02:56:47 +000083 * cardbus bridge in case a new card is plugged in.
84 */
Uwe Hermannd453dd02010-10-18 00:00:57 +000085 if (resource->size < min_size)
Yinghai Lu304f24c2005-07-08 02:56:47 +000086 resource->size = min_size;
Yinghai Lu304f24c2005-07-08 02:56:47 +000087 }
88}
89
90void cardbus_read_resources(device_t dev)
91{
92 resource_t moving_base, moving_limit, moving;
93 unsigned long type;
Uwe Hermannd453dd02010-10-18 00:00:57 +000094 u16 ctl;
Ronald G. Minnich43225bc2005-11-22 00:07:02 +000095
Uwe Hermannd453dd02010-10-18 00:00:57 +000096 /* See if needs a card control registers base address. */
Ronald G. Minnich43225bc2005-11-22 00:07:02 +000097
98 pci_get_resource(dev, PCI_BASE_ADDRESS_0);
99
100 compact_resources(dev);
101
Uwe Hermannd453dd02010-10-18 00:00:57 +0000102 /* See which bridge I/O resources are implemented. */
103 moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_0);
Yinghai Lu304f24c2005-07-08 02:56:47 +0000104 moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_0);
105 moving = moving_base & moving_limit;
106
Uwe Hermannd453dd02010-10-18 00:00:57 +0000107 /* Initialize the I/O space constraints on the current bus. */
Yinghai Lu304f24c2005-07-08 02:56:47 +0000108 cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE,
Uwe Hermannd453dd02010-10-18 00:00:57 +0000109 PCI_CB_IO_BASE_0, IORESOURCE_IO);
Yinghai Lu304f24c2005-07-08 02:56:47 +0000110 cardbus_size_bridge_resource(dev, PCI_CB_IO_BASE_0);
111
Uwe Hermannd453dd02010-10-18 00:00:57 +0000112 /* See which bridge I/O resources are implemented. */
113 moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_1);
Yinghai Lu304f24c2005-07-08 02:56:47 +0000114 moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_1);
115 moving = moving_base & moving_limit;
116
Uwe Hermannd453dd02010-10-18 00:00:57 +0000117 /* Initialize the I/O space constraints on the current bus. */
Yinghai Lu304f24c2005-07-08 02:56:47 +0000118 cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE,
Uwe Hermannd453dd02010-10-18 00:00:57 +0000119 PCI_CB_IO_BASE_1, IORESOURCE_IO);
Yinghai Lu304f24c2005-07-08 02:56:47 +0000120
Uwe Hermannd453dd02010-10-18 00:00:57 +0000121 /* If I can, enable prefetch for mem0. */
Yinghai Lu304f24c2005-07-08 02:56:47 +0000122 ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
123 ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
124 ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
125 ctl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
126 pci_write_config16(dev, PCI_CB_BRIDGE_CONTROL, ctl);
127 ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
128
Uwe Hermannd453dd02010-10-18 00:00:57 +0000129 /* See which bridge memory resources are implemented. */
130 moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_0);
Yinghai Lu304f24c2005-07-08 02:56:47 +0000131 moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_0);
132 moving = moving_base & moving_limit;
133
Uwe Hermannd453dd02010-10-18 00:00:57 +0000134 /* Initialize the memory space constraints on the current bus. */
Yinghai Lu304f24c2005-07-08 02:56:47 +0000135 type = IORESOURCE_MEM;
Uwe Hermannd453dd02010-10-18 00:00:57 +0000136 if (ctl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)
Yinghai Lu304f24c2005-07-08 02:56:47 +0000137 type |= IORESOURCE_PREFETCH;
Yinghai Lu304f24c2005-07-08 02:56:47 +0000138 cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE,
Uwe Hermannd453dd02010-10-18 00:00:57 +0000139 PCI_CB_MEMORY_BASE_0, type);
140 if (type & IORESOURCE_PREFETCH)
Yinghai Lu304f24c2005-07-08 02:56:47 +0000141 cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_0);
Yinghai Lu304f24c2005-07-08 02:56:47 +0000142
Uwe Hermannd453dd02010-10-18 00:00:57 +0000143 /* See which bridge memory resources are implemented. */
144 moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_1);
Yinghai Lu304f24c2005-07-08 02:56:47 +0000145 moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_1);
146 moving = moving_base & moving_limit;
147
Uwe Hermannd453dd02010-10-18 00:00:57 +0000148 /* Initialize the memory space constraints on the current bus. */
Yinghai Lu304f24c2005-07-08 02:56:47 +0000149 cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE,
Uwe Hermannd453dd02010-10-18 00:00:57 +0000150 PCI_CB_MEMORY_BASE_1, IORESOURCE_MEM);
Yinghai Lu304f24c2005-07-08 02:56:47 +0000151 cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_1);
152
153 compact_resources(dev);
154}
155
156void cardbus_enable_resources(device_t dev)
157{
Uwe Hermannd453dd02010-10-18 00:00:57 +0000158 u16 ctrl;
159
Yinghai Lu304f24c2005-07-08 02:56:47 +0000160 ctrl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
Myles Watson894a3472010-06-09 22:41:35 +0000161 ctrl |= (dev->link_list->bridge_ctrl & (
Stefan Reinauer14e22772010-04-27 06:56:47 +0000162 PCI_BRIDGE_CTL_PARITY |
163 PCI_BRIDGE_CTL_SERR |
Yinghai Lu304f24c2005-07-08 02:56:47 +0000164 PCI_BRIDGE_CTL_NO_ISA |
165 PCI_BRIDGE_CTL_VGA |
166 PCI_BRIDGE_CTL_MASTER_ABORT |
167 PCI_BRIDGE_CTL_BUS_RESET));
Uwe Hermannd453dd02010-10-18 00:00:57 +0000168 /* Error check */
169 ctrl |= (PCI_CB_BRIDGE_CTL_PARITY + PCI_CB_BRIDGE_CTL_SERR);
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000170 printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
Yinghai Lu304f24c2005-07-08 02:56:47 +0000171 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
172
173 pci_dev_enable_resources(dev);
Yinghai Lu304f24c2005-07-08 02:56:47 +0000174}
175
Yinghai Lu304f24c2005-07-08 02:56:47 +0000176struct device_operations default_cardbus_ops_bus = {
177 .read_resources = cardbus_read_resources,
178 .set_resources = pci_dev_set_resources,
179 .enable_resources = cardbus_enable_resources,
Uwe Hermannd453dd02010-10-18 00:00:57 +0000180 .init = 0,
181 .scan_bus = pci_scan_bridge,
Yinghai Lu304f24c2005-07-08 02:56:47 +0000182 .enable = 0,
183 .reset_bus = pci_bus_reset,
184};