blob: c08e8a084646e755ca7ec38f990c2b52c820bd6f [file] [log] [blame]
Uwe Hermann5211a702010-09-27 17:53:17 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
Paul Menzela46a7122013-02-23 18:37:27 +010017 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Uwe Hermann5211a702010-09-27 17:53:17 +000018 */
Eric Biedermanfcd5ace2004-10-14 19:29:29 +000019
Uwe Hermann5211a702010-09-27 17:53:17 +000020__fpu_start:
21 /* Preserve BIST. */
22 movl %eax, %ebp
23
24 /*
25 * Clear the CR0[2] bit (the "Emulation" flag, EM).
26 *
27 * This indicates that the processor has an (internal or external)
28 * x87 FPU, i.e. floating point operations will be executed by the
29 * hardware (and not emulated in software).
30 *
31 * Additionally, if this bit is not cleared, MMX/SSE instructions won't
32 * work, i.e., they will trigger an invalid opcode exception (#UD).
33 */
Eric Biedermanfcd5ace2004-10-14 19:29:29 +000034 movl %cr0, %eax
Uwe Hermann5211a702010-09-27 17:53:17 +000035 andl $~(1 << 2), %eax
Eric Biedermanfcd5ace2004-10-14 19:29:29 +000036 movl %eax, %cr0
37
Uwe Hermann5211a702010-09-27 17:53:17 +000038 /* Restore BIST. */
39 movl %ebp, %eax