blob: 2571e81c35638be03932d40442acddc5615dac04 [file] [log] [blame]
David Hendricks2fba5e22013-03-14 19:06:11 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2013 Google Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
David Hendricks08e36562013-03-25 15:02:29 -070028 *
29 * cache.h: Cache maintenance API for ARMv7
David Hendricks2fba5e22013-03-14 19:06:11 -070030 */
31
32#ifndef ARMV7_CACHE_H
33#define ARMV7_CACHE_H
34
35/* SCTLR bits */
36#define SCTLR_M (1 << 0) /* MMU enable */
37#define SCTLR_A (1 << 1) /* Alignment check enable */
38#define SCTLR_C (1 << 2) /* Data/unified cache enable */
39/* Bits 4:3 are reserved */
40#define SCTLR_CP15BEN (1 << 5) /* CP15 barrier enable */
41/* Bit 6 is reserved */
42#define SCTLR_B (1 << 7) /* Endianness */
43/* Bits 9:8 */
44#define SCTLR_SW (1 << 10) /* SWP and SWPB enable */
45#define SCTLR_Z (1 << 11) /* Branch prediction enable */
46#define SCTLR_I (1 << 12) /* Instruction cache enable */
47#define SCTLR_V (1 << 13) /* Low/high exception vectors */
48#define SCTLR_RR (1 << 14) /* Round Robin select */
49/* Bits 16:15 are reserved */
50#define SCTLR_HA (1 << 17) /* Hardware Access flag enable */
51/* Bit 18 is reserved */
52/* Bits 20:19 reserved virtualization not supported */
53#define SCTLR_WXN (1 << 19) /* Write permission implies XN */
54#define SCTLR_UWXN (1 << 20) /* Unprivileged write permission
55 implies PL1 XN */
56#define SCTLR_FI (1 << 21) /* Fast interrupt config enable */
57#define SCTLR_U (1 << 22) /* Unaligned access behavior */
58#define SCTLR_VE (1 << 24) /* Interrupt vectors enable */
59#define SCTLR_EE (1 << 25) /* Exception endianness */
60/* Bit 26 is reserved */
61#define SCTLR_NMFI (1 << 27) /* Non-maskable FIQ support */
62#define SCTLR_TRE (1 << 28) /* TEX remap enable */
63#define SCTLR_AFE (1 << 29) /* Access flag enable */
64#define SCTLR_TE (1 << 30) /* Thumb exception enable */
65/* Bit 31 is reserved */
66
67/*
68 * Sync primitives
69 */
70
71/* data memory barrier */
72static inline void dmb(void)
73{
74 asm volatile ("dmb" : : : "memory");
75}
76
77/* data sync barrier */
78static inline void dsb(void)
79{
80 asm volatile ("dsb" : : : "memory");
81}
82
83/* instruction sync barrier */
84static inline void isb(void)
85{
86 asm volatile ("isb" : : : "memory");
87}
88
89/*
90 * Low-level TLB maintenance operations
91 */
92
93/* invalidate entire data TLB */
94static inline void dtlbiall(void)
95{
David Hendricks08e36562013-03-25 15:02:29 -070096 asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0) : "memory");
David Hendricks2fba5e22013-03-14 19:06:11 -070097}
98
99/* invalidate entire instruction TLB */
100static inline void itlbiall(void)
101{
102 asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
103}
104
105/* invalidate entire unified TLB */
106static inline void tlbiall(void)
107{
David Hendricks08e36562013-03-25 15:02:29 -0700108 asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0) : "memory");
109}
110
111/* write data access control register (DACR) */
112static inline void write_dacr(uint32_t val)
113{
114 asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (val));
115}
116
117/* write translation table base register 0 (TTBR0) */
118static inline void write_ttbr0(uint32_t val)
119{
120 asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (val) : "memory");
121}
122
123/* read translation table base control register (TTBCR) */
124static inline uint32_t read_ttbcr(void)
125{
126 uint32_t val = 0;
127 asm volatile ("mrc p15, 0, %0, c2, c0, 2" : "=r" (val));
128 return val;
129}
130
131/* write translation table base control register (TTBCR) */
132static inline void write_ttbcr(uint32_t val)
133{
134 asm volatile ("mcr p15, 0, %0, c2, c0, 2" : : "r" (val) : "memory");
David Hendricks2fba5e22013-03-14 19:06:11 -0700135}
136
137/*
138 * Low-level cache maintenance operations
139 */
140
141/* branch predictor invalidate all */
142static inline void bpiall(void)
143{
144 asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
145}
146
147/* data cache clean and invalidate by MVA to PoC */
148static inline void dccimvac(unsigned long mva)
149{
David Hendricks08e36562013-03-25 15:02:29 -0700150 asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva) : "memory");
David Hendricks2fba5e22013-03-14 19:06:11 -0700151}
152
153/* data cache invalidate by set/way */
154static inline void dccisw(uint32_t val)
155{
David Hendricks08e36562013-03-25 15:02:29 -0700156 asm volatile ("mcr p15, 0, %0, c7, c14, 2" : : "r" (val) : "memory");
David Hendricks2fba5e22013-03-14 19:06:11 -0700157}
158
159/* data cache clean by MVA to PoC */
160static inline void dccmvac(unsigned long mva)
161{
David Hendricks08e36562013-03-25 15:02:29 -0700162 asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva) : "memory");
David Hendricks2fba5e22013-03-14 19:06:11 -0700163}
164
165/* data cache invalidate by MVA to PoC */
166static inline void dcimvac(unsigned long mva)
167{
David Hendricks08e36562013-03-25 15:02:29 -0700168 asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva) : "memory");
169}
170
171/* data cache invalidate by set/way */
172static inline void dcisw(uint32_t val)
173{
174 asm volatile ("mcr p15, 0, %0, c7, c6, 2" : : "r" (val) : "memory");
David Hendricks2fba5e22013-03-14 19:06:11 -0700175}
176
177/* instruction cache invalidate all by PoU */
178static inline void iciallu(void)
179{
180 asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
181}
182
183/*
184 * Cache co-processor (CP15) access functions
185 */
186
187/* read cache level ID register (CLIDR) */
188static inline uint32_t read_clidr(void)
189{
190 uint32_t val = 0;
191 asm volatile ("mrc p15, 1, %0, c0, c0, 1" : "=r" (val));
192 return val;
193}
194
195/* read cache size ID register register (CCSIDR) */
196static inline uint32_t read_ccsidr(void)
197{
198 uint32_t val = 0;
199 asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (val));
200 return val;
201}
202
203/* read cache size selection register (CSSELR) */
204static inline uint32_t read_csselr(void)
205{
206 uint32_t val = 0;
207 asm volatile ("mrc p15, 2, %0, c0, c0, 0" : "=r" (val));
208 return val;
209}
210
211/* write to cache size selection register (CSSELR) */
212static inline void write_csselr(uint32_t val)
213{
214 /*
215 * Bits [3:1] - Cache level + 1 (0b000 = L1, 0b110 = L7, 0b111 is rsvd)
216 * Bit 0 - 0 = data or unified cache, 1 = instruction cache
217 */
218 asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (val));
219 isb(); /* ISB to sync the change to CCSIDR */
220}
221
David Hendricks6119bea2013-03-29 13:24:29 -0700222/* read L2 control register (L2CTLR) */
223static inline uint32_t read_l2ctlr(void)
David Hendricks2fba5e22013-03-14 19:06:11 -0700224{
David Hendricks6119bea2013-03-29 13:24:29 -0700225 uint32_t val = 0;
226 asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
227 return val;
228}
229
230/* write L2 control register (L2CTLR) */
231static inline void write_l2ctlr(uint32_t val)
232{
233 /*
234 * Note: L2CTLR can only be written when the L2 memory system
235 * is idle, ie before the MMU is enabled.
236 */
237 asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory" );
238 isb();
239}
240
241/* read system control register (SCTLR) */
242static inline uint32_t read_sctlr(void)
243{
244 uint32_t val;
David Hendricks08e36562013-03-25 15:02:29 -0700245 asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val));
David Hendricks2fba5e22013-03-14 19:06:11 -0700246 return val;
247}
248
249/* write system control register (SCTLR) */
David Hendricks08e36562013-03-25 15:02:29 -0700250static inline void write_sctlr(uint32_t val)
David Hendricks2fba5e22013-03-14 19:06:11 -0700251{
252 asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val) : "cc");
253 isb();
254}
255
256/*
257 * Cache maintenance API
258 */
259
David Hendricks08e36562013-03-25 15:02:29 -0700260/* dcache clean and invalidate all (on current level given by CCSELR) */
David Hendricks2fba5e22013-03-14 19:06:11 -0700261void dcache_clean_invalidate_all(void);
262
David Hendricks08e36562013-03-25 15:02:29 -0700263/* dcache clean by modified virtual address to PoC */
264void dcache_clean_by_mva(unsigned long addr, unsigned long len);
David Hendricks2fba5e22013-03-14 19:06:11 -0700265
David Hendricks08e36562013-03-25 15:02:29 -0700266/* dcache clean and invalidate by modified virtual address to PoC */
David Hendricks2fba5e22013-03-14 19:06:11 -0700267void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len);
268
Hung-Te Lincb0aeef2013-07-08 12:27:13 +0800269/* dcache invalidate by modified virtual address to PoC */
270void dcache_invalidate_by_mva(unsigned long addr, unsigned long len);
271
David Hendricks08e36562013-03-25 15:02:29 -0700272/* dcache invalidate all (on current level given by CCSELR) */
273void dcache_invalidate_all(void);
274
275/* dcache and MMU disable */
276void dcache_mmu_disable(void);
277
278/* dcache and MMU enable */
279void dcache_mmu_enable(void);
280
281/* icache invalidate all (on current level given by CSSELR) */
David Hendricks2fba5e22013-03-14 19:06:11 -0700282void icache_invalidate_all(void);
283
David Hendricks08e36562013-03-25 15:02:29 -0700284/* tlb invalidate all */
285void tlb_invalidate_all(void);
286
287/*
288 * Generalized setup/init functions
289 */
290
291/* invalidate all caches on ARMv7 */
292void armv7_invalidate_caches(void);
293
294/* mmu initialization (set page table address, set permissions, etc) */
295void mmu_init(void);
296
297enum dcache_policy {
298 DCACHE_OFF,
299 DCACHE_WRITEBACK,
300 DCACHE_WRITETHROUGH,
301};
302
303/* mmu range configuration (set dcache policy) */
304void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
305 enum dcache_policy policy);
David Hendricks2fba5e22013-03-14 19:06:11 -0700306
307#endif /* ARMV7_CACHE_H */