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Edward O'Callaghan32960e32014-11-23 17:38:52 +11001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Edward O'Callaghan32960e32014-11-23 17:38:52 +110014 */
15
16/**
17 * @file
18 *
19 * AMD User options selection for a Brazos platform solution system
20 *
21 * This file is placed in the user's platform directory and contains the
22 * build option selections desired for that platform.
23 *
24 * For Information about this file, see @ref platforminstall.
25 *
Edward O'Callaghan32960e32014-11-23 17:38:52 +110026 */
27
28#include "mainboard.h"
29
30#include <stdlib.h>
31
32#include <vendorcode/amd/agesa/f15tn/AGESA.h>
33
34/* Include the files that instantiate the configuration definitions. */
35#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
Edward O'Callaghan32960e32014-11-23 17:38:52 +110036#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
37#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
38#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
39/* AGESA nonesense: the next two headers depend on heapManager.h */
40#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
41#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
42/* These tables are optional and may be used to adjust memory timing settings */
43#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
44#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
45
Edward O'Callaghan32960e32014-11-23 17:38:52 +110046
Elyes HAOUAS8ab989e2016-07-30 17:46:17 +020047/* Select the CPU family. */
Edward O'Callaghan32960e32014-11-23 17:38:52 +110048#define INSTALL_FAMILY_10_SUPPORT FALSE
49#define INSTALL_FAMILY_12_SUPPORT FALSE
50#define INSTALL_FAMILY_14_SUPPORT FALSE
51#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
52
Elyes HAOUAS8ab989e2016-07-30 17:46:17 +020053/* Select the CPU socket type. */
Edward O'Callaghan32960e32014-11-23 17:38:52 +110054#define INSTALL_G34_SOCKET_SUPPORT FALSE
55#define INSTALL_C32_SOCKET_SUPPORT FALSE
56#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
57#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
58#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
59#define INSTALL_FS1_SOCKET_SUPPORT TRUE
60#define INSTALL_FM1_SOCKET_SUPPORT FALSE
61#define INSTALL_FP2_SOCKET_SUPPORT TRUE
62#define INSTALL_FT1_SOCKET_SUPPORT FALSE
63#define INSTALL_AM3_SOCKET_SUPPORT FALSE
64
65#define INSTALL_FM2_SOCKET_SUPPORT FALSE
66
67//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
68//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
69#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
70//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
71//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
72//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
73#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
74#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
75#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
76//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
77#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
78//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
79#define BLDOPT_REMOVE_SRAT FALSE //TRUE
80#define BLDOPT_REMOVE_SLIT FALSE //TRUE
81#define BLDOPT_REMOVE_WHEA FALSE //TRUE
82#define BLDOPT_REMOVE_CRAT TRUE
83#define BLDOPT_REMOVE_DMI TRUE
84//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
85//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
86//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
87//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
88//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
89//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
90
91//This element selects whether P-States should be forced to be independent,
92// as reported by the ACPI _PSD object. For single-link processors,
93// setting TRUE for OS to support this feature.
94
95//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
96
97#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
98#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
99/* Build configuration values here.
100 */
101#define BLDCFG_VRM_CURRENT_LIMIT 90000
102#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
103#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0
104#define BLDCFG_PLAT_NUM_IO_APICS 3
105#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
106#define BLDCFG_MEM_INIT_PSTATE 0
107
108#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
109
110#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
111#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
112#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
113#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
114#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
115#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
116#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
117#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
118#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
119#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
120#define BLDCFG_MEMORY_POWER_DOWN TRUE
121#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
122#define BLDCFG_ONLINE_SPARE FALSE
123#define BLDCFG_BANK_SWIZZLE TRUE
124#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
125#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
126#define BLDCFG_DQS_TRAINING_CONTROL TRUE
127#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
128#define BLDCFG_USE_BURST_MODE FALSE
129#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
130#define BLDCFG_ENABLE_ECC_FEATURE TRUE
131#define BLDCFG_ECC_REDIRECTION FALSE
132#define BLDCFG_SCRUB_DRAM_RATE 0
133#define BLDCFG_SCRUB_L2_RATE 0
134#define BLDCFG_SCRUB_L3_RATE 0
135#define BLDCFG_SCRUB_IC_RATE 0
136#define BLDCFG_SCRUB_DC_RATE 0
137#define BLDCFG_ECC_SYMBOL_SIZE 4
138#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
139#define BLDCFG_ECC_SYNC_FLOOD FALSE
140#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
141#define BLDCFG_1GB_ALIGN FALSE
142#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
143#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36%
144#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770
145
146#define BLDOPT_REMOVE_ALIB FALSE
147#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled
148#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
149#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
150#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
151
152#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200
153#define BLDCFG_CFG_ABM_SUPPORT 0
154
155//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
156
157// Specify the default values for the VRM controlling the VDDNB plane.
158// If not specified, the values used for the core VRM will be applied
159//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity
160//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
161//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime
162//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity
163//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity
164//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
165
166#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
167
168#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
169#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
170
Martin Roth356b5192017-06-24 21:53:37 -0600171#if IS_ENABLED(CONFIG_GFXUMA)
Edward O'Callaghan32960e32014-11-23 17:38:52 +1100172#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
173#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
174//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
175#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
176#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
177#endif
178
Edward O'Callaghan14581fc62014-12-05 04:25:44 +1100179#define BLDCFG_IOMMU_SUPPORT TRUE
Edward O'Callaghan32960e32014-11-23 17:38:52 +1100180
181#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
182//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
183//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
184//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
185
186/* Process the options...
187 * This file include MUST occur AFTER the user option selection settings
188 */
Edward O'Callaghan32960e32014-11-23 17:38:52 +1100189/*
190 * Customized OEM build configurations for FCH component
191 */
192// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
193// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
194// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
195// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
196// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
197// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
198// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
199// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
200// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
201// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
202// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
203// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
204// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
205// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
206// #define BLDCFG_AZALIA_SSID 0x780D1022
207// #define BLDCFG_SMBUS_SSID 0x780B1022
208// #define BLDCFG_IDE_SSID 0x780C1022
209// #define BLDCFG_SATA_AHCI_SSID 0x78011022
210// #define BLDCFG_SATA_IDE_SSID 0x78001022
211// #define BLDCFG_SATA_RAID5_SSID 0x78031022
212// #define BLDCFG_SATA_RAID_SSID 0x78021022
213// #define BLDCFG_EHCI_SSID 0x78081022
214// #define BLDCFG_OHCI_SSID 0x78071022
215// #define BLDCFG_LPC_SSID 0x780E1022
216// #define BLDCFG_SD_SSID 0x78061022
217// #define BLDCFG_XHCI_SSID 0x78121022
218// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
219// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
220// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
221// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
222// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
223// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
224// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
225// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
226// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
227// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
228// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
229
230CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
231{
232 { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
233 { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
234 { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
235 { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
236 { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
237 { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
238 { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
239 { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
240 { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
241 { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
242 { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
243 { CPU_LIST_TERMINAL }
244};
245
246#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
247
248 // This is the delivery package title, "BrazosPI"
249 // This string MUST be exactly 8 characters long
250#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
251
252 // This is the release version number of the AGESA component
253 // This string MUST be exactly 12 characters long
254#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
255
256/* MEMORY_BUS_SPEED */
257#define DDR400_FREQUENCY 200 ///< DDR 400
258#define DDR533_FREQUENCY 266 ///< DDR 533
259#define DDR667_FREQUENCY 333 ///< DDR 667
260#define DDR800_FREQUENCY 400 ///< DDR 800
261#define DDR1066_FREQUENCY 533 ///< DDR 1066
262#define DDR1333_FREQUENCY 667 ///< DDR 1333
263#define DDR1600_FREQUENCY 800 ///< DDR 1600
264#define DDR1866_FREQUENCY 933 ///< DDR 1866
265#define DDR2100_FREQUENCY 1050 ///< DDR 2100
266#define DDR2133_FREQUENCY 1066 ///< DDR 2133
267#define DDR2400_FREQUENCY 1200 ///< DDR 2400
268#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
269
270/* QUANDRANK_TYPE*/
271#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
272#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
273
274/* USER_MEMORY_TIMING_MODE */
275#define TIMING_MODE_AUTO 0 ///< Use best rate possible
276#define TIMING_MODE_LIMITED 1 ///< Set user top limit
277#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
278
279/* POWER_DOWN_MODE */
280#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
281#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
282
283/*
284 * Agesa optional capabilities selection.
285 * Uncomment and mark FALSE those features you wish to include in the build.
286 * Comment out or mark TRUE those features you want to REMOVE from the build.
287 */
288
289#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
290#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
291#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
292#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
293#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
294#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
295#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
296#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
297#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
298#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
299#define DFLT_HPET_BASE_ADDRESS 0xFED00000
300#define DFLT_SMI_CMD_PORT 0xB0
301#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
302#define DFLT_GEC_BASE_ADDRESS 0xFED61000
303#define DFLT_AZALIA_SSID 0x780D1022
304#define DFLT_SMBUS_SSID 0x780B1022
305#define DFLT_IDE_SSID 0x780C1022
306#define DFLT_SATA_AHCI_SSID 0x78011022
307#define DFLT_SATA_IDE_SSID 0x78001022
308#define DFLT_SATA_RAID5_SSID 0x78031022
309#define DFLT_SATA_RAID_SSID 0x78021022
310#define DFLT_EHCI_SSID 0x78081022
311#define DFLT_OHCI_SSID 0x78071022
312#define DFLT_LPC_SSID 0x780E1022
313#define DFLT_SD_SSID 0x78061022
314#define DFLT_XHCI_SSID 0x78121022
315#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
316#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
317#define DFLT_FCH_GPP_LINK_CONFIG PortA4
318#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
319#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
320#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
321#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
322#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
323#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
324#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
325#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
326//#define BLDCFG_IR_PIN_CONTROL 0x33
327
328/*
329 * The GPIO control is not well documented in AGESA, but is in the BKDG
330 *
331 * Eg. FANIN1/GPIO57 on datasheet means power-on default (Function0) is to route
332 * from this ball to hardware monitor as FAN1 tacho input. Selecting Function1
333 * routes this to the GPIO block instead. Seems ACPI GPIOs and related GEVENTs
334 * are mostly in Function1, sometimes Function2.
335 *
336 * Note that the GpioOut bit does not mean that the GPIO is an output. That bit
337 * actually controls the output value, so GpioOut means "default to set".
338 * PullUpB is an inverted logic, so setting this bit means we're actually
339 * disabling the internal pull-up. The PullDown bit is NOT inverted logic.
340 * The output driver can be disabled with the GpioOutEnB bit, which is again,
341 * inverted logic. To make the list more readable, we define a few local macros
342 * to state what we mean.
343 */
344#define OUTPUT_HIGH (GpioOut)
345#define OUTPUT_LOW (0)
346#define INPUT (GpioOutEnB)
347#define PULL_UP (0)
348#define PULL_DOWN (PullDown | PullUpB)
349#define PULL_NONE (PullUpB)
350
351GPIO_CONTROL lenovo_g505s_gpio[] = {
352 {57, Function1, OUTPUT_HIGH | PULL_NONE}, /* WLAN enable */
353 {-1}
354};
355#define BLDCFG_FCH_GPIO_CONTROL_LIST (&lenovo_g505s_gpio[0])
356
357
358/* These definitions could be moved to a common Hudson header, should we decide
359 * to provide our own, saner SCI mapping function
360 */
361#define GEVENT_PIN(gpe) ((gpe) + 0x40)
362#define SCI_MAP_OHCI_12_0 0x58
363#define SCI_MAP_OHCI_13_0 0x59
364#define SCI_MAP_XHCI_10_0 0x78
365#define SCI_MAP_PWRBTN 0x73
366
Edward O'Callaghanc5c21d32014-12-06 05:07:33 +1100367SCI_MAP_CONTROL lenovo_g505s_sci_map[] = {
Edward O'Callaghan32960e32014-11-23 17:38:52 +1100368 {GEVENT_PIN( EC_SCI_GEVENT ), EC_SCI_GPE},
369 {GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE},
370 {GEVENT_PIN( PCIE_GEVENT ), PCIE_GPE},
371 {SCI_MAP_OHCI_12_0, PME_GPE},
372 {SCI_MAP_OHCI_13_0, PME_GPE},
373 {SCI_MAP_XHCI_10_0, PME_GPE},
374 {SCI_MAP_PWRBTN, PME_GPE},
375};
Edward O'Callaghanc5c21d32014-12-06 05:07:33 +1100376#define BLDCFG_FCH_SCI_MAP_LIST (&lenovo_g505s_sci_map[0])
Edward O'Callaghan32960e32014-11-23 17:38:52 +1100377
378// The following definitions specify the default values for various parameters in which there are
379// no clearly defined defaults to be used in the common file. The values below are based on product
380// and BKDG content, please consult the AGESA Memory team for consultation.
381#define DFLT_SCRUB_DRAM_RATE (0)
382#define DFLT_SCRUB_L2_RATE (0)
383#define DFLT_SCRUB_L3_RATE (0)
384#define DFLT_SCRUB_IC_RATE (0)
385#define DFLT_SCRUB_DC_RATE (0)
386#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
387#define DFLT_VRM_SLEW_RATE (5000)
388
389/* AGESA nonsense: this header depends on the definitions above */
Kyösti Mälkkic8e47422017-08-31 08:52:12 +0300390#include <PlatformInstall.h>